public inbox for linux-edac@vger.kernel.org
 help / color / mirror / Atom feed
From: Alison Schofield <alison.schofield@intel.com>
To: <shiju.jose@huawei.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
	<dave@stgolabs.net>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <linux-edac@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <bp@alien8.de>,
	<tony.luck@intel.com>, <lenb@kernel.org>, <Yazen.Ghannam@amd.com>,
	<mchehab@kernel.org>, <nifan.cxl@gmail.com>,
	<linuxarm@huawei.com>, <tanxiaofei@huawei.com>,
	<prime.zeng@hisilicon.com>, <roberto.sassu@huawei.com>,
	<kangkang.shen@futurewei.com>, <wanghuiqiang@huawei.com>
Subject: Re: [PATCH v5 0/8] cxl: support CXL memory RAS features
Date: Mon, 19 May 2025 18:36:01 -0700	[thread overview]
Message-ID: <aCvcgUv03XUWtYKS@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250515115927.772-1-shiju.jose@huawei.com>

On Thu, May 15, 2025 at 12:59:16PM +0100, shiju.jose@huawei.com wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Support for CXL memory EDAC features: patrol scrub, ECS, soft-PPR and
> memory sparing.

snip

> 
> Shiju Jose (8):
>   EDAC: Update documentation for the CXL memory patrol scrub control
>     feature
>   cxl: Update prototype of function get_support_feature_info()
>   cxl/edac: Add CXL memory device patrol scrub control feature
>   cxl/edac: Add CXL memory device ECS control feature
>   cxl/edac: Add support for PERFORM_MAINTENANCE command
>   cxl/edac: Support for finding memory operation attributes from the
>     current boot
>   cxl/edac: Add CXL memory device memory sparing control feature
>   cxl/edac: Add CXL memory device soft PPR control feature
> 
>  Documentation/edac/memory_repair.rst |   31 +
>  Documentation/edac/scrub.rst         |   76 +
>  drivers/cxl/Kconfig                  |   71 +
>  drivers/cxl/core/Makefile            |    1 +
>  drivers/cxl/core/core.h              |    2 +
>  drivers/cxl/core/edac.c              | 2082 ++++++++++++++++++++++++++

Hi Shiju, 

The file edac.c contains a scattering of ifdef's that can be replaced
with the IS_ENABLED() mechanism.

This issue touches many patches, looks like patches 3-7 all added to edac.c.

See Documentation/process/coding-style.rst  "Conditional Compilation".
You'll find a few usage example in drivers/cxl/ and of course many more
all over the kernel.

Conversely, in cxlmem.h, the patch uses IS_ENABLED() where an #ifdef
is perfectly fine and expected. See the surrounding ifdef's in cxlmem.h

I'm aware it's not a simple search and replace operation to rework this
but it is worth doing now to make the code more readable forever, and
there's also the benefit of allowing the compiler to check code inside
the block for correctness.

-- Alison

>  drivers/cxl/core/features.c          |   17 +-
>  drivers/cxl/core/mbox.c              |   11 +-
>  drivers/cxl/core/memdev.c            |    1 +
>  drivers/cxl/core/region.c            |   10 +
>  drivers/cxl/cxl.h                    |   10 +
>  drivers/cxl/cxlmem.h                 |   36 +
>  drivers/cxl/mem.c                    |    4 +
>  drivers/edac/mem_repair.c            |    9 +
>  include/linux/edac.h                 |    7 +
>  15 files changed, 2356 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/cxl/core/edac.c
> 
> -- 
> 2.43.0
> 

  parent reply	other threads:[~2025-05-20  1:36 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15 11:59 [PATCH v5 0/8] cxl: support CXL memory RAS features shiju.jose
2025-05-15 11:59 ` [PATCH v5 1/8] EDAC: Update documentation for the CXL memory patrol scrub control feature shiju.jose
2025-05-15 17:18   ` Randy Dunlap
2025-05-15 11:59 ` [PATCH v5 2/8] cxl: Update prototype of function get_support_feature_info() shiju.jose
2025-05-15 11:59 ` [PATCH v5 3/8] cxl/edac: Add CXL memory device patrol scrub control feature shiju.jose
2025-05-20  2:02   ` Alison Schofield
2025-05-20 10:21     ` Jonathan Cameron
2025-05-20 23:44     ` Shiju Jose
2025-05-15 11:59 ` [PATCH v5 4/8] cxl/edac: Add CXL memory device ECS " shiju.jose
2025-05-15 11:59 ` [PATCH v5 5/8] cxl/edac: Add support for PERFORM_MAINTENANCE command shiju.jose
2025-05-15 11:59 ` [PATCH v5 6/8] cxl/edac: Support for finding memory operation attributes from the current boot shiju.jose
2025-05-20  4:31   ` Alison Schofield
2025-05-20 23:45     ` Shiju Jose
2025-05-15 11:59 ` [PATCH v5 7/8] cxl/edac: Add CXL memory device memory sparing control feature shiju.jose
2025-05-19 21:01   ` Alison Schofield
2025-05-19 21:15     ` Dave Jiang
2025-05-19 21:34       ` Shiju Jose
2025-05-15 11:59 ` [PATCH v5 8/8] cxl/edac: Add CXL memory device soft PPR " shiju.jose
2025-05-15 17:23   ` Randy Dunlap
2025-05-20  1:36 ` Alison Schofield [this message]
2025-05-20 23:44   ` [PATCH v5 0/8] cxl: support CXL memory RAS features Shiju Jose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aCvcgUv03XUWtYKS@aschofie-mobl2.lan \
    --to=alison.schofield@intel.com \
    --cc=Yazen.Ghannam@amd.com \
    --cc=bp@alien8.de \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dave@stgolabs.net \
    --cc=ira.weiny@intel.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=kangkang.shen@futurewei.com \
    --cc=lenb@kernel.org \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-edac@vger.kernel.org \
    --cc=linuxarm@huawei.com \
    --cc=mchehab@kernel.org \
    --cc=nifan.cxl@gmail.com \
    --cc=prime.zeng@hisilicon.com \
    --cc=roberto.sassu@huawei.com \
    --cc=shiju.jose@huawei.com \
    --cc=tanxiaofei@huawei.com \
    --cc=tony.luck@intel.com \
    --cc=vishal.l.verma@intel.com \
    --cc=wanghuiqiang@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox