[PATCH v4 0/7] Add RZ/G3E pinctrl support

[PATCH v4 0/7] Add RZ/G3E pinctrl support

[Biju Das]

Add pin controller support for the Renesas RZ/G3E(R9A09G047) SoC. The
RZ/G3E PFC is similar to the RZ/V2H SoC but has more pins(P00-PS3).
The port number on both RZ/V2H and RZ/G3E is alpha-numeric compared to
the number on the other SoCs. So added support for defining alpha-numeric
port names.

v3->v4:
 * Added new header file with separate RZV2H_P* and RZG3E_P* definitions.
 * Dropped ack tag from Conor for patch#2 as there is separate file for
   RZG3E_P* definitions.
 * Included header file renesas,r9a09g057-pinctrl.h
 * Updated r9a09g057_variable_pin_cfg table replacing PORT_PB->RZV2H_PB
   macro.
 * Included header file renesas,r9a09g047-pinctrl.h
 * Replaced macros PORT_P*->RZG3E_P* 
 * Updated rzg3e_gpio_names table with NULL port names for ports
   corresponding to unsupported hardware indices.
 * Updated r9a09g047_gpio_configs table with NULL value for ports
   corresponding to unsupported hardware indices.
 * Collected Rb tag from Geert for dts changes.
v2->v3:
 * Added alpha-numerical port name support to both RZ/V2H and RZ/G3E.
 * Added PORT_P* macros based on PFC_P_mn offset and RZ{G3E,V2H}_*
   macros for defining port names in DT.  
 * Collected tags.
 * Updated r9a09g057_variable_pin_cfg table replacing port 11 with PORT_PB.
 * Replaced macros WDTUDF_CA->WDTUDFCA and WDTUDF_CM->WDTUDFCM.
 * Replaced macro QSD0_*->SD0*.
 * Updated gpio range from 176->232 to match the port number based
   on hardware indices.
v1->v2:
 * Updated typo of the patch header RZ/G2L->RZ/G3E
 * Fixed the binding warnings reported by bot.

Biju Das (7):
  dt-bindings: pinctrl: renesas: Add alpha-numerical port support for
    RZ/V2H
  dt-bindings: pinctrl: renesas: Document RZ/G3E SoC
  pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table
  pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Replace RZG2L macros
  arm64: dts: renesas: r9a09g047: Add pincontrol node
  arm64: dts: renesas: r9a09g047: Add scif pincontrol

 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   7 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  13 ++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  13 ++
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  36 ++--
 drivers/pinctrl/renesas/Kconfig               |   1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 186 +++++++++++++++++-
 .../pinctrl/renesas,r9a09g047-pinctrl.h       |  41 ++++
 .../pinctrl/renesas,r9a09g057-pinctrl.h       |  31 +++
 8 files changed, 302 insertions(+), 26 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h

-- 
2.43.0

[PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
ports in DT using RZV2H_* macros.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Added new header file with separate RZV2H_P* definitions.
v3:
 * New patch.
---
 .../pinctrl/renesas,r9a09g057-pinctrl.h       | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h

diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
new file mode 100644
index 000000000000..9008a7e71609
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H
+#define __DT_BINDINGS_RZV2H_PINCTRL_H
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZV2H_P0	0
+#define RZV2H_P1	1
+#define RZV2H_P2	2
+#define RZV2H_P3	3
+#define RZV2H_P4	4
+#define RZV2H_P5	5
+#define RZV2H_P6	6
+#define RZV2H_P7	7
+#define RZV2H_P8	8
+#define RZV2H_P9	9
+#define RZV2H_PA	10
+#define RZV2H_PB	11
+
+#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
+#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)
+
+#endif /* __DT_BINDINGS_RZV2H_PINCTRL_H */
-- 
2.43.0

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Krzysztof Kozlowski]

On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
> ports in DT using RZV2H_* macros.

So this is only for DT? Not really a binding. Binding binds
driver implementation with DTS and you do not have here driver.

Calling it a binding makes it immutable and gives us, DT maintainers,
more work, so really no benefits at all.

I guess other DT maintainers will ack it, I prefer to reduce number of
headers.

Best regards,
Krzysztof

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 17 December 2024 06:32
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> > RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> > alpha-numerical ports in DT using RZV2H_* macros.
> 
> So this is only for DT? Not really a binding. Binding binds driver implementation with DTS and you do
> not have here driver.

Please see patch [1], see how this definition binds driver implementation with DTS

[1] https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.renesas.com/

> 
> Calling it a binding makes it immutable and gives us, DT maintainers, more work, so really no benefits
> at all.

> 
> I guess other DT maintainers will ack it, I prefer to reduce number of headers.

DT describes hardware. The port names are alpha numeric on hardware manual.

For example, consider the case of  hardware pin PS1 mentioned in hardware manual.

With current changes,
pinmux = <RZG3E_PORT_PINMUX(S, 1, 0)>;

With existing code
pinmux = <RZG3E_PORT_PINMUX(28, 1, 0)>;

What do you prefer here? 28 is just a number derived from hardware indices
Or actual port name PS1 as mentioned in hardware manual?

Cheers,
Biju 

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Krzysztof Kozlowski]

On 17/12/2024 08:29, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
> Thanks for the feedback.
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 17 December 2024 06:32
>> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
>>
>> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
>>> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
>>> alpha-numerical ports in DT using RZV2H_* macros.
>>
>> So this is only for DT? Not really a binding. Binding binds driver implementation with DTS and you do
>> not have here driver.
> 
> Please see patch [1], see how this definition binds driver implementation with DTS
> 
> [1] https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.renesas.com/

I don't know what is this patch, it is not part of these series
addressed to me and commit msg says "in DT". If you want to receive
meaningful review, make it easier for reviewers.


> 
>>
>> Calling it a binding makes it immutable and gives us, DT maintainers, more work, so really no benefits
>> at all.
> 
>>
>> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
> 
> DT describes hardware. The port names are alpha numeric on hardware manual.

We talk about binding, not DT.

> 
> For example, consider the case of  hardware pin PS1 mentioned in hardware manual.
> 
> With current changes,
> pinmux = <RZG3E_PORT_PINMUX(S, 1, 0)>;
> 
> With existing code
> pinmux = <RZG3E_PORT_PINMUX(28, 1, 0)>;

Based on this pure code: still not a binding.

> 
> What do you prefer here? 28 is just a number derived from hardware indices

Let me ask rhetorical question: if 28 hardware constant is suitable for
binding, then why are you not defining GPIO numbers, IRQ numbers and
MMIO addresses as bindings as well?

> Or actual port name PS1 as mentioned in hardware manual?

Well, I don't know. Commit says DTS, no driver patches here in my inbox,
so what do I know?

Best regards,
Krzysztof

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 17 December 2024 07:51
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> On 17/12/2024 08:29, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> > Thanks for the feedback.
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 17 December 2024 06:32
> >> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add
> >> alpha-numerical port support for RZ/V2H
> >>
> >> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> >>> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> >>> alpha-numerical ports in DT using RZV2H_* macros.
> >>
> >> So this is only for DT? Not really a binding. Binding binds driver
> >> implementation with DTS and you do not have here driver.
> >
> > Please see patch [1], see how this definition binds driver
> > implementation with DTS
> >
> > [1]
> > https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.ren
> > esas.com/
> 
> I don't know what is this patch, it is not part of these series addressed to me and commit msg says
> "in DT". If you want to receive meaningful review, make it easier for reviewers.

The header files are part of DT bindings. So if it is wrong, why the 
Commit "997daa8de64ccbb" "dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings"
is part of bindings?



> 
> 
> >
> >>
> >> Calling it a binding makes it immutable and gives us, DT maintainers,
> >> more work, so really no benefits at all.
> >
> >>
> >> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
> >
> > DT describes hardware. The port names are alpha numeric on hardware manual.
> 
> We talk about binding, not DT.

Bu the definitions are part of bindings just like Commit "997daa8de64ccbb".

> 
> >
> > For example, consider the case of  hardware pin PS1 mentioned in hardware manual.
> >
> > With current changes,
> > pinmux = <RZG3E_PORT_PINMUX(S, 1, 0)>;
> >
> > With existing code
> > pinmux = <RZG3E_PORT_PINMUX(28, 1, 0)>;
> 
> Based on this pure code: still not a binding.

I agree. Macro converted to a number which binding care of.

> 
> >
> > What do you prefer here? 28 is just a number derived from hardware
> > indices
> 
> Let me ask rhetorical question: if 28 hardware constant is suitable for binding, then why are you not
> defining GPIO numbers, IRQ numbers and MMIO addresses as bindings as well?

On RZ/G2L all ports are in numbers not an issue. But on RZ/V2H an RZ/G3E
hardware manual just talks about Port {0..8} {A..H}{J..M}{S}. Hardware constant 28 is just derived one.

A device user just refer, hardware manual and pinctrl list and put the definitions on binding.
He does not need to undergo mapping for alpha numeric to hardware index conversion.


> 
> > Or actual port name PS1 as mentioned in hardware manual?
> 
> Well, I don't know. Commit says DTS, no driver patches here in my inbox, so what do I know?

OK, It is just definitions, so you mean it has to merge with driver + dts patch. so it won't
create any confusion and we can ignore check patch warning, "binding patch should be
Separate patch"

What about then merging this patch with [2] and [3] similar to [4], 

[2] https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.renesas.com/
[3] https://lore.kernel.org/all/20241216195325.164212-6-biju.das.jz@bp.renesas.com/

[4] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings?h=next-20241217&id=ecc79ab919ec54c658fb14f955c76872119829b8

Cheers,
Biju

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Krzysztof Kozlowski]

On 17/12/2024 09:49, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 17 December 2024 07:51
>> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
>>
>> On 17/12/2024 08:29, Biju Das wrote:
>>> Hi Krzysztof Kozlowski,
>>>
>>> Thanks for the feedback.
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <krzk@kernel.org>
>>>> Sent: 17 December 2024 06:32
>>>> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add
>>>> alpha-numerical port support for RZ/V2H
>>>>
>>>> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
>>>>> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
>>>>> alpha-numerical ports in DT using RZV2H_* macros.
>>>>
>>>> So this is only for DT? Not really a binding. Binding binds driver
>>>> implementation with DTS and you do not have here driver.
>>>
>>> Please see patch [1], see how this definition binds driver
>>> implementation with DTS
>>>
>>> [1]
>>> https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.ren
>>> esas.com/
>>
>> I don't know what is this patch, it is not part of these series addressed to me and commit msg says
>> "in DT". If you want to receive meaningful review, make it easier for reviewers.
> 
> The header files are part of DT bindings. So if it is wrong, why the 
> Commit "997daa8de64ccbb" "dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings"
> is part of bindings?

I meant that driver patch you linked.

> 
> 
> 
>>
>>
>>>
>>>>
>>>> Calling it a binding makes it immutable and gives us, DT maintainers,
>>>> more work, so really no benefits at all.
>>>
>>>>
>>>> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
>>>
>>> DT describes hardware. The port names are alpha numeric on hardware manual.
>>
>> We talk about binding, not DT.
> 
> Bu the definitions are part of bindings just like Commit "997daa8de64ccbb".

You made them part of bindings, but this is invalid as argument. How is
this anyhow related? How is "DT describes hardware" part of binding?

You said "DT describes hardware", but we do not talk here about DT, do
we? We talk about binding.


> 
>>
>>>
>>> For example, consider the case of  hardware pin PS1 mentioned in hardware manual.
>>>
>>> With current changes,
>>> pinmux = <RZG3E_PORT_PINMUX(S, 1, 0)>;
>>>
>>> With existing code
>>> pinmux = <RZG3E_PORT_PINMUX(28, 1, 0)>;
>>
>> Based on this pure code: still not a binding.
> 
> I agree. Macro converted to a number which binding care of.
> 
>>
>>>
>>> What do you prefer here? 28 is just a number derived from hardware
>>> indices
>>
>> Let me ask rhetorical question: if 28 hardware constant is suitable for binding, then why are you not
>> defining GPIO numbers, IRQ numbers and MMIO addresses as bindings as well?
> 
> On RZ/G2L all ports are in numbers not an issue. But on RZ/V2H an RZ/G3E
> hardware manual just talks about Port {0..8} {A..H}{J..M}{S}. Hardware constant 28 is just derived one.
> 
> A device user just refer, hardware manual and pinctrl list and put the definitions on binding.
> He does not need to undergo mapping for alpha numeric to hardware index conversion.

You just described something entirely else than binding, so why are you
using this as an argument?

> 
> 
>>
>>> Or actual port name PS1 as mentioned in hardware manual?
>>
>> Well, I don't know. Commit says DTS, no driver patches here in my inbox, so what do I know?
> 
> OK, It is just definitions, so you mean it has to merge with driver + dts patch. so it won't
> create any confusion and we can ignore check patch warning, "binding patch should be
> Separate patch"
> 
> What about then merging this patch with [2] and [3] similar to [4], 
> 
> [2] https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.renesas.com/
> [3] https://lore.kernel.org/all/20241216195325.164212-6-biju.das.jz@bp.renesas.com/

I am not going to keep reading all the external references you keep
bringing or discussing why someone else did something. This patch must
be logical and correct on its own, not because someone else made
something somewhere.

> 
> [4] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/include/dt-bindings?h=next-20241217&id=ecc79ab919ec54c658fb14f955c76872119829b8

Again, I did not see any driver using this, nothing in commit msg
explained this except referencing that DT will use it. Maybe your
patchset is wrongly organized? Maybe commit msg is incorrect? Not sure,
as I said, you got such review you helped me to make.


Best regards,
Krzysztof

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 17 December 2024 09:00
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> On 17/12/2024 09:49, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 17 December 2024 07:51
> >> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add
> >> alpha-numerical port support for RZ/V2H
> >>
> >> On 17/12/2024 08:29, Biju Das wrote:
> >>> Hi Krzysztof Kozlowski,
> >>>
> >>> Thanks for the feedback.
> >>>
> >>>> -----Original Message-----
> >>>> From: Krzysztof Kozlowski <krzk@kernel.org>
> >>>> Sent: 17 December 2024 06:32
> >>>> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add
> >>>> alpha-numerical port support for RZ/V2H
> >>>>
> >>>> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> >>>>> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> >>>>> alpha-numerical ports in DT using RZV2H_* macros.
> >>>>
> >>>> So this is only for DT? Not really a binding. Binding binds driver
> >>>> implementation with DTS and you do not have here driver.
> >>>
> >>> Please see patch [1], see how this definition binds driver
> >>> implementation with DTS
> >>>
> >>> [1]
> >>> https://lore.kernel.org/all/20241216195325.164212-4-biju.das.jz@bp.r
> >>> en
> >>> esas.com/
> >>
> >> I don't know what is this patch, it is not part of these series
> >> addressed to me and commit msg says "in DT". If you want to receive meaningful review, make it
> easier for reviewers.
> >
> > The header files are part of DT bindings. So if it is wrong, why the
> > Commit "997daa8de64ccbb" "dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings"
> > is part of bindings?
> 
> I meant that driver patch you linked.
> 
> >
> >
> >
> >>
> >>
> >>>
> >>>>
> >>>> Calling it a binding makes it immutable and gives us, DT
> >>>> maintainers, more work, so really no benefits at all.
> >>>
> >>>>
> >>>> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
> >>>
> >>> DT describes hardware. The port names are alpha numeric on hardware manual.
> >>
> >> We talk about binding, not DT.
> >
> > Bu the definitions are part of bindings just like Commit "997daa8de64ccbb".
> 
> You made them part of bindings, but this is invalid as argument. How is this anyhow related? How is
> "DT describes hardware" part of binding?
> 
> You said "DT describes hardware", but we do not talk here about DT, do we? We talk about binding.

OK.

> I am not going to keep reading all the external references you keep bringing or discussing why someone
> else did something. This patch must be logical and correct on its own, not because someone else made
> something somewhere.

OK. According to me this patch is correct. It is for DT user and it described clearly in commit message

"RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
ports in DT using RZV2H_* macros."

Geert,

Please suggest should we merge this patch with the dts patch to avoid confusion??

Cheers,
Biju

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Krzysztof Kozlowski]

On 17/12/2024 10:19, Biju Das wrote:
>>>>>> Calling it a binding makes it immutable and gives us, DT
>>>>>> maintainers, more work, so really no benefits at all.
>>>>>
>>>>>>
>>>>>> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
>>>>>
>>>>> DT describes hardware. The port names are alpha numeric on hardware manual.
>>>>
>>>> We talk about binding, not DT.
>>>
>>> Bu the definitions are part of bindings just like Commit "997daa8de64ccbb".
>>
>> You made them part of bindings, but this is invalid as argument. How is this anyhow related? How is
>> "DT describes hardware" part of binding?
>>
>> You said "DT describes hardware", but we do not talk here about DT, do we? We talk about binding.
> 
> OK.
> 
>> I am not going to keep reading all the external references you keep bringing or discussing why someone
>> else did something. This patch must be logical and correct on its own, not because someone else made
>> something somewhere.
> 
> OK. According to me this patch is correct. It is for DT user and it described clearly in commit message

So you repeat first point which I objected in the first place. If this
is for DT, then this is not a binding and does not deserve header.

> 
> "RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
> ports in DT using RZV2H_* macros."

I read it, I objected to it.

Best regards,
Krzysztof

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 17 December 2024 09:45
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> On 17/12/2024 10:19, Biju Das wrote:
> >>>>>> Calling it a binding makes it immutable and gives us, DT
> >>>>>> maintainers, more work, so really no benefits at all.
> >>>>>
> >>>>>>
> >>>>>> I guess other DT maintainers will ack it, I prefer to reduce number of headers.
> >>>>>
> >>>>> DT describes hardware. The port names are alpha numeric on hardware manual.
> >>>>
> >>>> We talk about binding, not DT.
> >>>
> >>> Bu the definitions are part of bindings just like Commit "997daa8de64ccbb".
> >>
> >> You made them part of bindings, but this is invalid as argument. How
> >> is this anyhow related? How is "DT describes hardware" part of binding?
> >>
> >> You said "DT describes hardware", but we do not talk here about DT, do we? We talk about binding.
> >
> > OK.
> >
> >> I am not going to keep reading all the external references you keep
> >> bringing or discussing why someone else did something. This patch
> >> must be logical and correct on its own, not because someone else made something somewhere.
> >
> > OK. According to me this patch is correct. It is for DT user and it
> > described clearly in commit message
> 
> So you repeat first point which I objected in the first place. If this is for DT, then this is not a
> binding and does not deserve header.

Binding refers macros and macros defined in the header. Did I miss anything here?
Or

Do you want me to update bindings with RZV2H_GPIO* and RZG3E_GPIO* macros??

Cheers,
Biju

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Rob Herring]

On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
> ports in DT using RZV2H_* macros.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Added new header file with separate RZV2H_P* definitions.
> v3:
>  * New patch.
> ---
>  .../pinctrl/renesas,r9a09g057-pinctrl.h       | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> 
> diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> new file mode 100644
> index 000000000000..9008a7e71609
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H
> +#define __DT_BINDINGS_RZV2H_PINCTRL_H
> +
> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> +
> +/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
> +#define RZV2H_P0	0
> +#define RZV2H_P1	1
> +#define RZV2H_P2	2
> +#define RZV2H_P3	3
> +#define RZV2H_P4	4
> +#define RZV2H_P5	5
> +#define RZV2H_P6	6
> +#define RZV2H_P7	7
> +#define RZV2H_P8	8
> +#define RZV2H_P9	9
> +#define RZV2H_PA	10
> +#define RZV2H_PB	11

I'm not a fan of defines which are just 'FOO_n n'. And these are if you 
speak hex.

> +
> +#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
> +#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)

So the user does RZV2H_GPIO(A, 123) instead of RZV2H_GPIO(0xA, 123)? Not 
sure the bounds checking the port is worth it. pin or function can still 
be crap.

Rob

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Rob,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 17 December 2024 11:58
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> > RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> > alpha-numerical ports in DT using RZV2H_* macros.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Added new header file with separate RZV2H_P* definitions.
> > v3:
> >  * New patch.
> > ---
> >  .../pinctrl/renesas,r9a09g057-pinctrl.h       | 31 +++++++++++++++++++
> >  1 file changed, 31 insertions(+)
> >  create mode 100644
> > include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> >
> > diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > new file mode 100644
> > index 000000000000..9008a7e71609
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > @@ -0,0 +1,31 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H #define
> > +__DT_BINDINGS_RZV2H_PINCTRL_H
> > +
> > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > +
> > +/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
> > +#define RZV2H_P0	0
> > +#define RZV2H_P1	1
> > +#define RZV2H_P2	2
> > +#define RZV2H_P3	3
> > +#define RZV2H_P4	4
> > +#define RZV2H_P5	5
> > +#define RZV2H_P6	6
> > +#define RZV2H_P7	7
> > +#define RZV2H_P8	8
> > +#define RZV2H_P9	9
> > +#define RZV2H_PA	10
> > +#define RZV2H_PB	11
> 
> I'm not a fan of defines which are just 'FOO_n n'. And these are if you speak hex.

For RZ/V2H, ports are P{0..9} and P{A..B}, the port name are with in hexa decimal range

whereas for RZ/G3E SoC,

Ports are P{0..8},P{A..H},P{J..M},PS

RZ/V2H and RZ/G3E are similar SoCs.

> 
> > +
> > +#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
> > +#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)
> 
> So the user does RZV2H_GPIO(A, 123) instead of RZV2H_GPIO(0xA, 123)? Not sure the bounds checking the
> port is worth it. pin or function can still be crap.

Previously we were using plain number in DT for RZ/V2H, RZG2L_GPIO(10, pin) = RZG2L_GPIO(0xA, pin)
The port names for RZ/G2L are plane number, whereas for RZ/G3E and RZ/V2H it's alpha numeric.

Since RZ/V2H ports are within the hexadecimal range, maybe this header file can be dropped
at least for RZ/V2H??

Any way we are doing bounds check in driver.

Cheers,
Biju

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Rob Herring]

On Tue, Dec 17, 2024 at 12:33:45PM +0000, Biju Das wrote:
> Hi Rob,
> 
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: 17 December 2024 11:58
> > Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> > 
> > On Mon, Dec 16, 2024 at 07:53:11PM +0000, Biju Das wrote:
> > > RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> > > alpha-numerical ports in DT using RZV2H_* macros.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v3->v4:
> > >  * Added new header file with separate RZV2H_P* definitions.
> > > v3:
> > >  * New patch.
> > > ---
> > >  .../pinctrl/renesas,r9a09g057-pinctrl.h       | 31 +++++++++++++++++++
> > >  1 file changed, 31 insertions(+)
> > >  create mode 100644
> > > include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > >
> > > diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > > b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > > new file mode 100644
> > > index 000000000000..9008a7e71609
> > > --- /dev/null
> > > +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > > @@ -0,0 +1,31 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > > +/*
> > > + * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
> > > + *
> > > + * Copyright (C) 2024 Renesas Electronics Corp.
> > > + *
> > > + */
> > > +
> > > +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H #define
> > > +__DT_BINDINGS_RZV2H_PINCTRL_H
> > > +
> > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > > +
> > > +/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
> > > +#define RZV2H_P0	0
> > > +#define RZV2H_P1	1
> > > +#define RZV2H_P2	2
> > > +#define RZV2H_P3	3
> > > +#define RZV2H_P4	4
> > > +#define RZV2H_P5	5
> > > +#define RZV2H_P6	6
> > > +#define RZV2H_P7	7
> > > +#define RZV2H_P8	8
> > > +#define RZV2H_P9	9
> > > +#define RZV2H_PA	10
> > > +#define RZV2H_PB	11
> > 
> > I'm not a fan of defines which are just 'FOO_n n'. And these are if you speak hex.
> 
> For RZ/V2H, ports are P{0..9} and P{A..B}, the port name are with in hexa decimal range
> 
> whereas for RZ/G3E SoC,
> 
> Ports are P{0..8},P{A..H},P{J..M},PS
> 
> RZ/V2H and RZ/G3E are similar SoCs.
> 
> > 
> > > +
> > > +#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
> > > +#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)
> > 
> > So the user does RZV2H_GPIO(A, 123) instead of RZV2H_GPIO(0xA, 123)? Not sure the bounds checking the
> > port is worth it. pin or function can still be crap.
> 
> Previously we were using plain number in DT for RZ/V2H, RZG2L_GPIO(10, pin) = RZG2L_GPIO(0xA, pin)
> The port names for RZ/G2L are plane number, whereas for RZ/G3E and RZ/V2H it's alpha numeric.
> 
> Since RZ/V2H ports are within the hexadecimal range, maybe this header file can be dropped
> at least for RZ/V2H??
> 
> Any way we are doing bounds check in driver.

If you are doing it elsewhere, then I guess it is fine for some 
consistency.

Rob

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Rob Herring (Arm)]

On Mon, 16 Dec 2024 19:53:11 +0000, Biju Das wrote:
> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
> ports in DT using RZV2H_* macros.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Added new header file with separate RZV2H_P* definitions.
> v3:
>  * New patch.
> ---
>  .../pinctrl/renesas,r9a09g057-pinctrl.h       | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Geert Uytterhoeven]

Hi Biju,

On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical
> ports in DT using RZV2H_* macros.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Added new header file with separate RZV2H_P* definitions.

Thanks for the update!

> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H
> +#define __DT_BINDINGS_RZV2H_PINCTRL_H

> +#endif /* __DT_BINDINGS_RZV2H_PINCTRL_H */

__DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__

Will fix that while applying, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.14.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 03 January 2025 18:43
> Subject: Re: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H
> 
> Hi Biju,
> 
> On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > RZ/V2H has ports P0-P9 and PA-PB. Add support for defining
> > alpha-numerical ports in DT using RZV2H_* macros.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Added new header file with separate RZV2H_P* definitions.
> 
> Thanks for the update!
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
> > @@ -0,0 +1,31 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H #define
> > +__DT_BINDINGS_RZV2H_PINCTRL_H
> 
> > +#endif /* __DT_BINDINGS_RZV2H_PINCTRL_H */
> 
> __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__


> 
> Will fix that while applying, so

Thanks for fixing it.

Cheers,
Biju

[PATCH v4 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC

[Biju Das]

Add documentation for the pin controller found on the Renesas RZ/G3E
(R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more
pins(P00-PS3).

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Dropped ack tag from Conor as there is separate file for RZG3E_P*
   definitions
v2->v3:
 * Updated the macros with hardware indices in the hardware manual.
 * The changes are trivial, so retained ack tag from Conor.
v1->v2:
 * Fixed the warnings reported by bot.
---
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  7 +++-
 .../pinctrl/renesas,r9a09g047-pinctrl.h       | 41 +++++++++++++++++++
 2 files changed, 46 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index a1805b6e3f63..768bb3c2b456 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
               - renesas,r9a08g045-pinctrl # RZ/G3S
+              - renesas,r9a09g047-pinctrl # RZ/G3E
               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 
       - items:
@@ -125,7 +126,7 @@ additionalProperties:
         drive-push-pull: true
         renesas,output-impedance:
           description:
-            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
             property corresponds to register bit values that can be set in the PFC_IOLH_mn
             register, which adjusts the drive strength value and is pin-dependent.
           $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g057-pinctrl
+            enum:
+              - renesas,r9a09g047-pinctrl
+              - renesas,r9a09g057-pinctrl
     then:
       properties:
         resets:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
new file mode 100644
index 000000000000..b2cda1a44b0a
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_RZG3E_PINCTRL_H
+#define __DT_BINDINGS_RZG3E_PINCTRL_H
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3E_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZG3E_P0	0
+#define RZG3E_P1	1
+#define RZG3E_P2	2
+#define RZG3E_P3	3
+#define RZG3E_P4	4
+#define RZG3E_P5	5
+#define RZG3E_P6	6
+#define RZG3E_P7	7
+#define RZG3E_P8	8
+#define RZG3E_PA	10
+#define RZG3E_PB	11
+#define RZG3E_PC	12
+#define RZG3E_PD	13
+#define RZG3E_PE	14
+#define RZG3E_PF	15
+#define RZG3E_PG	16
+#define RZG3E_PH	17
+#define RZG3E_PJ	19
+#define RZG3E_PK	20
+#define RZG3E_PL	21
+#define RZG3E_PM	22
+#define RZG3E_PS	28
+
+#define RZG3E_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
+#define RZG3E_GPIO(port, pin)		RZG2L_GPIO(RZG3E_P##port, pin)
+
+#endif /* __DT_BINDINGS_RZG3E_PINCTRL_H */
-- 
2.43.0

Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC

[Geert Uytterhoeven]

Hi Biju,

Thanks for the update!

On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add documentation for the pin controller found on the Renesas RZ/G3E
> (R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more
> pins(P00-PS3).
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Dropped ack tag from Conor as there is separate file for RZG3E_P*
>    definitions

You forgot to actually drop it?
I guess it doesn't matter much...

> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_RZG3E_PINCTRL_H
> +#define __DT_BINDINGS_RZG3E_PINCTRL_H

> +#endif /* __DT_BINDINGS_RZG3E_PINCTRL_H */

__DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__

Will fix that while applying, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.14.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v4 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 03 January 2025 18:46
> Subject: Re: [PATCH v4 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC
> 
> Hi Biju,
> 
> Thanks for the update!
> 
> On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add documentation for the pin controller found on the Renesas RZ/G3E
> > (R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has
> > more pins(P00-PS3).
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v3->v4:
> >  * Dropped ack tag from Conor as there is separate file for RZG3E_P*
> >    definitions
> 
> You forgot to actually drop it?

Oops. I missed it.

> I guess it doesn't matter much...

OK.

> 
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
> > @@ -0,0 +1,41 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + *
> > + */
> > +
> > +#ifndef __DT_BINDINGS_RZG3E_PINCTRL_H #define
> > +__DT_BINDINGS_RZG3E_PINCTRL_H
> 
> > +#endif /* __DT_BINDINGS_RZG3E_PINCTRL_H */
> 
> __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
> 

Thanks for fixing it.

Cheers,
Biju

[PATCH v4 3/7] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table

[Biju Das]

Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB
as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg
table with alpha-numeric port names to match with the hardware manual.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3->v4:
 * Included header file renesas,r9a09g057-pinctrl.h
 * Updated r9a09g057_variable_pin_cfg table replacing PORT_PB->RZV2H_PB
   macro.
v3:
 * New patch.
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 1a7be7d7b520..b5af69af937a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -26,6 +26,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 
+#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 #include "../core.h"
@@ -382,12 +383,12 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
 }
 
 static const u64 r9a09g057_variable_pin_cfg[] = {
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
-	RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
 };
 
 #ifdef CONFIG_RISCV
-- 
2.43.0

Re: [PATCH v4 3/7] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table

[Geert Uytterhoeven]

On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB
> as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg
> table with alpha-numeric port names to match with the hardware manual.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v3->v4:
>  * Included header file renesas,r9a09g057-pinctrl.h
>  * Updated r9a09g057_variable_pin_cfg table replacing PORT_PB->RZV2H_PB
>    macro.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.14.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v4 4/7] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC

[Biju Das]

Add pinctrl driver support for RZ/G3E SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v4->v4:
 * Included header file renesas,r9a09g047-pinctrl.h
 * Replaced macros PORT_P*->RZG3E_P* 
 * Updated rzg3e_gpio_names table with NULL port names for ports
   corresponding to unsupported hardware indices.
 * Updated r9a09g047_gpio_configs table with NULL value for ports
   corresponding to unsupported hardware indices.
v2->v3:
 * Replaced RZG3E_* macro with generic PORT_* macro.
 * Added ports based on hardware indices.
 * Replaced macros WDTUDF_CA->WDTUDFCA and WDTUDF_CM->WDTUDFCM.
 * Replaced macro QSD0_*->SD0*.
v1->v2:
 * No change.
---
 drivers/pinctrl/renesas/Kconfig         |   1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 173 ++++++++++++++++++++++++
 2 files changed, 174 insertions(+)

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 7f3f41c7fe54..3c18d908b21e 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -41,6 +41,7 @@ config PINCTRL_RENESAS
 	select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0
 	select PINCTRL_RZG2L if ARCH_RZG2L
 	select PINCTRL_RZV2M if ARCH_R9A09G011
+	select PINCTRL_RZG2L if ARCH_R9A09G047
 	select PINCTRL_RZG2L if ARCH_R9A09G057
 	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
 	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b5af69af937a..4fae24453c11 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -26,6 +26,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
@@ -382,6 +383,44 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
 	return 0;
 }
 
+static const u64 r9a09g047_variable_pin_cfg[] = {
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
+	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
+};
+
 static const u64 r9a09g057_variable_pin_cfg[] = {
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
 	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
@@ -1963,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = {
 	RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)),			/* P18 */
 };
 
+static const char * const rzg3e_gpio_names[] = {
+	"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
+	"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
+	"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
+	"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
+	"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
+	"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
+	"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
+	"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
+	"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
+	"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
+	"PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
+	"PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+	"PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
+	"PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
+	"PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
+	"PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
+	"PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
+	"PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
+	"PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"",    "",    "",    "",    "",    "",    "",    "",
+	"PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
+};
+
+static const u64 r9a09g047_gpio_configs[] = {
+	RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS),	/* P0 */
+	RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
+				      PIN_CFG_ELC),		/* P1 */
+	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
+				      PIN_CFG_NOD),		/* P2 */
+	RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS),	/* P3 */
+	RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS),	/* P4 */
+	RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS),	/* P5 */
+	RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS),	/* P6 */
+	RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
+				      PIN_CFG_ELC),		/* P7 */
+	RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS),	/* P8 */
+	0x0,
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a),			/* PA */
+	RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS),	/* PB */
+	RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS),	/* PC */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d),			/* PD */
+	RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS),	/* PE */
+	RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS),	/* PF */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30),			/* PG */
+	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31),			/* PH */
+	0x0,
+	RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33),			/* PJ */
+	RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS),	/* PK */
+	RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS),	/* PL */
+	RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS),	/* PM */
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS),	/* PS */
+};
+
 static const char * const rzv2h_gpio_names[] = {
 	"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
 	"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
@@ -2253,6 +2359,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
 	{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
 };
 
+static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
+	{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
+	{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
+	{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
+	{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
+	{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+	{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+	{ "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+	{ "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+	{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+	{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
+	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
+};
+
 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
 {
 	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2763,6 +2906,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
 	BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
 		     ARRAY_SIZE(rzg2l_gpio_names));
 
+	BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
+		     ARRAY_SIZE(rzg3e_gpio_names));
+
 	BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
 		     ARRAY_SIZE(rzv2h_gpio_names));
 
@@ -3161,6 +3307,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
 	.bias_param_to_hw = &rzg2l_bias_param_to_hw,
 };
 
+static struct rzg2l_pinctrl_data r9a09g047_data = {
+	.port_pins = rzg3e_gpio_names,
+	.port_pin_configs = r9a09g047_gpio_configs,
+	.n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
+	.dedicated_pins = rzg3e_dedicated_pins,
+	.n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
+	.n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
+	.hwcfg = &rzv2h_hwcfg,
+	.variable_pin_cfg = r9a09g047_variable_pin_cfg,
+	.n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
+	.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
+	.custom_params = renesas_rzv2h_custom_bindings,
+#ifdef CONFIG_DEBUG_FS
+	.custom_conf_items = renesas_rzv2h_conf_items,
+#endif
+	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
+	.pmc_writeb = &rzv2h_pmc_writeb,
+	.oen_read = &rzv2h_oen_read,
+	.oen_write = &rzv2h_oen_write,
+	.hw_to_bias_param = &rzv2h_hw_to_bias_param,
+	.bias_param_to_hw = &rzv2h_bias_param_to_hw,
+};
+
 static struct rzg2l_pinctrl_data r9a09g057_data = {
 	.port_pins = rzv2h_gpio_names,
 	.port_pin_configs = r9a09g057_gpio_configs,
@@ -3197,6 +3366,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
 		.compatible = "renesas,r9a08g045-pinctrl",
 		.data = &r9a08g045_data,
 	},
+	{
+		.compatible = "renesas,r9a09g047-pinctrl",
+		.data = &r9a09g047_data,
+	},
 	{
 		.compatible = "renesas,r9a09g057-pinctrl",
 		.data = &r9a09g057_data,
-- 
2.43.0

Re: [PATCH v4 4/7] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC

[Geert Uytterhoeven]

On Mon, Dec 16, 2024 at 8:53 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add pinctrl driver support for RZ/G3E SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v4->v4:
>  * Included header file renesas,r9a09g047-pinctrl.h
>  * Replaced macros PORT_P*->RZG3E_P*
>  * Updated rzg3e_gpio_names table with NULL port names for ports
>    corresponding to unsupported hardware indices.
>  * Updated r9a09g047_gpio_configs table with NULL value for ports
>    corresponding to unsupported hardware indices.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.14.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds