Re: [PATCH v3 2/2] hwmon: (lm75) Fix configuration register writes.

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Applying this fix without correcting the 16-bit sensor masks causes `tmp112` and `as6200` to be severely misconfigured during probe.
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commit 0da1c5266106ec86191304203df47a352a002b92
Author: Markus Stockhausen <markus.stockhausen@gmx.de>

hwmon: (lm75) Fix configuration register writes.

This commit fixes a bug in lm75_write_config() where set mask bits not
defined in the clear mask were being dropped. It ensures both masks are
properly combined for the regmap update.

> diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c
> index 7efcef7768cd..8b74cc314196 100644
> --- a/drivers/hwmon/lm75.c
> +++ b/drivers/hwmon/lm75.c
> @@ -353,7 +353,7 @@ static inline int lm75_write_config(struct lm75_data *data, u16 set_mask,
>  				    u16 clr_mask)
>  {
>  	return regmap_update_bits(data->regmap, LM75_REG_CONF,
> -				  clr_mask | LM75_SHUTDOWN, set_mask);
> +				  clr_mask | set_mask | LM75_SHUTDOWN, set_mask);

Will applying this fix without correcting the 16-bit sensor masks cause
sensors like tmp112 and as6200 to be misconfigured during probe?

I2C temperature sensors transmit and receive the MSB first, but
i2c_smbus_read_word_data() and i2c_smbus_write_word_data() read and write the
LSB first. This causes the driver's memory representation of the configuration
register to be byte-swapped, with the sensor's physical MSB in the lower 8
bits and the physical LSB in the upper 8 bits.

The set_mask for tmp112 (0x60C0) and as6200 (0x10C0) are defined assuming
native byte order. Prior to this patch, the logical bug in
lm75_write_config() silently dropped the set_mask bits because they were not
in clr_mask, leaving the sensors at their power-on defaults.

By fixing the helper, 0x60C0 is actively written to the byte-swapped register
value. Due to the byte-swap, the 0xC0 byte is applied to the lower 8 bits
(sensor MSB) and 0x60 to the upper 8 bits (sensor LSB).

For tmp112, the device receives 0xC0 as its MSB and 0x60 as its LSB. Does
this configure the sensor to 11-bit resolution and 1 Hz sample rate instead
of the intended 12-bit, 8 Hz configuration? 

Could the endianness of the masks for 16-bit devices be fixed simultaneously
to avoid this regression?

>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260502173207.3567876-1-markus.stockhausen@gmx.de?part=2