[PATCH v2 0/3] hwmon: (nct6775) Add support for NCT5525

[PATCH v2 0/3] hwmon: (nct6775) Add support for NCT5525

[Anton Lundin]

This implements support for the NCT5525 super I/O chip.

First two patches are minor fixes in the driver in preparation, and the last
implements the actual support.

These are tested on a ASRock 4X4-V2000 board.
That board has a monitoring of the raw dc comming in to the board, which I
thought I would be able to find as a monitor on this chip, but it's either
a external voltage divider or it's monitored by something else.

Changes in v2:
- Dropped devicetree bindings
- Alphabetic order of chip lists
- Fixed word size access to dual-use registers
- Fan debounce fixed
- Fan support modeled as NCT6116 with fan3 and 4 unpopulated
- Corrected detection of AUXFAN2 rpm and pwm
- Corrected beep functionallity
- Link to v1: https://lore.kernel.org/all/20261103132948.144216-1-glance@ac2.se/

Anton Lundin (3):
  hwmon: (nct6775) Handle dual use registers
  hwmon: (nct6775) Avoid reading nonexistent PWM-mode registers
  hwmon: (nct6775) Add support for NCT5525

 Documentation/hwmon/nct6775.rst  |  10 +-
 drivers/hwmon/nct6775-core.c     | 154 +++++++++++++++++++++++++++++--
 drivers/hwmon/nct6775-platform.c |  17 ++++
 drivers/hwmon/nct6775.h          |   5 +-
 4 files changed, 174 insertions(+), 12 deletions(-)

-- 
2.47.3

[PATCH v2 1/3] hwmon: (nct6775) Handle dual use registers

[Anton Lundin]

The REG_TARGET register has different meaning, depending on if pwm is in
thermal_cruise or speed_cruise.

This means we can't assume it's always word sized, so we need to handle
it differently depending on which mode we're in.

The code already does this, but the register was configured as word
sized for the speed_cruise mode, which would do the wrong thing in
thermal_cruise mode.

Signed-off-by: Anton Lundin <glance@ac2.se>
---
 drivers/hwmon/nct6775-core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/hwmon/nct6775-core.c b/drivers/hwmon/nct6775-core.c
index 6e97e4f08b90..3515a962adac 100644
--- a/drivers/hwmon/nct6775-core.c
+++ b/drivers/hwmon/nct6775-core.c
@@ -1188,15 +1188,13 @@ bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg)
 	case nct6106:
 		return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
 		  (reg >= 0x59 && reg < 0x69 && (reg & 1)) ||
-		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
-		  reg == 0x111 || reg == 0x121 || reg == 0x131;
+		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4;
 	case nct6116:
 	case nct6126:
 		return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
 		  reg == 0x26 || reg == 0x28 || reg == 0x59 || reg == 0x5b ||
 		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4 || reg == 0xe6 ||
-		  reg == 0xe8 || reg == 0x111 || reg == 0x121 || reg == 0x131 ||
-		  reg == 0x191 || reg == 0x1a1;
+		  reg == 0xe8;
 	case nct6775:
 		return (((reg & 0xff00) == 0x100 ||
 		    (reg & 0xff00) == 0x200) &&
-- 
2.47.3

[PATCH v2 2/3] hwmon: (nct6775) Avoid reading nonexistent PWM-mode registers

[Anton Lundin]

A register value of 0 is used to say that this pwm doesn't have modes.

There were already a guard for this in store_pwm_mode() but
nct6775_update_pwm() didn't have one, and read register 0 and then
didn't use the value.

This introduces a guard so we won't read a configuration register we're
not interested in.

Signed-off-by: Anton Lundin <glance@ac2.se>
---
 drivers/hwmon/nct6775-core.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/hwmon/nct6775-core.c b/drivers/hwmon/nct6775-core.c
index 3515a962adac..09dc9cecb278 100644
--- a/drivers/hwmon/nct6775-core.c
+++ b/drivers/hwmon/nct6775-core.c
@@ -1432,11 +1432,15 @@ static int nct6775_update_pwm(struct device *dev)
 		if (!(data->has_pwm & BIT(i)))
 			continue;
 
-		err = nct6775_read_value(data, data->REG_PWM_MODE[i], &reg);
-		if (err)
-			return err;
-		duty_is_dc = data->REG_PWM_MODE[i] && (reg & data->PWM_MODE_MASK[i]);
-		data->pwm_mode[i] = !duty_is_dc;
+		if (data->REG_PWM_MODE[i] == 0) {
+			data->pwm_mode[i] = 1;
+		} else {
+			err = nct6775_read_value(data, data->REG_PWM_MODE[i], &reg);
+			if (err)
+				return err;
+			duty_is_dc = data->REG_PWM_MODE[i] && (reg & data->PWM_MODE_MASK[i]);
+			data->pwm_mode[i] = !duty_is_dc;
+		}
 
 		err = nct6775_read_value(data, data->REG_FAN_MODE[i], &fanmodecfg);
 		if (err)
-- 
2.47.3

[PATCH v2 3/3] hwmon: (nct6775) Add support for NCT5525

[Anton Lundin]

Extend nct6775 driver to support NCT5525.

Signed-off-by: Anton Lundin <glance@ac2.se>
---
 Documentation/hwmon/nct6775.rst  |  10 ++-
 drivers/hwmon/nct6775-core.c     | 134 +++++++++++++++++++++++++++++++
 drivers/hwmon/nct6775-platform.c |  17 ++++
 drivers/hwmon/nct6775.h          |   5 +-
 4 files changed, 163 insertions(+), 3 deletions(-)

diff --git a/Documentation/hwmon/nct6775.rst b/Documentation/hwmon/nct6775.rst
index d2dedade0606..3e2992a1e24f 100644
--- a/Documentation/hwmon/nct6775.rst
+++ b/Documentation/hwmon/nct6775.rst
@@ -48,6 +48,14 @@ Supported chips:
 
     Datasheet: Available from the Nuvoton web site
 
+  * Nuvoton NCT5525D
+
+    Prefix: 'nct5525'
+
+    Addresses scanned: ISA address retrieved from Super I/O registers
+
+    Datasheet: Available from Nuvoton upon request
+
   * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
 
     Prefix: 'nct6775'
@@ -159,7 +167,7 @@ direct temperature sensor inputs, the others are special sources such as PECI,
 PCH, and SMBUS. Depending on the chip type, 2 to 6 of the temperature sources
 can be monitored and compared against minimum, maximum, and critical
 temperatures. The driver reports up to 10 of the temperatures to the user.
-There are 4 to 5 fan rotation speed sensors, 8 to 15 analog voltage sensors,
+There are 3 to 7 fan rotation speed sensors, 8 to 18 analog voltage sensors,
 one VID, alarms with beep warnings (control unimplemented), and some automatic
 fan regulation strategies (plus manual fan control mode).
 
diff --git a/drivers/hwmon/nct6775-core.c b/drivers/hwmon/nct6775-core.c
index 09dc9cecb278..6f7279fb8814 100644
--- a/drivers/hwmon/nct6775-core.c
+++ b/drivers/hwmon/nct6775-core.c
@@ -19,6 +19,7 @@
  * Supports the following chips:
  *
  * Chip        #vin    #fan    #pwm    #temp  chip IDs       man ID
+ * nct5525d     8      3       3       3+3    0xd2b3 0xc1    0x5ca3
  * nct6106d     9      3       3       6+3    0xc450 0xc1    0x5ca3
  * nct6116d     9      5       5       3+3    0xd280 0xc1    0x5ca3
  * nct6126d    10      5       5       3+3    0xd283 0xc1    0x5ca3
@@ -66,6 +67,7 @@
 
 /* used to set data->name = nct6775_device_names[data->sio_kind] */
 static const char * const nct6775_device_names[] = {
+	[nct5525] = "nct5525",
 	[nct6106] = "nct6106",
 	[nct6116] = "nct6116",
 	[nct6126] = "nct6126",
@@ -840,6 +842,41 @@ static const u16 NCT6106_REG_TEMP_CRIT[32] = {
 
 static const u16 NCT6106_REG_TSI_TEMP[] = { 0x59, 0x5b, 0x5d, 0x5f, 0x61, 0x63, 0x65, 0x67 };
 
+/* NCT5525D specific data */
+
+static const u16 NCT5525_REG_IN_MAX[] = {
+	0x92, 0x94, 0x96, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2 };
+static const u16 NCT5525_REG_IN_MIN[] = {
+	0x93, 0x95, 0x97, 0x9b, 0x9d, 0x9f, 0xa1, 0xa3 };
+static const u16 NCT5525_REG_IN[] = {
+	0x01, 0x02, 0x03, 0x05, 0x06, 0x07, 0x08, 0x09 };
+
+/* AUXFAN2 is a bit special without a Max Duty Output Register so
+ * use Output Value Select Register instead
+ */
+static const u16 NCT5525_REG_PWM_READ[] = {
+	0x4a, 0x4b, 0, 0, 0x1a9
+};
+
+static const u16 NCT5525_REG_TEMP_SEL[] = { 0x110, 0x120, 0, 0, 0x1a0 };
+static const u16 NCT5525_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0, 0, 0 };
+
+static const s8 NCT5525_ALARM_BITS[NUM_ALARM_BITS] = {
+	 1,  2,  3,  5,  6,  7,  8,  9, -1, -1, -1, -1,	  /* in0-in11     */
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	  /* in12-in23    */
+	32, 33, -1, -1, 36, -1, -1, -1, -1, -1, -1, -1,	  /* fan1-fan12   */
+	16, 17, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1,	  /* temp1-temp12 */
+	-1, -1,						  /* intr0-intr1  */
+};
+
+static const s8 NCT5525_BEEP_BITS[NUM_BEEP_BITS] = {
+	 1,  2,  3,  5,  6,  7,  8,  9, -1, -1, -1, -1,	  /* in0-in11     */
+	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	  /* in12-in23    */
+	24, 25, -1, -1, 28, -1, -1, -1, -1, -1, -1, -1,	  /* fan1-fan12   */
+	16, 17, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1,	  /* temp1-temp12 */
+	-1, -1, 32					  /* intr0-intr1, beep_en */
+};
+
 /* NCT6112D/NCT6114D/NCT6116D specific data */
 
 static const u16 NCT6116_REG_FAN[] = { 0x20, 0x22, 0x24, 0x26, 0x28 };
@@ -1034,6 +1071,14 @@ static const u16 scale_in_6126[10] = {
 	800, 800, 1600, 1600, 800, 800, 1600, 1600, 1600, 800
 };
 
+/*
+ * NCT5525 scaling:
+ * VIN0, AVSB, 3VCC, VIN2, VHIF, 3VSB, VBAT, VTT
+ */
+static const u16 scale_in_5525[8] = {
+	800, 1600, 1600, 800, 1600, 1600, 1600, 800
+};
+
 static inline long in_from_reg(u8 reg, u8 nr, const u16 *scales)
 {
 	return DIV_ROUND_CLOSEST(reg * scales[nr], 100);
@@ -1185,6 +1230,10 @@ static int nct6775_add_template_attr_group(struct device *dev, struct nct6775_da
 bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg)
 {
 	switch (data->kind) {
+	case nct5525:
+		return reg == 0x20 || reg == 0x22 || reg == 0x28 ||
+		  reg == 0x59 || reg == 0x5b || reg == 0xe0 || reg == 0xe2 ||
+		  reg == 0xe8;
 	case nct6106:
 		return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
 		  (reg >= 0x59 && reg < 0x69 && (reg & 1)) ||
@@ -1574,6 +1623,7 @@ static int nct6775_update_pwm_limits(struct device *dev)
 		case nct6776:
 			data->auto_pwm[i][data->auto_pwm_num] = 0xff;
 			break;
+		case nct5525:
 		case nct6106:
 		case nct6116:
 		case nct6126:
@@ -3240,6 +3290,7 @@ store_auto_pwm(struct device *dev, struct device_attribute *attr,
 			break;
 		case nct6776:
 			break; /* always enabled, nothing to do */
+		case nct5525:
 		case nct6106:
 		case nct6116:
 		case nct6126:
@@ -3566,6 +3617,89 @@ int nct6775_probe(struct device *dev, struct nct6775_data *data,
 	data->scale_in = scale_in;
 
 	switch (data->kind) {
+	case nct5525:
+		data->in_num = 8;
+		data->scale_in = scale_in_5525;
+		/* compatible with NCT6116, with pwm index 3 and 4 not populated. */
+		data->pwm_num = 5;
+		data->auto_pwm_num = 4;
+		data->temp_fixed_num = 3;
+		data->num_temp_alarms = 3;
+		data->num_temp_beeps = 3;
+
+		data->ALARM_BITS = NCT5525_ALARM_BITS;
+		data->BEEP_BITS = NCT5525_BEEP_BITS;
+
+		data->fan_from_reg = fan_from_reg13;
+		data->fan_from_reg_min = fan_from_reg13;
+		data->target_temp_mask = 0xff;
+		data->tolerance_mask = 0x07;
+		data->speed_tolerance_limit = 63;
+
+		data->temp_label = nct6776_temp_label;
+		data->temp_mask = NCT6776_TEMP_MASK;
+		data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
+
+		data->REG_VBAT = NCT6106_REG_VBAT;
+		data->REG_DIODE = NCT6106_REG_DIODE;
+		data->DIODE_MASK = NCT6106_DIODE_MASK;
+		data->REG_VIN = NCT5525_REG_IN;
+		data->REG_IN_MINMAX[0] = NCT5525_REG_IN_MIN;
+		data->REG_IN_MINMAX[1] = NCT5525_REG_IN_MAX;
+		/* compatible with NCT6116, with fans index 3 and 4 not populated. */
+		data->REG_TARGET = NCT6116_REG_TARGET;
+		data->REG_FAN = NCT6116_REG_FAN;
+		data->REG_FAN_MODE = NCT6116_REG_FAN_MODE;
+		data->REG_FAN_MIN = NCT6116_REG_FAN_MIN;
+		data->REG_FAN_PULSES = NCT6116_REG_FAN_PULSES;
+		data->FAN_PULSE_SHIFT = NCT6116_FAN_PULSE_SHIFT;
+		data->REG_FAN_TIME[0] = NCT6116_REG_FAN_STOP_TIME;
+		data->REG_FAN_TIME[1] = NCT6116_REG_FAN_STEP_UP_TIME;
+		data->REG_FAN_TIME[2] = NCT6116_REG_FAN_STEP_DOWN_TIME;
+		data->REG_TOLERANCE_H = NCT6116_REG_TOLERANCE_H;
+		data->REG_PWM[0] = NCT6116_REG_PWM;
+		data->REG_PWM[1] = NCT6116_REG_FAN_START_OUTPUT;
+		data->REG_PWM[2] = NCT6116_REG_FAN_STOP_OUTPUT;
+		data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
+		data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
+		data->REG_PWM_READ = NCT5525_REG_PWM_READ;
+		data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
+		data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
+		data->REG_AUTO_TEMP = NCT6116_REG_AUTO_TEMP;
+		data->REG_AUTO_PWM = NCT6116_REG_AUTO_PWM;
+		data->REG_CRITICAL_TEMP = NCT6116_REG_CRITICAL_TEMP;
+		data->REG_CRITICAL_TEMP_TOLERANCE =
+			NCT6116_REG_CRITICAL_TEMP_TOLERANCE;
+		data->REG_CRITICAL_PWM_ENABLE = NCT6116_REG_CRITICAL_PWM_ENABLE;
+		data->CRITICAL_PWM_ENABLE_MASK =
+			NCT6106_CRITICAL_PWM_ENABLE_MASK;
+		data->REG_CRITICAL_PWM = NCT6116_REG_CRITICAL_PWM;
+		data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
+		data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
+		data->REG_TEMP_SEL = NCT5525_REG_TEMP_SEL;
+		data->REG_WEIGHT_TEMP_SEL = NCT5525_REG_WEIGHT_TEMP_SEL;
+		data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
+		data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
+		data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
+		data->REG_ALARM = NCT6106_REG_ALARM;
+		data->REG_BEEP = NCT6106_REG_BEEP;
+		data->REG_TSI_TEMP = NCT6116_REG_TSI_TEMP;
+
+		reg_temp = NCT6106_REG_TEMP;
+		reg_temp_mon = NCT6106_REG_TEMP_MON;
+		num_reg_temp = 3;
+		num_reg_temp_mon = 2;
+		num_reg_tsi_temp = ARRAY_SIZE(NCT6116_REG_TSI_TEMP);
+		reg_temp_over = NCT6106_REG_TEMP_OVER;
+		reg_temp_hyst = NCT6106_REG_TEMP_HYST;
+		reg_temp_config = NCT6106_REG_TEMP_CONFIG;
+		num_reg_temp_config = 3;
+		reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
+		reg_temp_crit = NCT6106_REG_TEMP_CRIT;
+		reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
+		reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
+
+		break;
 	case nct6106:
 		data->in_num = 9;
 		data->pwm_num = 3;
diff --git a/drivers/hwmon/nct6775-platform.c b/drivers/hwmon/nct6775-platform.c
index 7e09fd387d96..f443ae1dac67 100644
--- a/drivers/hwmon/nct6775-platform.c
+++ b/drivers/hwmon/nct6775-platform.c
@@ -23,6 +23,7 @@
 enum sensor_access { access_direct, access_asuswmi };
 
 static const char * const nct6775_sio_names[] __initconst = {
+	[nct5525] = "NCT5525D",
 	[nct6106] = "NCT6106D",
 	[nct6116] = "NCT6116D",
 	[nct6126] = "NCT6122D/NCT6126D",
@@ -75,6 +76,7 @@ MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
 #define SIO_REG_ENABLE		0x30	/* Logical device enable */
 #define SIO_REG_ADDR		0x60	/* Logical device address (2 bytes) */
 
+#define SIO_NCT5525_ID		0xd2b0
 #define SIO_NCT6106_ID		0xc450
 #define SIO_NCT6116_ID		0xd280
 #define SIO_NCT6122_ID		0xd2a0
@@ -547,6 +549,14 @@ nct6775_check_fan_inputs(struct nct6775_data *data, struct nct6775_sio_data *sio
 
 		fan4min = fan4pin;
 		pwm3pin = fan3pin;
+	} else if (data->kind == nct5525) {
+		/* Pin 48 can be GP64 / SCL / MSCL / AUXFANOUT2 */
+		/* Pin 46 can be GP63 / SDA / MSDA / AUXFANIN2 */
+		int cr1b = sio_data->sio_inb(sio_data, 0x1b);
+		int cr2a = sio_data->sio_inb(sio_data, 0x2a);
+
+		fan5pin = (!(cr1b & 0x03) && (cr2a & 0x01));
+		pwm5pin = fan5pin;
 	} else if (data->kind == nct6106) {
 		int cr24 = sio_data->sio_inb(sio_data, 0x24);
 
@@ -882,6 +892,7 @@ static int nct6775_platform_probe_init(struct nct6775_data *data)
 	case nct6776:
 		data->have_vid = (cr2a & 0x60) == 0x40;
 		break;
+	case nct5525:
 	case nct6106:
 	case nct6116:
 	case nct6126:
@@ -914,6 +925,9 @@ static int nct6775_platform_probe_init(struct nct6775_data *data)
 		tmp = sio_data->sio_inb(sio_data,
 				    NCT6775_REG_CR_FAN_DEBOUNCE);
 		switch (data->kind) {
+		case nct5525:
+			tmp |= 0x68;
+			break;
 		case nct6106:
 		case nct6116:
 		case nct6126:
@@ -1027,6 +1041,9 @@ static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
 		val = force_id;
 
 	switch (val & SIO_ID_MASK) {
+	case SIO_NCT5525_ID:
+		sio_data->kind = nct5525;
+		break;
 	case SIO_NCT6106_ID:
 		sio_data->kind = nct6106;
 		break;
diff --git a/drivers/hwmon/nct6775.h b/drivers/hwmon/nct6775.h
index d18ac91be497..ced4cb9fb1f3 100644
--- a/drivers/hwmon/nct6775.h
+++ b/drivers/hwmon/nct6775.h
@@ -4,8 +4,9 @@
 
 #include <linux/types.h>
 
-enum kinds { nct6106, nct6116, nct6126, nct6775, nct6776, nct6779, nct6791,
-	     nct6792, nct6793, nct6795, nct6796, nct6797, nct6798, nct6799 };
+enum kinds { nct5525, nct6106, nct6116, nct6126, nct6775, nct6776, nct6779,
+	     nct6791, nct6792, nct6793, nct6795, nct6796, nct6797, nct6798,
+	     nct6799 };
 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
 
 #define NUM_TEMP	12	/* Max number of temp attribute sets w/ limits*/
-- 
2.47.3

Re: [PATCH v2 2/3] hwmon: (nct6775) Avoid reading nonexistent PWM-mode registers

[sashiko-bot]

> A register value of 0 is used to say that this pwm doesn't have modes.
> 
> There were already a guard for this in store_pwm_mode() but
> nct6775_update_pwm() didn't have one, and read register 0 and then
> didn't use the value.
> 
> This introduces a guard so we won't read a configuration register we're
> not interested in.
> 
> Signed-off-by: Anton Lundin <glance@ac2.se>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109082511.851377-1-glance@ac2.se?part=2

Re: [PATCH v2 3/3] hwmon: (nct6775) Add support for NCT5525

[sashiko-bot]

> Extend nct6775 driver to support NCT5525.
> 
> Signed-off-by: Anton Lundin <glance@ac2.se>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109082511.851377-1-glance@ac2.se?part=3

Re: [PATCH v2 1/3] hwmon: (nct6775) Handle dual use registers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] hwmon: (nct6775) missing Fixes trailers for REG_TARGET
  word-sized bug
--

commit 07bbb498967ba79c83375f58dde7d2cb44db82b2
Author: Anton Lundin <glance@ac2.se>

> hwmon: (nct6775) Handle dual use registers
>
> The REG_TARGET register has different meaning, depending on if pwm is in
> thermal_cruise or speed_cruise.
>
> This means we can't assume it's always word sized, so we need to handle
> it differently depending on which mode we're in.
>
> The code already does this, but the register was configured as word
> sized for the speed_cruise mode, which would do the wrong thing in
> thermal_cruise mode.
>
> Signed-off-by: Anton Lundin <glance@ac2.se>

[Severity: Low]
Since this fixes how REG_TARGET is accessed in thermal_cruise mode on
NCT6106, NCT6116, and NCT6126, should it include Fixes: tags for the
commits that added those entries to nct6775_reg_is_word_sized()?

  Fixes: 6c009501ff20 ("hwmon: (nct6775) Add support for NCT6102D/6106D")
  Fixes: 29c7cb485b32 ("hwmon: (nct6775) Integrate new model nct6116")
  Fixes: 437b3c2a4bdc ("hwmon: (nct6775) Add support for NCT6126D")

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109082511.851377-1-glance@ac2.se?part=1

Re: [PATCH v2 1/3] hwmon: (nct6775) Handle dual use registers

[Guenter Roeck]

On Mon, Nov 09, 2026 at 09:25:09AM +0100, Anton Lundin wrote:
> The REG_TARGET register has different meaning, depending on if pwm is in
> thermal_cruise or speed_cruise.
> 
> This means we can't assume it's always word sized, so we need to handle
> it differently depending on which mode we're in.
> 
> The code already does this, but the register was configured as word
> sized for the speed_cruise mode, which would do the wrong thing in
> thermal_cruise mode.
> 
> Signed-off-by: Anton Lundin <glance@ac2.se>

Applied, and added the Fixes: tags as suggested by Sashiko.

Thanks,
Guenter

> ---
>  drivers/hwmon/nct6775-core.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/hwmon/nct6775-core.c b/drivers/hwmon/nct6775-core.c
> index 6e97e4f08b90..3515a962adac 100644
> --- a/drivers/hwmon/nct6775-core.c
> +++ b/drivers/hwmon/nct6775-core.c
> @@ -1188,15 +1188,13 @@ bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg)
>  	case nct6106:
>  		return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
>  		  (reg >= 0x59 && reg < 0x69 && (reg & 1)) ||
> -		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
> -		  reg == 0x111 || reg == 0x121 || reg == 0x131;
> +		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4;
>  	case nct6116:
>  	case nct6126:
>  		return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
>  		  reg == 0x26 || reg == 0x28 || reg == 0x59 || reg == 0x5b ||
>  		  reg == 0xe0 || reg == 0xe2 || reg == 0xe4 || reg == 0xe6 ||
> -		  reg == 0xe8 || reg == 0x111 || reg == 0x121 || reg == 0x131 ||
> -		  reg == 0x191 || reg == 0x1a1;
> +		  reg == 0xe8;
>  	case nct6775:
>  		return (((reg & 0xff00) == 0x100 ||
>  		    (reg & 0xff00) == 0x200) &&

Re: [PATCH v2 2/3] hwmon: (nct6775) Avoid reading nonexistent PWM-mode registers

[Guenter Roeck]

On Mon, Nov 09, 2026 at 09:25:10AM +0100, Anton Lundin wrote:
> A register value of 0 is used to say that this pwm doesn't have modes.
> 
> There were already a guard for this in store_pwm_mode() but
> nct6775_update_pwm() didn't have one, and read register 0 and then
> didn't use the value.
> 
> This introduces a guard so we won't read a configuration register we're
> not interested in.
> 
> Signed-off-by: Anton Lundin <glance@ac2.se>

Applied.

Thanks,
Guenter

Re: [PATCH v2 3/3] hwmon: (nct6775) Add support for NCT5525

[Guenter Roeck]

On Mon, Nov 09, 2026 at 09:25:11AM +0100, Anton Lundin wrote:
> Extend nct6775 driver to support NCT5525.
> 
> Signed-off-by: Anton Lundin <glance@ac2.se>

Applied.

Thanks,
Guenter