Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Krishna Kothapalli]

Hi,

I have a couple of devices EEDPROM and Power Sequencer(ADM1066) that need "Sequential Random Read" which has 2 byte address requirements.
Currently Process call is not implemented in code drivers/i2c/busses/i2c-i801.c. 
Appreciate any suggestions for alternative implementations.

Thanks.,

/* I801 command constants */
 #define I801_QUICK              0x00
 #define I801_BYTE               0x04
 #define I801_BYTE_DATA          0x08
 #define I801_WORD_DATA          0x0C
 #define I801_PROC_CALL          0x10    /* unimplemented */<------ 
 #define I801_BLOCK_DATA         0x14
 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 #define I801_BLOCK_LAST         0x34
 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 #define I801_START              0x40
 #define I801_PEC_EN             0x80    /* ICH3 and later */

 		 	   		  
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Re: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Jean Delvare]

Hi Krishna,

On Thu, 8 Oct 2009 19:09:27 -0400, Krishna Kothapalli wrote:
> I have a couple of devices EEDPROM and Power Sequencer(ADM1066) that need "Sequential Random Read" which has 2 byte address requirements.
> Currently Process call is not implemented in code drivers/i2c/busses/i2c-i801.c.

This is correct. Adding process call support to the i2c-i801 driver
would be easy, I even think some developers have done it already but
omitted to send the changes upstream.

However, beware that SMBus process call is _not_ 2-byte addressing. It
is single-byte addressing, followed by two bytes from master to slave,
followed by two bytes from slave to master. Are you certain you need
SMBus process call for the ADM1066? The datasheet doesn't mention it.
All the SMBus transactions mentioned in the ADM1066 datasheet are
already supported by the i2c-i801 driver.

> Appreciate any suggestions for alternative implementations.

Please make sure you know what your needs are, first.

-- 
Jean Delvare
http://khali.linux-fr.org/wishlist.html

RE: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Krishna Kothapalli]

 <20091009083519.2659a79a-ig7AzVSIIG7kN2dkZ6Wm7A@public.gmane.org>
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0


Hi Jean=2C


Thanks much for your response.=20

1) Thanks for correcting: ADM1066 as you mentioned does not require process=
 call.

2) From eeprom AT24C64 sheets: It support  Sequential Random Read. After th=
e micro controller receives a data word=2C it responds with an acknowledge.=
 As long as the EEPROM receives an acknowledge=2C it will continue to incre=
ment the data word address and serially clock out sequential data words... =
The sequential read operation is terminated when the micro controller does =
not respond with a zero but does generate a following stop condition".

The above seems to map to SMBUS Process Call Cycle with I2C_EN=3D1b.

Pls suggest.


Thanks=2C
Krishna



----------------------------------------
> Date: Fri=2C 9 Oct 2009 08:35:19 +0200
> From: khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org
> To: krishna_sunitha-PkbjNfxxIARBDgjK7y7TUQ@public.gmane.org
> CC: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: Looking for ICH SMBUS "Process call" support in i2c-i801 bus=
 driver
>
> Hi Krishna=2C
>
> On Thu=2C 8 Oct 2009 19:09:27 -0400=2C Krishna Kothapalli wrote:
>> I have a couple of devices EEDPROM and Power Sequencer(ADM1066) that nee=
d "Sequential Random Read" which has 2 byte address requirements.
>> Currently Process call is not implemented in code drivers/i2c/busses/i2c=
-i801.c.
>
> This is correct. Adding process call support to the i2c-i801 driver
> would be easy=2C I even think some developers have done it already but
> omitted to send the changes upstream.
>
> However=2C beware that SMBus process call is _not_ 2-byte addressing. It
> is single-byte addressing=2C followed by two bytes from master to slave=
=2C
> followed by two bytes from slave to master. Are you certain you need
> SMBus process call for the ADM1066? The datasheet doesn't mention it.
> All the SMBus transactions mentioned in the ADM1066 datasheet are
> already supported by the i2c-i801 driver.
>
>> Appreciate any suggestions for alternative implementations.
>
> Please make sure you know what your needs are=2C first.
>
> --
> Jean Delvare
> http://khali.linux-fr.org/wishlist.html
 		 	   		  =0A=
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Hotmail: Powerful Free email with security by Microsoft.=0A=
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Re: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Jean Delvare]

Hi Krishna,

On Fri, 9 Oct 2009 19:54:11 -0400, Krishna Kothapalli wrote:
> 
>  <20091009083519.2659a79a-ig7AzVSIIG7kN2dkZ6Wm7A@public.gmane.org>
> Content-Type: text/plain; charset="iso-8859-1"
> Content-Transfer-Encoding: quoted-printable
> MIME-Version: 1.0
> 
> 
> Hi Jean=2C

Your reply is badly formatted. Please check your e-mail client and/or
e-mail server.

> Thanks much for your response.=20
> 
> 1) Thanks for correcting: ADM1066 as you mentioned does not require process=
>  call.
> 
> 2) From eeprom AT24C64 sheets: It support  Sequential Random Read. After th=
> e micro controller receives a data word=2C it responds with an acknowledge.=
>  As long as the EEPROM receives an acknowledge=2C it will continue to incre=
> ment the data word address and serially clock out sequential data words... =
> The sequential read operation is terminated when the micro controller does =
> not respond with a zero but does generate a following stop condition".
> 
> The above seems to map to SMBUS Process Call Cycle with I2C_EN=3D1b.

Not really. What the ICH SMBus can do (using the SMBus process call
with the I2C_EN bit set) is write a two-byte address and read exactly
two bytes back. For the AT24C64, this corresponds to a sequential
random read of size exactly 2 bytes. While I admit it would be possible
to read from the AT24C64 using this transaction, it would perform
rather badly: 6 bytes on the wire for 2 bytes of data read. Given how
large the AT24C64 is, I doubt you will enjoy it, especially with the
poll-based implementation of i2c-i801: you would need over 8 seconds to
read the full EEPROM.

Additionally, implementing it would be technically difficult. What the
ICH implements doesn't match any standard SMBus transaction, and I
don't know of any other SMBus controller implementing this. I don't
think we want to define a new functionality bit and helper function for
a non-standard transaction type only implemented by one controller.
Alternatively, we could let i2c-i801 claim that it supports raw I2C
transactions, and only accept this exact type of transaction. But this
would then require dedicated support in the at24 driver. That's not
particularly appealing either.

As a matter of fact, the at24 driver only accept EEPROM types up to
24C16 on SMBus controllers. For 24C32 and larger, it requires full I2C
support. Connecting an AT24C64 to an Intel ICH SMBus controller is
simply bad engineering. You'd rather use one or more AT24C16 instead,
so you can use standard SMBus transactions and (one address byte) I2C
block reads.

-- 
Jean Delvare
http://khali.linux-fr.org/wishlist.html

RE: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Krishna Kothapalli]

 <20091010090951.1fd0e1a0-ig7AzVSIIG7kN2dkZ6Wm7A@public.gmane.org>
Content-Type: text/plain; charset="Windows-1252"
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Hi Jean:

> For 24C32 and larger=2C it requires full I2C support.

Wondering if USB-I2C module (http://www.robot-electronics.co.uk/htm/usb_i2c=
_tech.htm) is a better compared to ICH9 SMBUS controller from full I2C cycl=
e support and software driver point of view?


Thanks
Krishna


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Re: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Jean Delvare]

Hi Krishna,

On Thu, 15 Oct 2009 16:42:07 -0400, Krishna Kothapalli wrote:
> > For 24C32 and larger=2C it requires full I2C support.
> 
> Wondering if USB-I2C module
> (http://www.robot-electronics.co.uk/htm/usb_i2c_tech.htm) is a better
> compared to ICH9 SMBUS controller from full I2C cycle support and
> software driver point of view?

I have no idea. Never heard of this USB device before. Apparently it
requires two drivers, one for USB to serial emulation and one for the
device itself, none of which is in the upstream kernel tree. The former
is binary-only and is in user-space. This means you will never be able
to use kernel I2C chip drivers on top of it. And anyway I would run
away from binary solutions.

The device in question supports the I2C transactions you need (if I
trust their website) but I wouldn't recommend it for technical
(software) reasons.

-- 
Jean Delvare
http://khali.linux-fr.org/wishlist.html

RE: Looking for ICH SMBUS "Process call" support in i2c-i801 bus driver

[Krishna Kothapalli]

 	<COL117-W4849AF5757A0D75EED6B5E88C50-MsuGFMq8XAE@public.gmane.org>
 

 <20091016090225.53438bdd-ig7AzVSIIG7kN2dkZ6Wm7A@public.gmane.org>
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Hi Jean:

> The device in question supports the I2C transactions you need (if I trust=
 their website) but I wouldn't recommend it for technical (software) reason=
s.

Thanks again. Let me spend more time on what works with ICH9 for 64k size e=
eproms ...

Regards
Krishna
 		 	   		 =20
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