[PATCH 0/3] i3c: mipi-i3c-hci: Add support for AMD_PT and improve IBI/PIO robustness

[PATCH 0/3] i3c: mipi-i3c-hci: Add support for AMD_PT and improve IBI/PIO robustness

[Jian-Ming Liao]

This patch series introduces support for the AMD_PT I3C controller and
includes several improvements to the MIPI I3C HCI driver to enhance
stability and compliance with the latest specifications.

Summary of changes:
- Patch 1: Enables IBI threshold interrupts by default in PIO mode to
  better handle Hot-Join requests and early IBIs.
- Patch 2: Adds explicit PIO queue management (enablement, starting, and
  stop/restart logic) for compliance with HCI v1.2.
- Patch 3: Adds the device ID and platform support for the AMD_PT I3C
  controller.

Testing:
These changes have been validated on the Intel Panther Lake (PTL) and
AMD_PT platforms. No regressions were observed for existing controllers.

Jian-Ming Liao (3):
  i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO
    mode
  i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2
  i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

 drivers/i3c/master/mipi-i3c-hci/core.c        |  4 +
 .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c    |  9 +++
 drivers/i3c/master/mipi-i3c-hci/pio.c         | 81 ++++++++++++++++---
 3 files changed, 82 insertions(+), 12 deletions(-)

-- 
2.43.0


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[PATCH 1/3] i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO mode

[Jian-Ming Liao]

Enable the IBI threshold interrupt (STAT_IBI_STATUS_THLD) by default
during PIO initialization. This ensures that Hot-Join requests and
early IBIs from devices that have not yet formally requested routing
are properly captured, improving system responsiveness and stability.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
 drivers/i3c/master/mipi-i3c-hci/pio.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index ff2657ee220b..7870b2c7888f 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -185,8 +185,13 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
 	pio_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
 
-	/* Always accept error interrupts (will be activated on first xfer) */
-	pio->enabled_irqs = STAT_ALL_ERRORS;
+	/*
+	 * Always accept error interrupts (will be activated on first xfer).
+	 * Also enable IBI threshold interrupt by default to catch Hot-Join
+	 * requests and IBIs from devices that haven't formally requested
+	 * IBI routing yet.
+	 */
+	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
 }
 
 static void hci_pio_suspend(struct i3c_hci *hci)
-- 
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[PATCH 2/3] i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

[Jian-Ming Liao]

- Support explicit enablement and starting of PIO queues as
  required by HCI v1.2.
- Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
- Implement explicit PIO queue stopping/disabling and restart
  logic after errors.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
 drivers/i3c/master/mipi-i3c-hci/core.c |  1 +
 drivers/i3c/master/mipi-i3c-hci/pio.c  | 72 ++++++++++++++++++++++----
 2 files changed, 63 insertions(+), 10 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index e80aa1f5722e..dccc974ef15a 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -1031,6 +1031,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	switch (regval & ~0xf) {
 	case 0x100:	/* version 1.0 */
 	case 0x110:	/* version 1.1 */
+	case 0x120:	/* version 1.2 */
 	case 0x200:	/* version 2.0 */
 		break;
 	default:
diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 7870b2c7888f..c05fb3666378 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -45,6 +45,11 @@
 #define IBI_STATUS_SIZE			GENMASK(15, 8)
 #define CR_QUEUE_SIZE			GENMASK(7, 0)
 
+#define PIO_ALT_QUEUE_SIZE      0x1C
+#define EXT_IBI_QUEUE_EN        BIT(28)
+#define ALT_RESP_QUEUE_EN       BIT(24)
+#define ALT_RESP_QUEUE_SIZE     GENMASK(7, 0)
+
 #define PIO_INTR_STATUS			0x20
 #define PIO_INTR_STATUS_ENABLE		0x24
 #define PIO_INTR_SIGNAL_ENABLE		0x28
@@ -72,6 +77,11 @@
 #define STAT_RX_THLD			BIT(1)
 #define STAT_TX_THLD			BIT(0)
 
+#define PIO_CONTROL			0x30
+#define PIO_CONTROL_ABORT		BIT(2)
+#define PIO_CONTROL_RS			BIT(1)
+#define PIO_CONTROL_ENABLE		BIT(0)
+
 #define PIO_QUEUE_CUR_STATUS		0x38
 #define CUR_IBI_Q_LEVEL			GENMASK(28, 20)
 #define CUR_RESP_Q_LEVEL		GENMASK(18, 10)
@@ -138,11 +148,44 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 {
 	u32 val, size_val, rx_thresh, tx_thresh, ibi_val;
 	struct hci_pio_data *pio = hci->io_data;
+	u32 cmd_sz, resp_sz;
 
 	size_val = pio_reg_read(QUEUE_SIZE);
 	if (size_val_ptr)
 		*size_val_ptr = size_val;
 
+	cmd_sz = FIELD_GET(CR_QUEUE_SIZE, size_val);
+	resp_sz = cmd_sz;
+	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
+
+	/* MIPI I3C HCI v1.2 requires explicitly enabling and starting PIO queues
+	 * and supports alternate queue sizes.
+	 */
+	if (hci->version_major == 1 && hci->version_minor >= 2) {
+		u32 ctl_val = pio_reg_read(CONTROL);
+		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
+
+		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
+			ctl_val |= PIO_CONTROL_ENABLE;
+			pio_reg_write(CONTROL, ctl_val);
+		}
+		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
+
+		/* Adjust actual FIFO sizes based on v1.2 ALT_QUEUE_SIZE */
+		if (alt_val & ALT_RESP_QUEUE_EN)
+			resp_sz = FIELD_GET(ALT_RESP_QUEUE_SIZE, alt_val);
+		if (alt_val & EXT_IBI_QUEUE_EN)
+			ibi_val *= 8;
+	}
+
+	dev_dbg(&hci->master.dev, "CMD FIFO = %u, RESP FIFO = %u entries\n",
+		cmd_sz, resp_sz);
+	dev_dbg(&hci->master.dev, "IBI FIFO = %u bytes\n", 4 * ibi_val);
+	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
+		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
+	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
+		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
+
 	/*
 	 * Let's initialize data thresholds to half of the actual FIFO size.
 	 * The start thresholds aren't used (set to 0) as the FIFO is always
@@ -172,7 +215,7 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	 * or one available response or IBI. For IBI data let's use half the
 	 * IBI queue size within allowed bounds.
 	 */
-	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
+
 	pio->max_ibi_thresh = clamp_val(ibi_val/2, 1, 63);
 	val = FIELD_PREP(QUEUE_IBI_STATUS_THLD, 1) |
 	      FIELD_PREP(QUEUE_IBI_DATA_THLD, pio->max_ibi_thresh) |
@@ -219,15 +262,6 @@ static int hci_pio_init(struct i3c_hci *hci)
 
 	__hci_pio_init(hci, &size_val);
 
-	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
-		FIELD_GET(CR_QUEUE_SIZE, size_val));
-	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
-		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
-	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
-		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
-	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
-		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
-
 	return 0;
 }
 
@@ -246,6 +280,12 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
 		BUG_ON(pio->curr_rx);
 		BUG_ON(pio->curr_tx);
 		BUG_ON(pio->curr_resp);
+		/* MIPI I3C HCI v1.2 requires explicitly stopping and disabling PIO queues */
+		if (hci->version_major == 1 && hci->version_minor >= 2)
+			pio_reg_write(CONTROL, 0x0);
+
+		kfree(pio);
+		hci->io_data = NULL;
 	}
 }
 
@@ -766,6 +806,18 @@ static void hci_pio_err(struct i3c_hci *hci, struct hci_pio_data *pio,
 		hci_pio_dequeue_xfer_common(hci, pio, pio->curr_tx, 1);
 	/* then reset the hardware */
 	mipi_i3c_hci_pio_reset(hci);
+
+	/* MIPI I3C HCI v1.2 requires explicitly restarting PIO queues after error/abort */
+	if (hci->version_major == 1 && hci->version_minor >= 2) {
+		u32 ctl_val = pio_reg_read(CONTROL);
+
+		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
+			ctl_val |= PIO_CONTROL_ENABLE;
+			pio_reg_write(CONTROL, ctl_val);
+		}
+		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
+	}
+
 	mipi_i3c_hci_resume(hci);
 
 	dev_dbg(&hci->master.dev, "status=%#x/%#x",
-- 
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[PATCH 3/3] i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

[Jian-Ming Liao]

Add support for the AMD_PT I3C controller by introducing the following
changes:
- Add AMD_PT I3C controller platform device ID in core.c.
- Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
 drivers/i3c/master/mipi-i3c-hci/core.c             | 3 +++
 drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index dccc974ef15a..15f9faed07c8 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -1198,6 +1198,9 @@ static const struct platform_device_id i3c_hci_driver_ids[] = {
 			HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET |
 			HCI_QUIRK_DMA_REQUIRES_HC_ABORT,
 	},
+	{	.name = "amd-pt-i3c-hci",
+		.driver_data = HCI_QUIRK_RPM_ALLOWED,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
index 5a9e2a43eff8..d7549edd5839 100644
--- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
+++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
@@ -193,6 +193,13 @@ static void intel_i3c_exit(struct mipi_i3c_hci_pci *hci)
 	intel_ltr_hide(&hci->pci->dev);
 }
 
+static const struct mipi_i3c_hci_pci_info amd_pt_info = {
+	.name = "amd-pt-i3c-hci",
+	.id = {0},
+	.instance_offset = {0},
+	.instance_count = 1,
+};
+
 static const struct mipi_i3c_hci_pci_info intel_mi_1_info = {
 	.init = intel_i3c_init,
 	.exit = intel_i3c_exit,
@@ -475,6 +482,8 @@ static const struct pci_device_id mipi_i3c_hci_pci_devices[] = {
 	/* Nova Lake-H */
 	{ PCI_VDEVICE(INTEL, 0xd37c), .driver_data = (kernel_ulong_t)&intel_mi_1_info },
 	{ PCI_VDEVICE(INTEL, 0xd36f), .driver_data = (kernel_ulong_t)&intel_mi_2_info },
+	/* AMD_PT */
+	{ PCI_VDEVICE(AMD, 0x444c), .driver_data = (kernel_ulong_t)&amd_pt_info},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices);
-- 
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Re: [PATCH 1/3] i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO mode

[Frank Li]

On Thu, Jul 09, 2026 at 03:17:42PM +0800, Jian-Ming Liao wrote:
> Enable the IBI threshold interrupt (STAT_IBI_STATUS_THLD) by default
> during PIO initialization. This ensures that Hot-Join requests and
> early IBIs from devices that have not yet formally requested routing

Do you means not call i3c_device_request_ibi()?

Frank
> are properly captured, improving system responsiveness and stability.
>
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
> ---
>  drivers/i3c/master/mipi-i3c-hci/pio.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
> index ff2657ee220b..7870b2c7888f 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/pio.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
> @@ -185,8 +185,13 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  	pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
>  	pio_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
>
> -	/* Always accept error interrupts (will be activated on first xfer) */
> -	pio->enabled_irqs = STAT_ALL_ERRORS;
> +	/*
> +	 * Always accept error interrupts (will be activated on first xfer).
> +	 * Also enable IBI threshold interrupt by default to catch Hot-Join
> +	 * requests and IBIs from devices that haven't formally requested
> +	 * IBI routing yet.
> +	 */
> +	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
>  }
>
>  static void hci_pio_suspend(struct i3c_hci *hci)
> --
> 2.43.0
>
>
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Re: [PATCH 2/3] i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

[Frank Li]

On Thu, Jul 09, 2026 at 03:17:43PM +0800, Jian-Ming Liao wrote:
> - Support explicit enablement and starting of PIO queues as
>   required by HCI v1.2.
> - Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
> - Implement explicit PIO queue stopping/disabling and restart
>   logic after errors.

Remove -

Support explicit enablement and starting of PIO queues as required by
HCI v1.2.

Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.

Implement explicit PIO queue stopping/disabling and restart logic after
errors.

if you prefer -, need

Some sentense ...
  - abc...

>
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
> ---
>  drivers/i3c/master/mipi-i3c-hci/core.c |  1 +
>  drivers/i3c/master/mipi-i3c-hci/pio.c  | 72 ++++++++++++++++++++++----
>  2 files changed, 63 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index e80aa1f5722e..dccc974ef15a 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -1031,6 +1031,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	switch (regval & ~0xf) {
>  	case 0x100:	/* version 1.0 */
>  	case 0x110:	/* version 1.1 */
> +	case 0x120:	/* version 1.2 */
>  	case 0x200:	/* version 2.0 */
>  		break;
>  	default:
> diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
> index 7870b2c7888f..c05fb3666378 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/pio.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
> @@ -45,6 +45,11 @@
>  #define IBI_STATUS_SIZE			GENMASK(15, 8)
>  #define CR_QUEUE_SIZE			GENMASK(7, 0)
>
> +#define PIO_ALT_QUEUE_SIZE      0x1C
> +#define EXT_IBI_QUEUE_EN        BIT(28)
> +#define ALT_RESP_QUEUE_EN       BIT(24)
> +#define ALT_RESP_QUEUE_SIZE     GENMASK(7, 0)
> +

Number start pos align to prevous GENMASK(7, 0) of CR_QUEUE_SIZE

>  #define PIO_INTR_STATUS			0x20
>  #define PIO_INTR_STATUS_ENABLE		0x24
>  #define PIO_INTR_SIGNAL_ENABLE		0x28
> @@ -72,6 +77,11 @@
>  #define STAT_RX_THLD			BIT(1)
>  #define STAT_TX_THLD			BIT(0)
>
> +#define PIO_CONTROL			0x30
> +#define PIO_CONTROL_ABORT		BIT(2)
> +#define PIO_CONTROL_RS			BIT(1)
> +#define PIO_CONTROL_ENABLE		BIT(0)
> +
>  #define PIO_QUEUE_CUR_STATUS		0x38
>  #define CUR_IBI_Q_LEVEL			GENMASK(28, 20)
>  #define CUR_RESP_Q_LEVEL		GENMASK(18, 10)
> @@ -138,11 +148,44 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  {
>  	u32 val, size_val, rx_thresh, tx_thresh, ibi_val;
>  	struct hci_pio_data *pio = hci->io_data;
> +	u32 cmd_sz, resp_sz;
>
>  	size_val = pio_reg_read(QUEUE_SIZE);
>  	if (size_val_ptr)
>  		*size_val_ptr = size_val;
>
> +	cmd_sz = FIELD_GET(CR_QUEUE_SIZE, size_val);
> +	resp_sz = cmd_sz;
> +	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
> +
> +	/* MIPI I3C HCI v1.2 requires explicitly enabling and starting PIO queues
> +	 * and supports alternate queue sizes.
> +	 */
> +	if (hci->version_major == 1 && hci->version_minor >= 2) {
> +		u32 ctl_val = pio_reg_read(CONTROL);
> +		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
> +
> +		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
> +			ctl_val |= PIO_CONTROL_ENABLE;
> +			pio_reg_write(CONTROL, ctl_val);
> +		}
> +		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
> +
> +		/* Adjust actual FIFO sizes based on v1.2 ALT_QUEUE_SIZE */
> +		if (alt_val & ALT_RESP_QUEUE_EN)
> +			resp_sz = FIELD_GET(ALT_RESP_QUEUE_SIZE, alt_val);
> +		if (alt_val & EXT_IBI_QUEUE_EN)
> +			ibi_val *= 8;
> +	}
> +
> +	dev_dbg(&hci->master.dev, "CMD FIFO = %u, RESP FIFO = %u entries\n",
> +		cmd_sz, resp_sz);
> +	dev_dbg(&hci->master.dev, "IBI FIFO = %u bytes\n", 4 * ibi_val);
> +	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
> +		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
> +	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
> +		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
> +
>  	/*
>  	 * Let's initialize data thresholds to half of the actual FIFO size.
>  	 * The start thresholds aren't used (set to 0) as the FIFO is always
> @@ -172,7 +215,7 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  	 * or one available response or IBI. For IBI data let's use half the
>  	 * IBI queue size within allowed bounds.
>  	 */
> -	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
> +
>  	pio->max_ibi_thresh = clamp_val(ibi_val/2, 1, 63);
>  	val = FIELD_PREP(QUEUE_IBI_STATUS_THLD, 1) |
>  	      FIELD_PREP(QUEUE_IBI_DATA_THLD, pio->max_ibi_thresh) |
> @@ -219,15 +262,6 @@ static int hci_pio_init(struct i3c_hci *hci)
>
>  	__hci_pio_init(hci, &size_val);
>
> -	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
> -		FIELD_GET(CR_QUEUE_SIZE, size_val));
> -	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
> -		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
> -	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
> -		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
> -	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
> -		4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
> -

why need move this part?

>  	return 0;
>  }
>
> @@ -246,6 +280,12 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
>  		BUG_ON(pio->curr_rx);
>  		BUG_ON(pio->curr_tx);
>  		BUG_ON(pio->curr_resp);
> +		/* MIPI I3C HCI v1.2 requires explicitly stopping and disabling PIO queues */
> +		if (hci->version_major == 1 && hci->version_minor >= 2)
> +			pio_reg_write(CONTROL, 0x0);
> +
> +		kfree(pio);

why need kfree() here? if fix existing problem, use seperate patch.

> +		hci->io_data = NULL;
>  	}
>  }
>
> @@ -766,6 +806,18 @@ static void hci_pio_err(struct i3c_hci *hci, struct hci_pio_data *pio,
>  		hci_pio_dequeue_xfer_common(hci, pio, pio->curr_tx, 1);
>  	/* then reset the hardware */
>  	mipi_i3c_hci_pio_reset(hci);
> +
> +	/* MIPI I3C HCI v1.2 requires explicitly restarting PIO queues after error/abort */
> +	if (hci->version_major == 1 && hci->version_minor >= 2) {

Can you use helper macro this check, many place use similar check

Frank

> +		u32 ctl_val = pio_reg_read(CONTROL);
> +
> +		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
> +			ctl_val |= PIO_CONTROL_ENABLE;
> +			pio_reg_write(CONTROL, ctl_val);
> +		}
> +		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
> +	}
> +
>  	mipi_i3c_hci_resume(hci);
>
>  	dev_dbg(&hci->master.dev, "status=%#x/%#x",
> --
> 2.43.0
>
>
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Re: [PATCH 3/3] i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

[Frank Li]

On Thu, Jul 09, 2026 at 03:17:44PM +0800, Jian-Ming Liao wrote:
> Add support for the AMD_PT I3C controller by introducing the following
> changes:
> - Add AMD_PT I3C controller platform device ID in core.c.
> - Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.
>
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/i3c/master/mipi-i3c-hci/core.c             | 3 +++
>  drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 9 +++++++++
>  2 files changed, 12 insertions(+)
>
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index dccc974ef15a..15f9faed07c8 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -1198,6 +1198,9 @@ static const struct platform_device_id i3c_hci_driver_ids[] = {
>  			HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET |
>  			HCI_QUIRK_DMA_REQUIRES_HC_ABORT,
>  	},
> +	{	.name = "amd-pt-i3c-hci",
> +		.driver_data = HCI_QUIRK_RPM_ALLOWED,
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
> diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> index 5a9e2a43eff8..d7549edd5839 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> @@ -193,6 +193,13 @@ static void intel_i3c_exit(struct mipi_i3c_hci_pci *hci)
>  	intel_ltr_hide(&hci->pci->dev);
>  }
>
> +static const struct mipi_i3c_hci_pci_info amd_pt_info = {
> +	.name = "amd-pt-i3c-hci",
> +	.id = {0},
> +	.instance_offset = {0},
> +	.instance_count = 1,
> +};
> +
>  static const struct mipi_i3c_hci_pci_info intel_mi_1_info = {
>  	.init = intel_i3c_init,
>  	.exit = intel_i3c_exit,
> @@ -475,6 +482,8 @@ static const struct pci_device_id mipi_i3c_hci_pci_devices[] = {
>  	/* Nova Lake-H */
>  	{ PCI_VDEVICE(INTEL, 0xd37c), .driver_data = (kernel_ulong_t)&intel_mi_1_info },
>  	{ PCI_VDEVICE(INTEL, 0xd36f), .driver_data = (kernel_ulong_t)&intel_mi_2_info },
> +	/* AMD_PT */
> +	{ PCI_VDEVICE(AMD, 0x444c), .driver_data = (kernel_ulong_t)&amd_pt_info},
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices);
> --
> 2.43.0
>
>
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Re: [PATCH 1/3] i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO mode

[廖建銘]

On Fri, Jul 10, 2026 at 02:46:00AM +0000, Frank Li wrote:
>
> On Thu, Jul 09, 2026 at 03:17:42PM +0800, Jian-Ming Liao wrote:
> > Enable the IBI threshold interrupt (STAT_IBI_STATUS_THLD) by default
> > during PIO initialization. This ensures that Hot-Join requests and
> > early IBIs from devices that have not yet formally requested routing
>
> Do you means not call i3c_device_request_ibi()?
>
> Frank

Hi Frank,

Thank you for the feedback.

To provide more context, i3c_device_request_ibi() is indeed being called.
However, according to the HCI spec, if the driver needs to receive interrupts
from the IBI, the STAT_IBI_STATUS_THLD bit in PIO_INTR_SIGNAL_ENABLE must be
set. I noticed that the current driver implementation does not handle this
flag, not even in i3c_device_request_ibi().

Would you recommend handling this in hci_pio_request_ibi() to ensure it's
only enabled when requested? Or is there a preferred way in the I3C framework
to implement this kind of configuration?

I would appreciate your guidance on the best approach to handle this
without compromising the common code path.

Best regards,
Jian-Ming Liao

> > are properly captured, improving system responsiveness and stability.

> > -     pio->enabled_irqs = STAT_ALL_ERRORS;
> > +     pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;

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Re: [PATCH 2/3] i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

[廖建銘]

On Fri, Jul 10, 2026 at 02:57:00AM +0000, Frank Li wrote:
>
> On Thu, Jul 09, 2026 at 03:17:43PM +0800, Jian-Ming Liao wrote:
> > - Support explicit enablement and starting of PIO queues as
> >   required by HCI v1.2.
> > - Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
> > - Implement explicit PIO queue stopping/disabling and restart
> >   logic after errors.
>
> Remove -
>
> Support explicit enablement and starting of PIO queues as required by
> HCI v1.2.
>
> Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
>
> Implement explicit PIO queue stopping/disabling and restart logic after
> errors.
>
> if you prefer -, need
>
> Some sentense ...
>   - abc...
>

Hi Frank,

Thank you for the feedback.

I will remove the '-' prefix in the commit message.

> >  #define IBI_STATUS_SIZE                      GENMASK(15, 8)
> >  #define CR_QUEUE_SIZE                        GENMASK(7, 0)
> >
> > +#define PIO_ALT_QUEUE_SIZE      0x1C
> > +#define EXT_IBI_QUEUE_EN        BIT(28)
> > +#define ALT_RESP_QUEUE_EN       BIT(24)
> > +#define ALT_RESP_QUEUE_SIZE     GENMASK(7, 0)
> > +
>
> Number start pos align to prevous GENMASK(7, 0) of CR_QUEUE_SIZE
>

I will fix it.

> >       __hci_pio_init(hci, &size_val);
> >
> > -     dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
> > -             FIELD_GET(CR_QUEUE_SIZE, size_val));
> > -     dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
> > -             4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
> > -     dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
> > -             4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
> > -     dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
> > -             4 * (2 << FIELD_GET(TX_DATA_BUFFER_SIZE, size_val)));
> > -
>
> why need move this part?

I understand that unnecessary code movement makes the diff harder to review.
My intention for moving the dev_dbg lines was to place them after
calculating the adjusted resp_sz and ibi_val(which are dynamic in
v1.2) @ func "__hci_pio_init".
However, I agree with you, so I will revert the movement and calculate
the adjusted sizes(resp_sz, ibi_val) in place to keep the diff clean.


> > @@ -246,6 +280,12 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
> >               BUG_ON(pio->curr_rx);
> >               BUG_ON(pio->curr_tx);
> >               BUG_ON(pio->curr_resp);
> > +             /* MIPI I3C HCI v1.2 requires explicitly stopping and disabling PIO queues */
> > +             if (hci->version_major == 1 && hci->version_minor >= 2)
> > +                     pio_reg_write(CONTROL, 0x0);
> > +
> > +             kfree(pio);
>
> why need kfree() here? if fix existing problem, use seperate patch.
>

I have verified that pio is managed by devm_kzalloc. I will remove the
manual kfree() to prevent potential double-free issues.

> > @@ -766,6 +806,18 @@ static void hci_pio_err(struct i3c_hci *hci, struct hci_pio_data *pio,
> >               hci_pio_dequeue_xfer_common(hci, pio, pio->curr_tx, 1);
> >       /* then reset the hardware */
> >       mipi_i3c_hci_pio_reset(hci);
> > +
> > +     /* MIPI I3C HCI v1.2 requires explicitly restarting PIO queues after error/abort */
> > +     if (hci->version_major == 1 && hci->version_minor >= 2) {
>
> Can you use helper macro this check, many place use similar check
>
> Frank
>

I agree that a helper macro for checking the HCI version is better for
maintainability.
I will define a helper like hci_version_at_least(hci, maj, min) and
use it to replace the hardcoded checks throughout the driver.

Best regards,
Jian-Ming Liao

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[PATCH v2 0/3] i3c: mipi-i3c-hci: Add support for AMD_PT and improve IBI/PIO robustness

[Jian-Ming Liao]

This patch series introduces support for the AMD_PT I3C controller and
includes several improvements to the MIPI I3C HCI driver to enhance
stability and compliance with the latest specifications.

Summary of changes:
- Patch 1: Enables IBI threshold interrupts by default in PIO mode to
  better handle early IBIs.
- Patch 2: Adds explicit PIO queue management (enablement, starting, and
  stop/restart logic) for compliance with HCI v1.2.
- Patch 3: Adds the device ID and platform support for the AMD_PT I3C
  controller.

Changes in v2:
- Patch 1: Removed unverified "Hot-Join" wording from comments and
  commit message.
- Patch 2: Addressed maintainer feedback:
  - Removed '-' prefixes from commit message.
  - Reverted unnecessary debug line movements and cleaned up 
    macro alignments.
  - Removed redundant manual kfree(pio) to prevent double-free issues.
  - Adopted a helper macro for HCI version checks instead of hardcoding.

Testing:
These changes have been validated on the Intel Panther Lake (PTL) and
AMD_PT platforms. No regressions were observed for existing controllers.

Jian-Ming Liao (3):
  i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO
    mode
  i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2
  i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

 drivers/i3c/master/mipi-i3c-hci/core.c        |  4 +
 drivers/i3c/master/mipi-i3c-hci/hci.h         |  5 ++
 .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c    |  9 +++
 drivers/i3c/master/mipi-i3c-hci/pio.c         | 76 +++++++++++++++++--
 4 files changed, 88 insertions(+), 6 deletions(-)

-- 
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[PATCH v2 1/3] i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO mode

[Jian-Ming Liao]

Enable the IBI threshold interrupt (STAT_IBI_STATUS_THLD) by default
during PIO initialization. This ensures that early IBIs from devices
that have not yet formally requested IBI routing are properly captured,
improving system responsiveness and stability.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
v2:
  - Removed "Hot-Join" references from the commit message and comments,
    as the change focuses strictly on enabling STAT_IBI_STATUS_THLD 
    for general IBI reception per HCI spec.

 drivers/i3c/master/mipi-i3c-hci/pio.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index ff2657ee220b..9df114ef0278 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -185,8 +185,13 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
 	pio_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
 
-	/* Always accept error interrupts (will be activated on first xfer) */
-	pio->enabled_irqs = STAT_ALL_ERRORS;
+	/*
+	 * Always accept error interrupts (will be activated on first xfer).
+	 * Also enable IBI threshold interrupt by default to ensure that IBIs
+	 * are captured, even for devices that haven't formally requested
+	 * IBI routing yet.
+	 */
+	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
 }
 
 static void hci_pio_suspend(struct i3c_hci *hci)
-- 
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[PATCH v2 2/3] i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

[Jian-Ming Liao]

Support explicit enablement and starting of PIO queues as required by
HCI v1.2.
Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
Implement explicit PIO queue stopping/disabling and restart logic after
errors.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
v2:
  - Removed '-' prefixes from commit message per maintainer's suggestion.
  - Aligned GENMASK bit definitions with existing macro styles.
  - Reverted unnecessary dev_dbg line movements to keep the diff clean.
  - Removed manual kfree(pio) as pio is managed by devm_kzalloc.
  - Introduced/used helper macro for HCI version checks instead of hardcoding.

 drivers/i3c/master/mipi-i3c-hci/core.c |  1 +
 drivers/i3c/master/mipi-i3c-hci/hci.h  |  5 ++
 drivers/i3c/master/mipi-i3c-hci/pio.c  | 67 ++++++++++++++++++++++++--
 3 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index e80aa1f5722e..dccc974ef15a 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -1031,6 +1031,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
 	switch (regval & ~0xf) {
 	case 0x100:	/* version 1.0 */
 	case 0x110:	/* version 1.1 */
+	case 0x120:	/* version 1.2 */
 	case 0x200:	/* version 2.0 */
 		break;
 	default:
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index b3d9803b1968..becccb1a8cf5 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -30,6 +30,11 @@
 #define reg_set(r, v)		reg_write(r, reg_read(r) | (v))
 #define reg_clear(r, v)		reg_write(r, reg_read(r) & ~(v))
 
+/* helper macro for HCI version check */
+#define hci_version_at_least(hci, maj, min) \
+	((hci)->version_major > (maj) || \
+	((hci)->version_major == (maj) && (hci)->version_minor >= (min)))
+
 struct hci_cmd_ops;
 
 struct dat_words {
diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
index 9df114ef0278..43ef05468cc4 100644
--- a/drivers/i3c/master/mipi-i3c-hci/pio.c
+++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
@@ -45,6 +45,11 @@
 #define IBI_STATUS_SIZE			GENMASK(15, 8)
 #define CR_QUEUE_SIZE			GENMASK(7, 0)
 
+#define PIO_ALT_QUEUE_SIZE		0x1C
+#define EXT_IBI_QUEUE_EN		BIT(28)
+#define ALT_RESP_QUEUE_EN		BIT(24)
+#define ALT_RESP_QUEUE_SIZE		GENMASK(7, 0)
+
 #define PIO_INTR_STATUS			0x20
 #define PIO_INTR_STATUS_ENABLE		0x24
 #define PIO_INTR_SIGNAL_ENABLE		0x28
@@ -72,6 +77,11 @@
 #define STAT_RX_THLD			BIT(1)
 #define STAT_TX_THLD			BIT(0)
 
+#define PIO_CONTROL			0x30
+#define PIO_CONTROL_ABORT		BIT(2)
+#define PIO_CONTROL_RS			BIT(1)
+#define PIO_CONTROL_ENABLE		BIT(0)
+
 #define PIO_QUEUE_CUR_STATUS		0x38
 #define CUR_IBI_Q_LEVEL			GENMASK(28, 20)
 #define CUR_RESP_Q_LEVEL		GENMASK(18, 10)
@@ -173,6 +183,14 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	 * IBI queue size within allowed bounds.
 	 */
 	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
+	/* Adjust actual IBI queue size based on v1.2 ALT_QUEUE_SIZE */
+	if (hci_version_at_least(hci, 1, 2)) {
+		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
+
+		if (alt_val & EXT_IBI_QUEUE_EN)
+			ibi_val *= 8;
+	}
+
 	pio->max_ibi_thresh = clamp_val(ibi_val/2, 1, 63);
 	val = FIELD_PREP(QUEUE_IBI_STATUS_THLD, 1) |
 	      FIELD_PREP(QUEUE_IBI_DATA_THLD, pio->max_ibi_thresh) |
@@ -192,6 +210,17 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
 	 * IBI routing yet.
 	 */
 	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
+
+	/* MIPI I3C HCI v1.2 requires explicitly enabling and starting PIO queues */
+	if (hci_version_at_least(hci, 1, 2)) {
+		u32 ctl_val = pio_reg_read(CONTROL);
+
+		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
+			ctl_val |= PIO_CONTROL_ENABLE;
+			pio_reg_write(CONTROL, ctl_val);
+		}
+		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
+	}
 }
 
 static void hci_pio_suspend(struct i3c_hci *hci)
@@ -210,6 +239,7 @@ static int hci_pio_init(struct i3c_hci *hci)
 {
 	struct hci_pio_data *pio;
 	u32 size_val;
+	u32 cmd_sz, resp_sz, ibi_val;
 
 	pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL);
 	if (!pio)
@@ -219,10 +249,24 @@ static int hci_pio_init(struct i3c_hci *hci)
 
 	__hci_pio_init(hci, &size_val);
 
-	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
-		FIELD_GET(CR_QUEUE_SIZE, size_val));
-	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
-		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
+	cmd_sz = FIELD_GET(CR_QUEUE_SIZE, size_val);
+	resp_sz = cmd_sz;
+	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
+
+	/* MIPI I3C HCI v1.2 supports alternate RESP/IBI queue size */
+	if (hci_version_at_least(hci, 1, 2)) {
+		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
+
+		if (alt_val & ALT_RESP_QUEUE_EN)
+			resp_sz = FIELD_GET(ALT_RESP_QUEUE_SIZE, alt_val);
+		if (alt_val & EXT_IBI_QUEUE_EN)
+			ibi_val *= 8;
+	}
+
+	dev_dbg(&hci->master.dev, "CMD FIFO = %u, RESP FIFO = %u entries\n",
+		cmd_sz, resp_sz);
+	dev_dbg(&hci->master.dev, "IBI FIFO = %u bytes\n",
+		4 * ibi_val);
 	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
 		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
 	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
@@ -246,6 +290,9 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
 		BUG_ON(pio->curr_rx);
 		BUG_ON(pio->curr_tx);
 		BUG_ON(pio->curr_resp);
+		/* MIPI I3C HCI v1.2 requires explicitly stopping and disabling PIO queues */
+		if (hci_version_at_least(hci, 1, 2))
+			pio_reg_write(CONTROL, 0x0);
 	}
 }
 
@@ -766,6 +813,18 @@ static void hci_pio_err(struct i3c_hci *hci, struct hci_pio_data *pio,
 		hci_pio_dequeue_xfer_common(hci, pio, pio->curr_tx, 1);
 	/* then reset the hardware */
 	mipi_i3c_hci_pio_reset(hci);
+
+	/* MIPI I3C HCI v1.2 requires explicitly restarting PIO queues after error/abort */
+	if (hci_version_at_least(hci, 1, 2)) {
+		u32 ctl_val = pio_reg_read(CONTROL);
+
+		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
+			ctl_val |= PIO_CONTROL_ENABLE;
+			pio_reg_write(CONTROL, ctl_val);
+		}
+		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
+	}
+
 	mipi_i3c_hci_resume(hci);
 
 	dev_dbg(&hci->master.dev, "status=%#x/%#x",
-- 
2.43.0


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[PATCH v2 3/3] i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

[Jian-Ming Liao]

Add support for the AMD_PT I3C controller by introducing the following
changes:
- Add AMD_PT I3C controller platform device ID in core.c.
- Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.

Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>
---
v2:
  - No changes (rebased on top of v2 patch series).

 drivers/i3c/master/mipi-i3c-hci/core.c             | 3 +++
 drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index dccc974ef15a..15f9faed07c8 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -1198,6 +1198,9 @@ static const struct platform_device_id i3c_hci_driver_ids[] = {
 			HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET |
 			HCI_QUIRK_DMA_REQUIRES_HC_ABORT,
 	},
+	{	.name = "amd-pt-i3c-hci",
+		.driver_data = HCI_QUIRK_RPM_ALLOWED,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
index 5a9e2a43eff8..d7549edd5839 100644
--- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
+++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
@@ -193,6 +193,13 @@ static void intel_i3c_exit(struct mipi_i3c_hci_pci *hci)
 	intel_ltr_hide(&hci->pci->dev);
 }
 
+static const struct mipi_i3c_hci_pci_info amd_pt_info = {
+	.name = "amd-pt-i3c-hci",
+	.id = {0},
+	.instance_offset = {0},
+	.instance_count = 1,
+};
+
 static const struct mipi_i3c_hci_pci_info intel_mi_1_info = {
 	.init = intel_i3c_init,
 	.exit = intel_i3c_exit,
@@ -475,6 +482,8 @@ static const struct pci_device_id mipi_i3c_hci_pci_devices[] = {
 	/* Nova Lake-H */
 	{ PCI_VDEVICE(INTEL, 0xd37c), .driver_data = (kernel_ulong_t)&intel_mi_1_info },
 	{ PCI_VDEVICE(INTEL, 0xd36f), .driver_data = (kernel_ulong_t)&intel_mi_2_info },
+	/* AMD_PT */
+	{ PCI_VDEVICE(AMD, 0x444c), .driver_data = (kernel_ulong_t)&amd_pt_info},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices);
-- 
2.43.0


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Re: [PATCH v2 1/3] i3c: mipi-i3c-hci: Enable IBI threshold interrupt by default in PIO mode

[Adrian Hunter]

On 28/07/2026 12:32, Jian-Ming Liao wrote:
> Enable the IBI threshold interrupt (STAT_IBI_STATUS_THLD) by default

Seems like it wasn't enabled at all before.  Should this have
a Fixes tag then?

> during PIO initialization. This ensures that early IBIs from devices
> that have not yet formally requested IBI routing are properly captured,

Is that right?  I think DAT has always been initialized with
SIR_REJECT.  Also i3c_hci_addr_to_dev() has recently been
hardened to prevent IBIs when they are not enabled.

> improving system responsiveness and stability.
> 
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>

./scripts/checkpatch.pl warning:

WARNING: From:/Signed-off-by: email address mismatch: 'From: Jian-Ming Liao <tim678910@gmail.com>' != 'Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>

> ---
> v2:
>   - Removed "Hot-Join" references from the commit message and comments,
>     as the change focuses strictly on enabling STAT_IBI_STATUS_THLD 
>     for general IBI reception per HCI spec.
> 
>  drivers/i3c/master/mipi-i3c-hci/pio.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
> index ff2657ee220b..9df114ef0278 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/pio.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
> @@ -185,8 +185,13 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  	pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
>  	pio_reg_write(INTR_STATUS_ENABLE, 0xffffffff);
>  
> -	/* Always accept error interrupts (will be activated on first xfer) */
> -	pio->enabled_irqs = STAT_ALL_ERRORS;
> +	/*
> +	 * Always accept error interrupts (will be activated on first xfer).
> +	 * Also enable IBI threshold interrupt by default to ensure that IBIs

Actually, in the current code, not enabled until the first xfer

> +	 * are captured, even for devices that haven't formally requested
> +	 * IBI routing yet.
> +	 */
> +	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
>  }
>  
>  static void hci_pio_suspend(struct i3c_hci *hci)


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Re: [PATCH v2 2/3] i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

[Adrian Hunter]

On 28/07/2026 12:32, Jian-Ming Liao wrote:
> Support explicit enablement and starting of PIO queues as required by
> HCI v1.2.
> Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
> Implement explicit PIO queue stopping/disabling and restart logic after
> errors.
> 
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>

./scripts/checkpatch.pl warning:

WARNING: From:/Signed-off-by: email address mismatch: 'From: Jian-Ming Liao <tim678910@gmail.com>' != 'Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>

> ---
> v2:
>   - Removed '-' prefixes from commit message per maintainer's suggestion.
>   - Aligned GENMASK bit definitions with existing macro styles.
>   - Reverted unnecessary dev_dbg line movements to keep the diff clean.
>   - Removed manual kfree(pio) as pio is managed by devm_kzalloc.
>   - Introduced/used helper macro for HCI version checks instead of hardcoding.
> 
>  drivers/i3c/master/mipi-i3c-hci/core.c |  1 +
>  drivers/i3c/master/mipi-i3c-hci/hci.h  |  5 ++
>  drivers/i3c/master/mipi-i3c-hci/pio.c  | 67 ++++++++++++++++++++++++--
>  3 files changed, 69 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index e80aa1f5722e..dccc974ef15a 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -1031,6 +1031,7 @@ static int i3c_hci_init(struct i3c_hci *hci)
>  	switch (regval & ~0xf) {
>  	case 0x100:	/* version 1.0 */
>  	case 0x110:	/* version 1.1 */
> +	case 0x120:	/* version 1.2 */
>  	case 0x200:	/* version 2.0 */
>  		break;
>  	default:
> diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
> index b3d9803b1968..becccb1a8cf5 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/hci.h
> +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
> @@ -30,6 +30,11 @@
>  #define reg_set(r, v)		reg_write(r, reg_read(r) | (v))
>  #define reg_clear(r, v)		reg_write(r, reg_read(r) & ~(v))
>  
> +/* helper macro for HCI version check */
> +#define hci_version_at_least(hci, maj, min) \
> +	((hci)->version_major > (maj) || \
> +	((hci)->version_major == (maj) && (hci)->version_minor >= (min)))
> +
>  struct hci_cmd_ops;
>  
>  struct dat_words {
> diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mipi-i3c-hci/pio.c
> index 9df114ef0278..43ef05468cc4 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/pio.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c
> @@ -45,6 +45,11 @@
>  #define IBI_STATUS_SIZE			GENMASK(15, 8)
>  #define CR_QUEUE_SIZE			GENMASK(7, 0)
>  
> +#define PIO_ALT_QUEUE_SIZE		0x1C
> +#define EXT_IBI_QUEUE_EN		BIT(28)
> +#define ALT_RESP_QUEUE_EN		BIT(24)
> +#define ALT_RESP_QUEUE_SIZE		GENMASK(7, 0)
> +
>  #define PIO_INTR_STATUS			0x20
>  #define PIO_INTR_STATUS_ENABLE		0x24
>  #define PIO_INTR_SIGNAL_ENABLE		0x28
> @@ -72,6 +77,11 @@
>  #define STAT_RX_THLD			BIT(1)
>  #define STAT_TX_THLD			BIT(0)
>  
> +#define PIO_CONTROL			0x30
> +#define PIO_CONTROL_ABORT		BIT(2)
> +#define PIO_CONTROL_RS			BIT(1)
> +#define PIO_CONTROL_ENABLE		BIT(0)
> +
>  #define PIO_QUEUE_CUR_STATUS		0x38
>  #define CUR_IBI_Q_LEVEL			GENMASK(28, 20)
>  #define CUR_RESP_Q_LEVEL		GENMASK(18, 10)
> @@ -173,6 +183,14 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  	 * IBI queue size within allowed bounds.
>  	 */
>  	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
> +	/* Adjust actual IBI queue size based on v1.2 ALT_QUEUE_SIZE */
> +	if (hci_version_at_least(hci, 1, 2)) {
> +		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
> +
> +		if (alt_val & EXT_IBI_QUEUE_EN)
> +			ibi_val *= 8;
> +	}
> +
>  	pio->max_ibi_thresh = clamp_val(ibi_val/2, 1, 63);
>  	val = FIELD_PREP(QUEUE_IBI_STATUS_THLD, 1) |
>  	      FIELD_PREP(QUEUE_IBI_DATA_THLD, pio->max_ibi_thresh) |
> @@ -192,6 +210,17 @@ static void __hci_pio_init(struct i3c_hci *hci, u32 *size_val_ptr)
>  	 * IBI routing yet.
>  	 */
>  	pio->enabled_irqs = STAT_ALL_ERRORS | STAT_IBI_STATUS_THLD;
> +
> +	/* MIPI I3C HCI v1.2 requires explicitly enabling and starting PIO queues */
> +	if (hci_version_at_least(hci, 1, 2)) {
> +		u32 ctl_val = pio_reg_read(CONTROL);
> +
> +		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
> +			ctl_val |= PIO_CONTROL_ENABLE;
> +			pio_reg_write(CONTROL, ctl_val);
> +		}
> +		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
> +	}
>  }
>  
>  static void hci_pio_suspend(struct i3c_hci *hci)
> @@ -210,6 +239,7 @@ static int hci_pio_init(struct i3c_hci *hci)
>  {
>  	struct hci_pio_data *pio;
>  	u32 size_val;
> +	u32 cmd_sz, resp_sz, ibi_val;
>  
>  	pio = devm_kzalloc(hci->master.dev.parent, sizeof(*pio), GFP_KERNEL);
>  	if (!pio)
> @@ -219,10 +249,24 @@ static int hci_pio_init(struct i3c_hci *hci)
>  
>  	__hci_pio_init(hci, &size_val);
>  
> -	dev_dbg(&hci->master.dev, "CMD/RESP FIFO = %ld entries\n",
> -		FIELD_GET(CR_QUEUE_SIZE, size_val));
> -	dev_dbg(&hci->master.dev, "IBI FIFO = %ld bytes\n",
> -		4 * FIELD_GET(IBI_STATUS_SIZE, size_val));
> +	cmd_sz = FIELD_GET(CR_QUEUE_SIZE, size_val);
> +	resp_sz = cmd_sz;
> +	ibi_val = FIELD_GET(IBI_STATUS_SIZE, size_val);
> +
> +	/* MIPI I3C HCI v1.2 supports alternate RESP/IBI queue size */
> +	if (hci_version_at_least(hci, 1, 2)) {
> +		u32 alt_val = pio_reg_read(ALT_QUEUE_SIZE);
> +
> +		if (alt_val & ALT_RESP_QUEUE_EN)
> +			resp_sz = FIELD_GET(ALT_RESP_QUEUE_SIZE, alt_val);
> +		if (alt_val & EXT_IBI_QUEUE_EN)
> +			ibi_val *= 8;
> +	}
> +
> +	dev_dbg(&hci->master.dev, "CMD FIFO = %u, RESP FIFO = %u entries\n",
> +		cmd_sz, resp_sz);
> +	dev_dbg(&hci->master.dev, "IBI FIFO = %u bytes\n",
> +		4 * ibi_val);
>  	dev_dbg(&hci->master.dev, "RX data FIFO = %d bytes\n",
>  		4 * (2 << FIELD_GET(RX_DATA_BUFFER_SIZE, size_val)));
>  	dev_dbg(&hci->master.dev, "TX data FIFO = %d bytes\n",
> @@ -246,6 +290,9 @@ static void hci_pio_cleanup(struct i3c_hci *hci)
>  		BUG_ON(pio->curr_rx);
>  		BUG_ON(pio->curr_tx);
>  		BUG_ON(pio->curr_resp);
> +		/* MIPI I3C HCI v1.2 requires explicitly stopping and disabling PIO queues */
> +		if (hci_version_at_least(hci, 1, 2))
> +			pio_reg_write(CONTROL, 0x0);
>  	}
>  }
>  
> @@ -766,6 +813,18 @@ static void hci_pio_err(struct i3c_hci *hci, struct hci_pio_data *pio,
>  		hci_pio_dequeue_xfer_common(hci, pio, pio->curr_tx, 1);
>  	/* then reset the hardware */
>  	mipi_i3c_hci_pio_reset(hci);
> +
> +	/* MIPI I3C HCI v1.2 requires explicitly restarting PIO queues after error/abort */
> +	if (hci_version_at_least(hci, 1, 2)) {
> +		u32 ctl_val = pio_reg_read(CONTROL);
> +
> +		if (!(ctl_val & PIO_CONTROL_ENABLE)) {
> +			ctl_val |= PIO_CONTROL_ENABLE;
> +			pio_reg_write(CONTROL, ctl_val);
> +		}
> +		pio_reg_write(CONTROL, ctl_val | PIO_CONTROL_RS);
> +	}
> +
>  	mipi_i3c_hci_resume(hci);
>  
>  	dev_dbg(&hci->master.dev, "status=%#x/%#x",


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Re: [PATCH v2 3/3] i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

[Adrian Hunter]

On 28/07/2026 12:32, Jian-Ming Liao wrote:
> Add support for the AMD_PT I3C controller by introducing the following
> changes:
> - Add AMD_PT I3C controller platform device ID in core.c.
> - Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.
> 
> Co-developed-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Patrick Yen <Patrick_Yen@asmedia.com.tw>
> Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>

WARNING: From:/Signed-off-by: email address mismatch: 'From: Jian-Ming Liao <tim678910@gmail.com>' != 'Signed-off-by: Jian-Ming Liao <Jm_Liao@asmedia.com.tw>'

Also missing Frank's Rev'd-by from V1

> ---
> v2:
>   - No changes (rebased on top of v2 patch series).
> 
>  drivers/i3c/master/mipi-i3c-hci/core.c             | 3 +++
>  drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 9 +++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
> index dccc974ef15a..15f9faed07c8 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/core.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/core.c
> @@ -1198,6 +1198,9 @@ static const struct platform_device_id i3c_hci_driver_ids[] = {
>  			HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET |
>  			HCI_QUIRK_DMA_REQUIRES_HC_ABORT,
>  	},
> +	{	.name = "amd-pt-i3c-hci",

Perhaps put '{' on a separate line to match the entry above

> +		.driver_data = HCI_QUIRK_RPM_ALLOWED,
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids);
> diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> index 5a9e2a43eff8..d7549edd5839 100644
> --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
> @@ -193,6 +193,13 @@ static void intel_i3c_exit(struct mipi_i3c_hci_pci *hci)
>  	intel_ltr_hide(&hci->pci->dev);
>  }
>  
> +static const struct mipi_i3c_hci_pci_info amd_pt_info = {
> +	.name = "amd-pt-i3c-hci",
> +	.id = {0},
> +	.instance_offset = {0},
> +	.instance_count = 1,
> +};

Perhaps move this after the other struct mipi_i3c_hci_pci_info
i.e. to approx. match the order in mipi_i3c_hci_pci_devices[]

> +
>  static const struct mipi_i3c_hci_pci_info intel_mi_1_info = {
>  	.init = intel_i3c_init,
>  	.exit = intel_i3c_exit,
> @@ -475,6 +482,8 @@ static const struct pci_device_id mipi_i3c_hci_pci_devices[] = {
>  	/* Nova Lake-H */
>  	{ PCI_VDEVICE(INTEL, 0xd37c), .driver_data = (kernel_ulong_t)&intel_mi_1_info },
>  	{ PCI_VDEVICE(INTEL, 0xd36f), .driver_data = (kernel_ulong_t)&intel_mi_2_info },
> +	/* AMD_PT */
> +	{ PCI_VDEVICE(AMD, 0x444c), .driver_data = (kernel_ulong_t)&amd_pt_info},

Perhaps add a space before '}', just to match the ones above

>  	{ }
>  };
>  MODULE_DEVICE_TABLE(pci, mipi_i3c_hci_pci_devices);


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