From: "Santosh Abraham" <santosha@india.hp.com>
To: linux-ia64@vger.kernel.org
Subject: Cache related question
Date: Fri, 30 Apr 2004 11:57:27 +0000 [thread overview]
Message-ID: <005c01c42ea8$a22c9270$e5624c0f@india.hp.com> (raw)
Hi,
I came to know recently that the itanium based processors
do not implement the inclusion principle wrt caches ? Is
this information correct ?
This was a bit surprising, as I had imagined that inclusion
would'nt be maitained perhaps only after a certain L1 cache
size. What are the trade-offs involved ?
Would there be any s/w (kernel) visible effects of not
implementing inclusion ?
thx,
santosh.
reply other threads:[~2004-04-30 11:57 UTC|newest]
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