RE: cacheble to uncachble change

["Jim Hull" <jim.hull@hp.com>]

In addition to what David wrote, which I completely agree with, you also need to
be aware that it is platform dependent whether any particular address range
supports cacheable, uncacheable, or both attributes.  System firmware
communicates to the OS which attributes are allowed for which address ranges.
I'm not familiar with how ia64-linux exposes this info within the kernel (maybe
David could fill you in).

 -- Jim
    HP Itanium Processor Architect

> -----Original Message-----
> From: linux-ia64-owner@vger.kernel.org 
> [mailto:linux-ia64-owner@vger.kernel.org] On Behalf Of David Mosberger
> Sent: Monday, April 26, 2004 12:25 PM
> To: Mario Smarduch
> Cc: IA-64 Mailing List (New)
> Subject: Re: cacheble to uncachble change
> 
> 
> >>>>> On Mon, 26 Apr 2004 14:00:40 -0500, Mario Smarduch 
> <cms063@email.mot.com> said:
> 
>   Mario> Is there support in IA64 kernel to change a memory mapping
>   Mario> from cacheble to uncacheble attribute. By support I mean one
>   Mario> function which can accept an addr start/range, make sure
>   Mario> in-transit cache data/prefetch hits are synced and upon
>   Mario> return gurantee no CPU has any stale data in its caches and
>   Mario> after installing the new attribute memory is guranteed
>   Mario> synchronized. Or is a combonition of functions/macros
>   Mario> required?
> 
> Volume 2 (System Architecture) of the ASDM outlines the steps needed
> to do such a transition.  All the necessary primitives should be there
> in ia64 linux, but there is no single convenient-to-use function to do
> this.
> 
> In any case, just be careful about not introducing memory attribute
> aliases.  You need to be especially careful since the kernel accesses
> memory with granule-sized mappings (normally 64MB page size, but on
> some machines its 16MB).
> 
> 	--david
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