From: David Mosberger <davidm@napali.hpl.hp.com>
To: linux-ia64@vger.kernel.org
Subject: Re: cacheble to uncachble change
Date: Thu, 29 Apr 2004 04:49:46 +0000 [thread overview]
Message-ID: <16528.35178.111833.357038@napali.hpl.hp.com> (raw)
In-Reply-To: <408D5C58.E07A5FBE@email.mot.com>
>>>>> On Wed, 28 Apr 2004 10:52:58 -0500, Mario Smarduch <cms063@email.mot.com> said:
Mario> But now that I look at it, it seems that TRs pin the kernel
Mario> as well with cacheble attribute.
Yes, there are the pinned entries and, additionally, any address
that's accessed via region 7 (address 0xe000...) will get mapped by
the alternate TLB miss-handler with a granule-sized TLB entry. The
size of a granule is given by IA64_GRANULE_SIZE and is normally 64MB
(but may be 16MB for machines that require it).
So if you map _anything_ uncachable, you need to reserve the _entire_
(naturally-aligned) granule (all 64/16MB of it) and then you'll be OK.
--david
next prev parent reply other threads:[~2004-04-29 4:49 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-04-26 18:57 cacheble to uncachble change Mario Smarduch
2004-04-26 19:25 ` David Mosberger
2004-04-26 21:24 ` Jim Hull
2004-04-26 21:35 ` Robin Holt
2004-04-26 21:46 ` David Mosberger
2004-04-27 0:03 ` David Mosberger
2004-04-27 10:52 ` Robin Holt
2004-04-27 14:24 ` Jack Steiner
2004-04-27 19:50 ` David Mosberger
2004-04-27 21:31 ` Jack Steiner
2004-04-27 21:48 ` David Mosberger
2004-04-27 22:35 ` Mario Smarduch
2004-04-27 22:45 ` David Mosberger
2004-04-27 23:53 ` Luck, Tony
2004-04-28 1:43 ` Robin Holt
2004-04-28 15:52 ` Mario Smarduch
2004-04-29 4:49 ` David Mosberger [this message]
2004-04-29 13:39 ` Smarduch Mario-CMS063
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