From: "Chen, Kenneth W" <kenneth.w.chen@intel.com>
To: linux-ia64@vger.kernel.org
Subject: RE: PMU and timer interrupts
Date: Fri, 10 Feb 2006 20:33:20 +0000 [thread overview]
Message-ID: <200602102033.k1AKXKg25864@unix-os.sc.intel.com> (raw)
In-Reply-To: <20060209171648.GA26865@frankl.hpl.hp.com>
Stephane Eranian wrote on Friday, February 10, 2006 5:35 AM
> Suposing I move up the PERFMON_VECTOR to 0xf1, it will be in the
> top priority class (15) with the following vectors:
>
> Today, the PMU interrupt handler runs with interrupts disabled,
> as such the situation would not be different. In fact, we could
> skip masking/unmasking because we would be in the top class +
> TPR masking done by the kernel on interrupt.
>
> Anybody, has a problem with this?
If your goal is to be able to sample timer interrupt with PMU, you
won't get it even after you move PMU vector one class up. Because
just like PMU vector, timer interrupt handler is run with interrupt
off all the through.
- Ken
next prev parent reply other threads:[~2006-02-10 20:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-09 17:16 PMU and timer interrupts Stephane Eranian
2006-02-09 18:16 ` Jack Steiner
2006-02-09 18:20 ` Luck, Tony
2006-02-09 18:39 ` Stephane Eranian
2006-02-09 19:10 ` Jack Steiner
2006-02-09 19:11 ` Stephane Eranian
2006-02-10 13:35 ` Stephane Eranian
2006-02-10 13:54 ` Jes Sorensen
2006-02-10 20:33 ` Chen, Kenneth W [this message]
2006-02-10 21:22 ` Stephane Eranian
2006-02-10 23:04 ` Chen, Kenneth W
2006-02-10 23:21 ` Stephane Eranian
2006-02-10 23:26 ` Jes Sorensen
2006-02-13 10:38 ` Stephane Eranian
2006-02-13 10:53 ` Jes Sorensen
2006-02-13 20:01 ` Stephane Eranian
2006-02-13 20:12 ` Stephane Eranian
2006-02-13 20:13 ` Chen, Kenneth W
2006-02-13 20:32 ` Chen, Kenneth W
2006-02-13 21:26 ` Keith Owens
2006-02-13 22:49 ` Chen, Kenneth W
2006-02-13 23:46 ` Stephane Eranian
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