From: Guy Sauvebois <Guy.Sauvebois@bull.net>
To: linux-ia64@vger.kernel.org
Subject: bus_features in palinfo.c
Date: Mon, 07 Jun 2004 08:23:07 +0000 [thread overview]
Message-ID: <40C425EB.40703@bull.net> (raw)
Hi,
If i read well, bus_features table in palinfo.c decribes
bit 52 as "Enable Cache Line Repl. Exclusive"
bit 53 as "Enable Cache Line Repl. Shared"
and Intel documentation System Architecture vol 2 (table 11-25)
defines bit 52 as "shared" and bit 53 as "exclusive".
what's right ? Intel doc I think
thanks
guy
--
Guy Sauvebois tel:229 7978 ou 04 76 29 70 81
email: Guy.Sauvebois@bull.net
next reply other threads:[~2004-06-07 8:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-06-07 8:23 Guy Sauvebois [this message]
2004-06-15 16:59 ` bus_features in palinfo.c Stephane Eranian
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