* bus_features in palinfo.c
@ 2004-06-07 8:23 Guy Sauvebois
2004-06-15 16:59 ` Stephane Eranian
0 siblings, 1 reply; 2+ messages in thread
From: Guy Sauvebois @ 2004-06-07 8:23 UTC (permalink / raw)
To: linux-ia64
Hi,
If i read well, bus_features table in palinfo.c decribes
bit 52 as "Enable Cache Line Repl. Exclusive"
bit 53 as "Enable Cache Line Repl. Shared"
and Intel documentation System Architecture vol 2 (table 11-25)
defines bit 52 as "shared" and bit 53 as "exclusive".
what's right ? Intel doc I think
thanks
guy
--
Guy Sauvebois tel:229 7978 ou 04 76 29 70 81
email: Guy.Sauvebois@bull.net
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: bus_features in palinfo.c
2004-06-07 8:23 bus_features in palinfo.c Guy Sauvebois
@ 2004-06-15 16:59 ` Stephane Eranian
0 siblings, 0 replies; 2+ messages in thread
From: Stephane Eranian @ 2004-06-15 16:59 UTC (permalink / raw)
To: linux-ia64
Guy,
On Mon, Jun 07, 2004 at 10:23:07AM +0200, Guy Sauvebois wrote:
>
> If i read well, bus_features table in palinfo.c decribes
> bit 52 as "Enable Cache Line Repl. Exclusive"
> bit 53 as "Enable Cache Line Repl. Shared"
> and Intel documentation System Architecture vol 2 (table 11-25)
> defines bit 52 as "shared" and bit 53 as "exclusive".
> what's right ? Intel doc I think
> thanks
Yes, there is a bug in palinfo.c. I submitted a patch to David
for 2.6 and I will submit to Bjorn for 2.4 as well.
Thanks.
--
-Stephane
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