* AHCI performance and IRQ load
@ 2012-11-23 16:02 Joachim Foerster
2012-11-25 7:58 ` Jack Wang
0 siblings, 1 reply; 2+ messages in thread
From: Joachim Foerster @ 2012-11-23 16:02 UTC (permalink / raw)
To: linux-ide; +Cc: Lorenz Kolb
Hi all,
we are currently working on a high performance storage test solution
using SATA/AHCI. Due to having performance issues with small block sizes
(high interrupt load), we did some research and came across a FAST12
paper by Intel: "When Poll is Better than Interrupt".
The authors do suggest a synchronous completion model or even a hybrid
mode with support for async and sync completion - for future SSDs.
Does anybody know, if there already is work going on to incorporate such
functionality into the block layer & backends (meaning, among others:
libata/ahci)?
Another thing, which seemed promising was AHCI's
CommandCompletionCoalescing (CCC) feature. However most AHCI controllers
don't seem to support this feature.
Anybody aware of AHCI controllers having CCC support?
There seemed to be a discussion about CCC support for the ahci driver
some years ago http://www.spinics.net/lists/linux-ide/msg02994.html, but
obviously no code came out of it - or is there a known patchset?
Thanks,
--
Joachim Förster
Direct DE: +49 (731) 141-149-42
Missing Link Electronics
http://www.missinglinkelectronics.com
Office DE: +49 (731) 141-149-0
Office US: +1 (408) 457-0700
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: AHCI performance and IRQ load
2012-11-23 16:02 AHCI performance and IRQ load Joachim Foerster
@ 2012-11-25 7:58 ` Jack Wang
0 siblings, 0 replies; 2+ messages in thread
From: Jack Wang @ 2012-11-25 7:58 UTC (permalink / raw)
To: Joachim Foerster; +Cc: linux-ide, Lorenz Kolb
2012/11/24 Joachim Foerster <joachim.foerster@missinglinkelectronics.com>:
> Hi all,
>
> we are currently working on a high performance storage test solution using
> SATA/AHCI. Due to having performance issues with small block sizes (high
> interrupt load), we did some research and came across a FAST12 paper by
> Intel: "When Poll is Better than Interrupt".
> The authors do suggest a synchronous completion model or even a hybrid mode
> with support for async and sync completion - for future SSDs.
>
> Does anybody know, if there already is work going on to incorporate such
> functionality into the block layer & backends (meaning, among others:
> libata/ahci)?
>
> Another thing, which seemed promising was AHCI's CommandCompletionCoalescing
> (CCC) feature. However most AHCI controllers don't seem to support this
> feature.
> Anybody aware of AHCI controllers having CCC support?
>
> There seemed to be a discussion about CCC support for the ahci driver some
> years ago http://www.spinics.net/lists/linux-ide/msg02994.html, but
> obviously no code came out of it - or is there a known patchset?
>
> Thanks,
> --
Hi,
Maybe patchset ---- x86, MSI, AHCI: Support multiple MSIs should help
in your case.
regards!
Jack
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