Re: [PATCH v3 0/9] iommu/amd: Add Generic IO Page Table Framework Support for v2 Page Table

[Baolu Lu <baolu.lu@linux.intel.com>]

On 2022/9/8 23:23, Robin Murphy wrote:
> 
>> I can't think of a use case for nesting the PASID under the RID, in
>> every scenario this seems to be problematic. Glad to see it is undone
>> with the new HW.
> 
> I assume you mean you can't think of a use-case for having the RID 
> bypass stage 1/guest translation, since "nesting the PASID under the 
> RID" is basically just how PASIDs work. AMD phrases it as "An upstream 
> packet with a valid PASID in the PASID TLP prefix contains a canonical 
> GVA; an upstream packet without a valid PASID in the PASID TLP prefix or 
> with no PASID TLP prefix and an untranslated address contains a GPA". So 
> GVA->GPA is per-PASID, then GPA->PA is for the entire RID, which is 
> exactly how SMMU stage 1/2 work as well. As far as I'm aware that's 
> standard for Intel too, until SIOV where they can carry the PASID 
> through to the second level also.

Yes. That's something called ECS mode in VT-d 2.x spec. Then Scalable
Mode began to appear in 3.x and replaced the previous ECS. Intel has no
real ECS hardware implementation in the shipping products.

Best regards,
baolu