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From: Will Deacon <will@kernel.org>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: iommu@lists.linux-foundation.org, robin.murphy@arm.com,
	sspatil@android.com
Subject: Re: Users of IOMMU_QCOM_SYS_CACHE?
Date: Thu, 24 Oct 2019 12:21:31 +0100	[thread overview]
Message-ID: <20191024112130.GD1242@willie-the-truck> (raw)
In-Reply-To: <d255a4a6835fb982b5852106f970b0e6@codeaurora.org>

On Thu, Oct 24, 2019 at 04:41:04PM +0530, Sai Prakash Ranjan wrote:
> On 2019-10-24 16:21, Will Deacon wrote:
> > In commit 90ec7a76cc4b ("iommu/io-pgtable-arm: Add support to use system
> > cache") we added support for IOMMU_QCOM_SYS_CACHE which was merged into
> > 5.3.
> > This allows non-coherent devices to request an outer cacheable memory
> > type.... except that nobody actually does this in mainline. I remember
> > there
> > being a potential DRM user but I don't know what happened to it.
> > 
> > Given that this isn't actually exposed in the DMA API, I worry that
> > we're
> > just carrying part of an out-of-tree hack here and propose that we drop
> > the flag altogether unless we get an upstream user, preferably by
> > plumbing
> > this into the DMA API via a new attribute.
> > 
> > Thoughts?
> > 
> 
> There is definitely a user of this coming soon atleast for SC7180 SoC once
> we have support for this SoC upstream.

Ok, I'm keen to see how you end up using this. How soon is soon?

Will
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  reply	other threads:[~2019-10-24 11:21 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 10:51 Users of IOMMU_QCOM_SYS_CACHE? Will Deacon
2019-10-24 11:11 ` Sai Prakash Ranjan
2019-10-24 11:21   ` Will Deacon [this message]
2019-10-24 11:31     ` Sai Prakash Ranjan
2019-10-24 15:38 ` Jordan Crouse

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