From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>
Cc: iommu@lists.linux-foundation.org, robin.murphy@arm.com,
sspatil@android.com
Subject: Re: Users of IOMMU_QCOM_SYS_CACHE?
Date: Thu, 24 Oct 2019 16:41:04 +0530 [thread overview]
Message-ID: <d255a4a6835fb982b5852106f970b0e6@codeaurora.org> (raw)
In-Reply-To: <20191024105150.GC1242@willie-the-truck>
Hi Will,
On 2019-10-24 16:21, Will Deacon wrote:
> Hi all,
>
> In commit 90ec7a76cc4b ("iommu/io-pgtable-arm: Add support to use
> system
> cache") we added support for IOMMU_QCOM_SYS_CACHE which was merged into
> 5.3.
> This allows non-coherent devices to request an outer cacheable memory
> type.... except that nobody actually does this in mainline. I remember
> there
> being a potential DRM user but I don't know what happened to it.
>
> Given that this isn't actually exposed in the DMA API, I worry that
> we're
> just carrying part of an out-of-tree hack here and propose that we drop
> the flag altogether unless we get an upstream user, preferably by
> plumbing
> this into the DMA API via a new attribute.
>
> Thoughts?
>
There is definitely a user of this coming soon atleast for SC7180 SoC
once we have support for this SoC upstream.
-Sai
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next prev parent reply other threads:[~2019-10-24 11:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-24 10:51 Users of IOMMU_QCOM_SYS_CACHE? Will Deacon
2019-10-24 11:11 ` Sai Prakash Ranjan [this message]
2019-10-24 11:21 ` Will Deacon
2019-10-24 11:31 ` Sai Prakash Ranjan
2019-10-24 15:38 ` Jordan Crouse
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