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From: Jordan Crouse <jcrouse@codeaurora.org>
To: Will Deacon <will@kernel.org>
Cc: smasetty@codeaurora.org, iommu@lists.linux-foundation.org,
	robin.murphy@arm.com, sspatil@android.com
Subject: Re: Users of IOMMU_QCOM_SYS_CACHE?
Date: Thu, 24 Oct 2019 09:38:33 -0600	[thread overview]
Message-ID: <20191024153832.GA7966@jcrouse1-lnx.qualcomm.com> (raw)
In-Reply-To: <20191024105150.GC1242@willie-the-truck>

On Thu, Oct 24, 2019 at 11:51:51AM +0100, Will Deacon wrote:
> Hi all,
> 
> In commit 90ec7a76cc4b ("iommu/io-pgtable-arm: Add support to use system
> cache") we added support for IOMMU_QCOM_SYS_CACHE which was merged into 5.3.
> This allows non-coherent devices to request an outer cacheable memory
> type.... except that nobody actually does this in mainline. I remember there
> being a potential DRM user but I don't know what happened to it.

You are thinking of:

https://lore.kernel.org/linux-arm-msm/1538744915-25490-8-git-send-email-smasetty@codeaurora.org/

That is still a thing but it never got revisited after 5.3. I believe that
Sharat will have a refresh coming soon.

> Given that this isn't actually exposed in the DMA API, I worry that we're
> just carrying part of an out-of-tree hack here and propose that we drop
> the flag altogether unless we get an upstream user, preferably by plumbing
> this into the DMA API via a new attribute.

I wouldn't mind if you plumbed it into the DMA API as well but I would ask to
keep an alternate path for those of us who make our own way.

Jordan

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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      parent reply	other threads:[~2019-10-24 15:38 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 10:51 Users of IOMMU_QCOM_SYS_CACHE? Will Deacon
2019-10-24 11:11 ` Sai Prakash Ranjan
2019-10-24 11:21   ` Will Deacon
2019-10-24 11:31     ` Sai Prakash Ranjan
2019-10-24 15:38 ` Jordan Crouse [this message]

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