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From: Lu Baolu <baolu.lu@linux.intel.com>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org
Subject: [PATCH 15/19] iommu/vt-d: Enlightened PASID allocation
Date: Sun,  5 Apr 2020 16:30:49 +0800	[thread overview]
Message-ID: <20200405083053.17865-16-baolu.lu@linux.intel.com> (raw)
In-Reply-To: <20200405083053.17865-1-baolu.lu@linux.intel.com>

Enabling IOMMU in a guest requires communication with the host
driver for certain aspects. Use of PASID ID to enable Shared Virtual
Addressing (SVA) requires managing PASID's in the host. VT-d 3.0 spec
provides a Virtual Command Register (VCMD) to facilitate this.
Writes to this register in the guest are trapped by vIOMMU which
proxies the call to the host driver.

This virtual command interface consists of a capability register,
a virtual command register, and a virtual response register. Refer
to section 10.4.42, 10.4.43, 10.4.44 for more information.

This patch adds the enlightened PASID allocation/free interfaces
via the virtual command interface.

Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
---
 drivers/iommu/intel-pasid.c | 57 +++++++++++++++++++++++++++++++++++++
 drivers/iommu/intel-pasid.h | 13 ++++++++-
 include/linux/intel-iommu.h |  1 +
 3 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index d6573a454d20..8da1b4162a82 100644
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -27,6 +27,63 @@
 static DEFINE_SPINLOCK(pasid_lock);
 u32 intel_pasid_max_id = PASID_MAX;
 
+int vcmd_alloc_pasid(struct intel_iommu *iommu, unsigned int *pasid)
+{
+	unsigned long flags;
+	u8 status_code;
+	int ret = 0;
+	u64 res;
+
+	raw_spin_lock_irqsave(&iommu->register_lock, flags);
+	dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC);
+	IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,
+		      !(res & VCMD_VRSP_IP), res);
+	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
+
+	status_code = VCMD_VRSP_SC(res);
+	switch (status_code) {
+	case VCMD_VRSP_SC_SUCCESS:
+		*pasid = VCMD_VRSP_RESULT_PASID(res);
+		break;
+	case VCMD_VRSP_SC_NO_PASID_AVAIL:
+		pr_info("IOMMU: %s: No PASID available\n", iommu->name);
+		ret = -ENOSPC;
+		break;
+	default:
+		ret = -ENODEV;
+		pr_warn("IOMMU: %s: Unexpected error code %d\n",
+			iommu->name, status_code);
+	}
+
+	return ret;
+}
+
+void vcmd_free_pasid(struct intel_iommu *iommu, unsigned int pasid)
+{
+	unsigned long flags;
+	u8 status_code;
+	u64 res;
+
+	raw_spin_lock_irqsave(&iommu->register_lock, flags);
+	dmar_writeq(iommu->reg + DMAR_VCMD_REG,
+		    VCMD_CMD_OPERAND(pasid) | VCMD_CMD_FREE);
+	IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq,
+		      !(res & VCMD_VRSP_IP), res);
+	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
+
+	status_code = VCMD_VRSP_SC(res);
+	switch (status_code) {
+	case VCMD_VRSP_SC_SUCCESS:
+		break;
+	case VCMD_VRSP_SC_INVALID_PASID:
+		pr_info("IOMMU: %s: Invalid PASID\n", iommu->name);
+		break;
+	default:
+		pr_warn("IOMMU: %s: Unexpected error code %d\n",
+			iommu->name, status_code);
+	}
+}
+
 /*
  * Per device pasid table management:
  */
diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
index ccd50c2ae75c..a41b09b3ffde 100644
--- a/drivers/iommu/intel-pasid.h
+++ b/drivers/iommu/intel-pasid.h
@@ -23,6 +23,16 @@
 #define is_pasid_enabled(entry)		(((entry)->lo >> 3) & 0x1)
 #define get_pasid_dir_size(entry)	(1 << ((((entry)->lo >> 9) & 0x7) + 7))
 
+/* Virtual command interface for enlightened pasid management. */
+#define VCMD_CMD_ALLOC			0x1
+#define VCMD_CMD_FREE			0x2
+#define VCMD_VRSP_IP			0x1
+#define VCMD_VRSP_SC(e)			(((e) >> 1) & 0x3)
+#define VCMD_VRSP_SC_SUCCESS		0
+#define VCMD_VRSP_SC_NO_PASID_AVAIL	1
+#define VCMD_VRSP_SC_INVALID_PASID	1
+#define VCMD_VRSP_RESULT_PASID(e)	(((e) >> 8) & 0xfffff)
+#define VCMD_CMD_OPERAND(e)		((e) << 8)
 /*
  * Domain ID reserved for pasid entries programmed for first-level
  * only and pass-through transfer modes.
@@ -111,5 +121,6 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu,
 			     struct dmar_domain *domain, int addr_width);
 void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
 				 struct device *dev, int pasid);
-
+int vcmd_alloc_pasid(struct intel_iommu *iommu, unsigned int *pasid);
+void vcmd_free_pasid(struct intel_iommu *iommu, unsigned int pasid);
 #endif /* __INTEL_PASID_H */
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 0da2f75f2f3d..fcee324173a8 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -169,6 +169,7 @@
 #define ecap_smpwc(e)		(((e) >> 48) & 0x1)
 #define ecap_flts(e)		(((e) >> 47) & 0x1)
 #define ecap_slts(e)		(((e) >> 46) & 0x1)
+#define ecap_vcs(e)		(((e) >> 44) & 0x1)
 #define ecap_smts(e)		(((e) >> 43) & 0x1)
 #define ecap_dit(e)		((e >> 41) & 0x1)
 #define ecap_pasid(e)		((e >> 40) & 0x1)
-- 
2.17.1

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  parent reply	other threads:[~2020-04-05  8:34 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-05  8:30 [PATCH 00/19] [PULL REQUEST] iommu/vt-d: patches for v5.7 Lu Baolu
2020-04-05  8:30 ` [PATCH 01/19] iommu: Add def_domain_type() callback in iommu_ops Lu Baolu
2020-04-05  8:30 ` [PATCH 02/19] iommu: Configure default domain with def_domain_type Lu Baolu
2020-04-05  8:30 ` [PATCH 03/19] iommu/vt-d: Don't force 32bit devices to uses DMA domain Lu Baolu
2020-04-05  8:30 ` [PATCH 04/19] iommu/vt-d: Don't force PCI sub-hierarchy to use " Lu Baolu
2020-04-05  8:30 ` [PATCH 05/19] iommu/vt-d: Add def_domain_type callback Lu Baolu
2020-04-05  8:30 ` [PATCH 06/19] iommu/vt-d: Apply per-device dma_ops Lu Baolu
2020-04-05  8:30 ` [PATCH 07/19] iommu/vt-d: Move domain helper to header Lu Baolu
2020-04-05  8:30 ` [PATCH 08/19] iommu/uapi: Define a mask for bind data Lu Baolu
2020-04-05  8:30 ` [PATCH 09/19] iommu/vt-d: Use a helper function to skip agaw for SL Lu Baolu
2020-04-05  8:30 ` [PATCH 10/19] iommu/vt-d: Add nested translation helper function Lu Baolu
2020-04-05  8:30 ` [PATCH 11/19] iommu/vt-d: Add bind guest PASID support Lu Baolu
2020-04-05  8:30 ` [PATCH 12/19] iommu/vt-d: Support flushing more translation cache types Lu Baolu
2020-04-05  8:30 ` [PATCH 13/19] iommu/vt-d: Add svm/sva invalidate function Lu Baolu
2020-04-05  8:30 ` [PATCH 14/19] iommu/vt-d: Cache virtual command capability register Lu Baolu
2020-04-05  8:30 ` Lu Baolu [this message]
2020-04-05  8:30 ` [PATCH 16/19] iommu/vt-d: Add custom allocator for IOASID Lu Baolu
2020-04-05  8:30 ` [PATCH 17/19] iommu/vt-d: Add get_domain_info() helper Lu Baolu
2020-04-05  8:30 ` [PATCH 18/19] iommu/vt-d: Report SVA feature with generic flag Lu Baolu
2020-04-05  8:30 ` [PATCH 19/19] iommu/vt-d: Replace intel SVM APIs with generic SVA APIs Lu Baolu
2020-04-06 13:36 ` [PATCH 00/19] [PULL REQUEST] iommu/vt-d: patches for v5.7 Christoph Hellwig
2020-04-07  0:09   ` Lu Baolu

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