* [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro
@ 2023-06-09 9:03 Vasant Hegde
2023-06-12 18:24 ` Jerry Snitselaar
2023-06-16 14:31 ` Joerg Roedel
0 siblings, 2 replies; 3+ messages in thread
From: Vasant Hegde @ 2023-06-09 9:03 UTC (permalink / raw)
To: iommu, joro; +Cc: suravee.suthikulpanit, Vasant Hegde
Interrupt Table Root Pointer is 52 bit and table must be aligned to start
on a 128-byte boundary. Hence first 6 bits are ignored.
Current code uses address mask as 45 instead of 46bit. Use GENMASK_ULL
macro instead of manually generating address mask.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/amd_iommu_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 2ddbda3a4374..ae0edeb379d4 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -283,7 +283,7 @@
#define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
/* Bit value definition for dte irq remapping fields*/
-#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
+#define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
#define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
#define DTE_IRQ_REMAP_ENABLE 1ULL
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro
2023-06-09 9:03 [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro Vasant Hegde
@ 2023-06-12 18:24 ` Jerry Snitselaar
2023-06-16 14:31 ` Joerg Roedel
1 sibling, 0 replies; 3+ messages in thread
From: Jerry Snitselaar @ 2023-06-12 18:24 UTC (permalink / raw)
To: Vasant Hegde; +Cc: iommu, joro, suravee.suthikulpanit
On Fri, Jun 09, 2023 at 09:03:27AM +0000, Vasant Hegde wrote:
> Interrupt Table Root Pointer is 52 bit and table must be aligned to start
> on a 128-byte boundary. Hence first 6 bits are ignored.
>
> Current code uses address mask as 45 instead of 46bit. Use GENMASK_ULL
> macro instead of manually generating address mask.
>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
> ---
> drivers/iommu/amd/amd_iommu_types.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 2ddbda3a4374..ae0edeb379d4 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -283,7 +283,7 @@
> #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30))
>
> /* Bit value definition for dte irq remapping fields*/
> -#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
> +#define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6)
> #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
> #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
> #define DTE_IRQ_REMAP_ENABLE 1ULL
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro
2023-06-09 9:03 [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro Vasant Hegde
2023-06-12 18:24 ` Jerry Snitselaar
@ 2023-06-16 14:31 ` Joerg Roedel
1 sibling, 0 replies; 3+ messages in thread
From: Joerg Roedel @ 2023-06-16 14:31 UTC (permalink / raw)
To: Vasant Hegde; +Cc: iommu, suravee.suthikulpanit
On Fri, Jun 09, 2023 at 09:03:27AM +0000, Vasant Hegde wrote:
> Interrupt Table Root Pointer is 52 bit and table must be aligned to start
> on a 128-byte boundary. Hence first 6 bits are ignored.
>
> Current code uses address mask as 45 instead of 46bit. Use GENMASK_ULL
> macro instead of manually generating address mask.
>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
> drivers/iommu/amd/amd_iommu_types.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-06-09 9:03 [PATCH] iommu/amd: Fix DTE_IRQ_PHYS_ADDR_MASK macro Vasant Hegde
2023-06-12 18:24 ` Jerry Snitselaar
2023-06-16 14:31 ` Joerg Roedel
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