From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>,
Jason Gunthorpe <jgg@nvidia.com>
Subject: [PATCH v3 11/16] iommu/amd: Rename ats related variables
Date: Fri, 4 Aug 2023 06:42:11 +0000 [thread overview]
Message-ID: <20230804064216.835544-12-vasant.hegde@amd.com> (raw)
In-Reply-To: <20230804064216.835544-1-vasant.hegde@amd.com>
Remove nested structure and make it as 'ats_{enable/qdep}'.
Also convert 'dev_data.pri_tlp' to bit field.
No functional changes intended.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
---
drivers/iommu/amd/amd_iommu_types.h | 8 +++-----
drivers/iommu/amd/iommu.c | 28 ++++++++++++++--------------
2 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index bbb5ac4f0d39..b79c6e10684d 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -816,11 +816,9 @@ struct iommu_dev_data {
struct device *dev;
u16 devid; /* PCI Device ID */
bool iommu_v2; /* Device can make use of IOMMUv2 */
- struct {
- bool enabled;
- int qdep;
- } ats; /* ATS state */
- bool pri_tlp; /* PASID TLB required for
+ int ats_qdep;
+ u8 ats_enabled :1; /* ATS state */
+ u8 pri_tlp :1; /* PASID TLB required for
PPR completions */
bool use_vapic; /* Enable device to use vapic mode */
bool defer_attach;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index e5b2dbf841c6..5968eb8d265c 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1086,7 +1086,7 @@ static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
}
static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
- int status, int tag, bool gn)
+ int status, int tag, u8 gn)
{
memset(cmd, 0, sizeof(*cmd));
@@ -1309,7 +1309,7 @@ static int device_flush_iotlb(struct iommu_dev_data *dev_data,
struct iommu_cmd cmd;
int qdep;
- qdep = dev_data->ats.qdep;
+ qdep = dev_data->ats_qdep;
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
return -EINVAL;
@@ -1360,7 +1360,7 @@ static int device_flush_dte(struct iommu_dev_data *dev_data)
return ret;
}
- if (dev_data->ats.enabled)
+ if (dev_data->ats_enabled)
ret = device_flush_iotlb(dev_data, 0, ~0UL);
return ret;
@@ -1393,7 +1393,7 @@ static void __domain_flush_pages(struct protection_domain *domain,
list_for_each_entry(dev_data, &domain->dev_list, list) {
- if (!dev_data->ats.enabled)
+ if (!dev_data->ats_enabled)
continue;
ret |= device_flush_iotlb(dev_data, address, size);
@@ -1714,7 +1714,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
return;
- ats = dev_data->ats.enabled;
+ ats = dev_data->ats_enabled;
/* Update data structures */
dev_data->domain = domain;
@@ -1852,14 +1852,14 @@ static int attach_device(struct device *dev,
if (pdev_pri_ats_enable(pdev) != 0)
goto out;
- dev_data->ats.enabled = true;
- dev_data->ats.qdep = pci_ats_queue_depth(pdev);
+ dev_data->ats_enabled = 1;
+ dev_data->ats_qdep = pci_ats_queue_depth(pdev);
dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
}
} else if (amd_iommu_iotlb_sup &&
pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
- dev_data->ats.enabled = true;
- dev_data->ats.qdep = pci_ats_queue_depth(pdev);
+ dev_data->ats_enabled = 1;
+ dev_data->ats_qdep = pci_ats_queue_depth(pdev);
}
skip_ats_check:
@@ -1916,10 +1916,10 @@ static void detach_device(struct device *dev)
if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
pdev_iommuv2_disable(to_pci_dev(dev));
- else if (dev_data->ats.enabled)
+ else if (dev_data->ats_enabled)
pci_disable_ats(to_pci_dev(dev));
- dev_data->ats.enabled = false;
+ dev_data->ats_enabled = 0;
out:
spin_unlock(&dev_data->lock);
@@ -2009,7 +2009,7 @@ static void update_device_table(struct protection_domain *domain)
if (!iommu)
continue;
set_dte_entry(iommu, dev_data->devid, domain,
- dev_data->ats.enabled, dev_data->iommu_v2);
+ dev_data->ats_enabled, dev_data->iommu_v2);
clone_aliases(iommu, dev_data->dev);
}
}
@@ -2608,10 +2608,10 @@ static int __flush_pasid(struct protection_domain *domain, u32 pasid,
There might be non-IOMMUv2 capable devices in an IOMMUv2
* domain.
*/
- if (!dev_data->ats.enabled)
+ if (!dev_data->ats_enabled)
continue;
- qdep = dev_data->ats.qdep;
+ qdep = dev_data->ats_qdep;
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
continue;
--
2.31.1
next prev parent reply other threads:[~2023-08-04 6:46 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-04 6:42 [PATCH v3 00/16] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 01/16] iommu/amd: Remove unused amd_io_pgtable.pt_root variable Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 02/16] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 03/16] iommu/amd: Consolidate logic to allocate protection domain Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 04/16] iommu/amd: Refactor protection domain allocation code Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 05/16] iommu/amd/iommu_v2: Use protection_domain in struct device_state Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 06/16] iommu/amd: Introduce helper functions for managing GCR3 table Vasant Hegde
2023-08-04 13:17 ` Jason Gunthorpe
2023-08-04 16:51 ` Vasant Hegde
2023-08-04 18:13 ` Jason Gunthorpe
2023-08-07 6:13 ` Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 07/16] iommu/amd: Use struct protection_domain in helper functions Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 08/16] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 09/16] iommu/amd: Miscellaneous clean up when free domain Vasant Hegde
2023-08-04 13:19 ` Jason Gunthorpe
2023-08-04 6:42 ` [PATCH v3 10/16] iommu/amd: Modify logic for checking GT and PPR features Vasant Hegde
2023-08-04 13:19 ` Jason Gunthorpe
2023-08-07 16:44 ` Vasant Hegde
2023-08-08 13:55 ` Jason Gunthorpe
2023-08-10 20:31 ` Suthikulpanit, Suravee
2023-08-11 13:15 ` Jason Gunthorpe
2023-08-11 17:02 ` Suthikulpanit, Suravee
2023-08-04 6:42 ` Vasant Hegde [this message]
2023-08-04 6:42 ` [PATCH v3 12/16] iommu/amd: Add support for different types of PPR handler Vasant Hegde
2023-08-04 13:28 ` Jason Gunthorpe
2023-08-04 16:22 ` Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 13/16] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities Vasant Hegde
2023-08-04 13:36 ` Jason Gunthorpe
2023-08-04 6:42 ` [PATCH v3 14/16] iommu/amd: Enable device ATS/PASID/PRI capabilities independently Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 15/16] iommu/amd: Initialize iommu_device->max_pasids Vasant Hegde
2023-08-04 13:14 ` Jason Gunthorpe
2023-08-07 16:45 ` Vasant Hegde
2023-08-04 6:42 ` [PATCH v3 16/16] iommu/amd: Simplify amd_iommu_device_info() Vasant Hegde
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