From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
jsnitsel@redhat.com
Subject: Re: [PATCH v3 10/13] iommu/amd: Refactor helper function for attaching / detaching device
Date: Mon, 6 Nov 2023 13:29:31 -0400 [thread overview]
Message-ID: <20231106172931.GM4634@ziepe.ca> (raw)
In-Reply-To: <20231013151652.6008-11-vasant.hegde@amd.com>
On Fri, Oct 13, 2023 at 03:16:49PM +0000, Vasant Hegde wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>
> To use the new helper function for setting up GCR3 table.
>
> If system is booted with V2 page table then setup default GCR3 with
> domain GCR3 pointer.
Lets stop talking about "booted with V2 page table" - "If the domain
uses the V2 format then setup a GCR3 table in the device to point to it"
> +static int _init_gcr3_tbl(struct iommu_dev_data *dev_data)
> +{
> + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
> +
> + /* By default, GCR3 is set to support non-PASID devices. */
> + gcr3_info->giov = true;
I admit I find it really hard to read the AMD spec here.. In terms of
the SW model what modes are actually supportable by HW?
No PASIDs being used:
RID domain=IDENTITY - yes [V=0]
RID domain=BLOCKED - yes [V=1, TV=1, GV=0, mode == 0]
RID domain=v1 - Yes [V=1, TV=1, GV=0, mode != 0]
RID domain=v2 - Yes [V=1, TV=0, GV=1, GIOV=1]
Some kind of PASID in use:
RID domain=v2 & PASID - Yes [V=1, TV=0, GV=1, GIOV=1]
RID domain=V1 & PASID - No??
RID domain=IDENTITY & PASID - ?? [V=1, TV=1 GV=1, mode=0, GIOV=0] (Section 2.2.7.1?)
RID domain=BLOCKED & PASID - ?? [V=1, TV=0, GV=1, GIOV=1 with GCR3 entry 0 being non-valid]
Did I get it right? If so GIOV should ultimately be deduced based on
what domain the RID has?
Look at how the SMMUv3 stuff ended up. Their STE is the same purpose
as the AMD DTE. There are alot of combinations here, it was hard to
make a code flow that was clean. It turned out pretty good when the
DTE was generated in the ops->attach based on a calculation of exactly
what the current configuration is, because we already know what we are
in alot of detail at that point.
eg we know if we are attaching an identity domain and PASIDs are in
use that a single specific DTE should be created. So just call a
function directly to get the required DTE.
IOW - I'm not sure it really makes logical sense to store giov in
gcr3_info.
> +static int do_attach(struct iommu_dev_data *dev_data,
> + struct protection_domain *domain)
> {
> struct amd_iommu *iommu;
> + int ret = 0;
>
> iommu = get_amd_iommu_from_dev(dev_data->dev);
> if (!iommu)
> - return;
> + return -EINVAL;
iommu can't be null here, have a dev_data.
> dev_data->domain = domain;
> @@ -2080,11 +2103,27 @@ static void do_attach(struct iommu_dev_data *dev_data,
> if (domain_id_is_per_dev(domain))
> dev_data->domid = domain_id_alloc();
At some point this is the wrong place to put this, the domain ID is
logically associated with the gcr3 table, it should never be used if
there is no gcr table allocated, and it should be freed once the gcr3
table is freed.
> + /* Init GCR3 table */
> + if (domain->pd_mode == PD_MODE_V2) {
Is there a case where domain_id_is_per_dev() but we are attaching a v1
table?
Jason
next prev parent reply other threads:[~2023-11-06 17:29 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 15:16 [PATCH v3 00/13] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 01/13] iommu/amd: Pass struct iommu_dev_data to set_dte_entry() Vasant Hegde
2023-11-05 18:00 ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 02/13] iommu/amd: Introduce get_amd_iommu_from_dev() Vasant Hegde
2023-11-05 18:05 ` Jason Gunthorpe
2023-11-06 11:54 ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 03/13] iommu/amd: Introduce struct protection_domain.pd_mode Vasant Hegde
2023-11-05 18:07 ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 04/13] iommu/amd: Introduce per-device GCR3 table Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 05/13] iommu/amd: Use protection_domain.flags to check page table mode Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 06/13] iommu/amd: Introduce per-device domain ID to workaround potential TLB aliasing issue Vasant Hegde
2023-11-05 18:16 ` Jason Gunthorpe
2023-11-06 12:39 ` Vasant Hegde
2023-11-06 13:36 ` Jason Gunthorpe
2023-11-07 5:30 ` Vasant Hegde
2023-11-07 13:21 ` Jason Gunthorpe
2023-12-12 5:53 ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 07/13] iommu/amd: Add support for device based flush TLB Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 08/13] iommu/amd: Rearrange GCR3 table setup code Vasant Hegde
2023-11-05 18:16 ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 09/13] iommu/amd: Refactor helper function for setting / clearing GCR3 Vasant Hegde
2023-11-06 16:51 ` Jason Gunthorpe
2023-11-07 6:16 ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 10/13] iommu/amd: Refactor helper function for attaching / detaching device Vasant Hegde
2023-11-06 17:29 ` Jason Gunthorpe [this message]
2023-11-07 5:55 ` Vasant Hegde
2023-11-07 13:28 ` Jason Gunthorpe
2023-11-23 17:39 ` Vasant Hegde
2023-11-30 17:55 ` Jason Gunthorpe
2023-12-12 5:41 ` Vasant Hegde
2023-12-12 14:59 ` Jason Gunthorpe
2023-12-18 5:17 ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 11/13] iommu/amd: Refactor protection_domain helper functions Vasant Hegde
2023-11-06 17:30 ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 12/13] iommu/amd: Refactor GCR3 table " Vasant Hegde
2023-11-06 17:40 ` Jason Gunthorpe
2023-11-07 6:13 ` Vasant Hegde
2023-11-07 13:31 ` Jason Gunthorpe
2023-11-23 17:23 ` Vasant Hegde
2023-11-23 17:24 ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 13/13] iommu/amd: Remove unused GCR3 table parameters from struct protection_domain Vasant Hegde
2023-11-06 17:33 ` Jason Gunthorpe
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