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From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org,
	suravee.suthikulpanit@amd.com, wei.huang2@amd.com,
	jsnitsel@redhat.com
Subject: Re: [PATCH v3 12/13] iommu/amd: Refactor GCR3 table helper functions
Date: Mon, 6 Nov 2023 13:40:03 -0400	[thread overview]
Message-ID: <20231106174003.GP4634@ziepe.ca> (raw)
In-Reply-To: <20231013151652.6008-13-vasant.hegde@amd.com>

On Fri, Oct 13, 2023 at 03:16:51PM +0000, Vasant Hegde wrote:
> -static void free_gcr3_table(struct protection_domain *domain)
> +static void free_gcr3_table(struct iommu_dev_data *dev_data)
>  {
> -	if (domain->glx == 2)
> -		free_gcr3_tbl_level2(domain->gcr3_tbl);
> -	else if (domain->glx == 1)
> -		free_gcr3_tbl_level1(domain->gcr3_tbl);
> +	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
> +	struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
> +
> +	if (gcr3_info->glx == 2)
> +		free_gcr3_tbl_level2(gcr3_info->gcr3_tbl);
> +	else if (gcr3_info->glx == 1)
> +		free_gcr3_tbl_level1(gcr3_info->gcr3_tbl);
>  	else
> -		BUG_ON(domain->glx != 0);
> +		WARN_ON_ONCE(gcr3_info->glx != 0);
> +
> +	gcr3_info->glx = 0;
> +
> +	set_dte_entry(iommu, dev_data);
> +	clone_aliases(iommu, dev_data->dev);
> +	device_flush_dte(dev_data);

This looks super wonky. We free some of the gcr3 memory and *then*
update the DTE? Is that ordered properly?

As per my prior email the caller should have already updated the DTE
because it attached some non-gcr3 needing thing. Once the new DTE is
in place then free_gcr3_table() should simply just free the allocated
memory.

Commingling DTE manipulation inside the gcr3 layer is not good layering.

You should be moving to a direction where the ops->attach_dev does
exactly one update to the DTE. It loads the new correct value of the
DTE that attach_dev is asking to create. All this repeated touching of
the DTE during the attach_dev flow is sort of a functional bug, or at
least a sub-optimal implementation of the API.

> -/* Note: This function expects iommu_domain->lock to be held prior calling the function. */
> -static int setup_gcr3_table(struct protection_domain *domain, int pasids)
> +static int setup_gcr3_table(struct iommu_dev_data *dev_data, int pasids)
>  {
> +	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
> +	struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
>  	int levels = get_gcr3_levels(pasids);
>  
>  	if (levels > amd_iommu_max_glx_val)
>  		return -EINVAL;
>  
> -	domain->gcr3_tbl = alloc_pgtable_page(domain->nid, GFP_ATOMIC);
> -	if (domain->gcr3_tbl == NULL)
> +	if (gcr3_info->gcr3_tbl)
> +		return -EBUSY;
> +
> +	gcr3_info->gcr3_tbl = alloc_pgtable_page(dev_to_node(dev_data->dev),
> +						 GFP_ATOMIC);
> +	if (gcr3_info->gcr3_tbl == NULL)
>  		return -ENOMEM;

Why is this in an atomic context? I can understand that the domain was
because it used a spinlock, but this should now be locked by the group
mutex which is not atomic.

Jason

  reply	other threads:[~2023-11-06 17:40 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-13 15:16 [PATCH v3 00/13] iommu/amd: SVA Support (part 3) - refactor support for GCR3 table Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 01/13] iommu/amd: Pass struct iommu_dev_data to set_dte_entry() Vasant Hegde
2023-11-05 18:00   ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 02/13] iommu/amd: Introduce get_amd_iommu_from_dev() Vasant Hegde
2023-11-05 18:05   ` Jason Gunthorpe
2023-11-06 11:54     ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 03/13] iommu/amd: Introduce struct protection_domain.pd_mode Vasant Hegde
2023-11-05 18:07   ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 04/13] iommu/amd: Introduce per-device GCR3 table Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 05/13] iommu/amd: Use protection_domain.flags to check page table mode Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 06/13] iommu/amd: Introduce per-device domain ID to workaround potential TLB aliasing issue Vasant Hegde
2023-11-05 18:16   ` Jason Gunthorpe
2023-11-06 12:39     ` Vasant Hegde
2023-11-06 13:36       ` Jason Gunthorpe
2023-11-07  5:30         ` Vasant Hegde
2023-11-07 13:21           ` Jason Gunthorpe
2023-12-12  5:53             ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 07/13] iommu/amd: Add support for device based flush TLB Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 08/13] iommu/amd: Rearrange GCR3 table setup code Vasant Hegde
2023-11-05 18:16   ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 09/13] iommu/amd: Refactor helper function for setting / clearing GCR3 Vasant Hegde
2023-11-06 16:51   ` Jason Gunthorpe
2023-11-07  6:16     ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 10/13] iommu/amd: Refactor helper function for attaching / detaching device Vasant Hegde
2023-11-06 17:29   ` Jason Gunthorpe
2023-11-07  5:55     ` Vasant Hegde
2023-11-07 13:28       ` Jason Gunthorpe
2023-11-23 17:39         ` Vasant Hegde
2023-11-30 17:55           ` Jason Gunthorpe
2023-12-12  5:41             ` Vasant Hegde
2023-12-12 14:59               ` Jason Gunthorpe
2023-12-18  5:17                 ` Vasant Hegde
2023-10-13 15:16 ` [PATCH v3 11/13] iommu/amd: Refactor protection_domain helper functions Vasant Hegde
2023-11-06 17:30   ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 12/13] iommu/amd: Refactor GCR3 table " Vasant Hegde
2023-11-06 17:40   ` Jason Gunthorpe [this message]
2023-11-07  6:13     ` Vasant Hegde
2023-11-07 13:31       ` Jason Gunthorpe
2023-11-23 17:23         ` Vasant Hegde
2023-11-23 17:24           ` Jason Gunthorpe
2023-10-13 15:16 ` [PATCH v3 13/13] iommu/amd: Remove unused GCR3 table parameters from struct protection_domain Vasant Hegde
2023-11-06 17:33   ` Jason Gunthorpe

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