From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <will@kernel.org>, <robin.murphy@arm.com>,
<suravee.suthikulpanit@amd.com>, <jgg@ziepe.ca>,
<yi.l.liu@intel.com>, <baolu.lu@linux.intel.com>,
<kevin.tian@intel.com>, Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH 3/5] iommu/amd: Pass page table type to pdomain_setup_pgtable()
Date: Wed, 21 Aug 2024 13:35:52 +0000 [thread overview]
Message-ID: <20240821133554.7405-4-vasant.hegde@amd.com> (raw)
In-Reply-To: <20240821133554.7405-1-vasant.hegde@amd.com>
Current code forces v1 page table for UNMANAGED domain and global page
table type (amd_iommu_pgtable) for rest of paging domain.
Following patch series adds support for domain_alloc_paging() ops. Also
enhances domain_alloc_user() to allocate page table based on 'flags.
Hence pass page table type to parameter to pdomain_setup_pgtable(). So
that caller can decide right page table type. Also update
dma_max_address() to take pgtable as parameter.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
---
drivers/iommu/amd/iommu.c | 50 +++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 26 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 33930e08bd4c..817a26727894 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2324,29 +2324,14 @@ struct protection_domain *protection_domain_alloc(unsigned int type)
}
static int pdom_setup_pgtable(struct protection_domain *domain,
- unsigned int type)
+ int pgtable)
{
struct io_pgtable_ops *pgtbl_ops;
- int pgtable;
int ret;
- switch (type) {
- /* No need to allocate io pgtable ops in passthrough mode */
- case IOMMU_DOMAIN_IDENTITY:
+ if (!(domain->domain.type & __IOMMU_DOMAIN_PAGING))
return 0;
- case IOMMU_DOMAIN_DMA:
- pgtable = amd_iommu_pgtable;
- break;
- /*
- * Force IOMMU v1 page table when allocating
- * domain for pass-through devices.
- */
- case IOMMU_DOMAIN_UNMANAGED:
- pgtable = AMD_IOMMU_V1;
- break;
- default:
- return -EINVAL;
- }
+
switch (pgtable) {
case AMD_IOMMU_V1:
ret = protection_domain_init_v1(domain, DEFAULT_PGTABLE_LEVEL);
@@ -2368,9 +2353,9 @@ static int pdom_setup_pgtable(struct protection_domain *domain,
return 0;
}
-static inline u64 dma_max_address(void)
+static inline u64 dma_max_address(int pgtable)
{
- if (amd_iommu_pgtable == AMD_IOMMU_V1)
+ if (pgtable == AMD_IOMMU_V1)
return ~0ULL;
/* V2 with 4/5 level page table */
@@ -2383,7 +2368,8 @@ static bool amd_iommu_hd_support(struct amd_iommu *iommu)
}
static struct iommu_domain *do_iommu_domain_alloc(unsigned int type,
- struct device *dev, u32 flags)
+ struct device *dev,
+ u32 flags, int pgtable)
{
bool dirty_tracking = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING;
struct protection_domain *domain;
@@ -2407,18 +2393,22 @@ static struct iommu_domain *do_iommu_domain_alloc(unsigned int type,
if (!domain)
return ERR_PTR(-ENOMEM);
- ret = pdom_setup_pgtable(domain, type);
+ ret = pdom_setup_pgtable(domain, pgtable);
if (ret) {
protection_domain_free(domain);
return ERR_PTR(ret);
}
domain->domain.geometry.aperture_start = 0;
- domain->domain.geometry.aperture_end = dma_max_address();
+ domain->domain.geometry.aperture_end = dma_max_address(pgtable);
domain->domain.geometry.force_aperture = true;
if (iommu) {
- domain->domain.pgsize_bitmap = iommu->iommu.ops->pgsize_bitmap;
+ if (pgtable == AMD_IOMMU_V2)
+ domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
+ else
+ domain->domain.pgsize_bitmap = iommu->iommu.ops->pgsize_bitmap;
+
domain->domain.ops = iommu->iommu.ops->default_domain_ops;
if (dirty_tracking)
@@ -2431,8 +2421,16 @@ static struct iommu_domain *do_iommu_domain_alloc(unsigned int type,
static struct iommu_domain *amd_iommu_domain_alloc(unsigned int type)
{
struct iommu_domain *domain;
+ int pgtable = amd_iommu_pgtable;
+
+ /*
+ * Force IOMMU v1 page table when allocating
+ * domain for pass-through devices.
+ */
+ if (type == IOMMU_DOMAIN_UNMANAGED)
+ pgtable = AMD_IOMMU_V1;
- domain = do_iommu_domain_alloc(type, NULL, 0);
+ domain = do_iommu_domain_alloc(type, NULL, 0, pgtable);
if (IS_ERR(domain))
return NULL;
@@ -2450,7 +2448,7 @@ amd_iommu_domain_alloc_user(struct device *dev, u32 flags,
if ((flags & ~IOMMU_HWPT_ALLOC_DIRTY_TRACKING) || parent || user_data)
return ERR_PTR(-EOPNOTSUPP);
- return do_iommu_domain_alloc(type, dev, flags);
+ return do_iommu_domain_alloc(type, dev, flags, AMD_IOMMU_V1);
}
void amd_iommu_domain_free(struct iommu_domain *dom)
--
2.31.1
next prev parent reply other threads:[~2024-08-21 13:37 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 13:35 [PATCH 0/5] iommu: Domain allocation enhancements Vasant Hegde
2024-08-21 13:35 ` [PATCH 1/5] iommu: Enhance domain allocation code to take additional flags Vasant Hegde
2024-08-21 16:31 ` Jason Gunthorpe
2024-08-22 1:50 ` Baolu Lu
2024-08-22 12:43 ` Jason Gunthorpe
2024-08-23 2:47 ` Baolu Lu
2024-08-26 8:08 ` Tian, Kevin
2024-08-26 8:34 ` Baolu Lu
2024-08-26 8:59 ` Tian, Kevin
2024-08-26 13:51 ` Jason Gunthorpe
2024-08-26 8:47 ` Vasant Hegde
2024-08-26 13:45 ` Jason Gunthorpe
2024-08-22 11:27 ` Yi Liu
2024-08-22 12:44 ` Jason Gunthorpe
2024-08-23 8:58 ` Yi Liu
2024-08-24 14:47 ` Vasant Hegde
2024-08-28 21:52 ` Jacob Pan
2024-08-29 10:51 ` Vasant Hegde
2024-08-29 12:10 ` Jason Gunthorpe
2024-08-29 12:47 ` Vasant Hegde
2024-08-29 13:11 ` Jason Gunthorpe
2024-09-11 10:54 ` Vasant Hegde
2024-08-29 17:40 ` Jacob Pan
[not found] ` <66d0b2a1.630a0220.1dd301.daceSMTPIN_ADDED_BROKEN@mx.google.com>
2024-08-30 15:00 ` Jason Gunthorpe
2024-08-26 8:36 ` Vasant Hegde
2024-08-26 13:56 ` Jason Gunthorpe
2024-08-29 12:34 ` Vasant Hegde
2024-08-22 1:38 ` Baolu Lu
2024-08-22 12:40 ` Jason Gunthorpe
2024-08-23 2:04 ` Baolu Lu
2024-08-26 6:09 ` Vasant Hegde
2024-08-22 2:10 ` kernel test robot
2024-08-22 3:03 ` kernel test robot
2024-08-22 5:07 ` kernel test robot
2024-08-21 13:35 ` [PATCH 2/5] iommu/amd: Separate page table setup from domain allocation Vasant Hegde
2024-08-21 16:40 ` Jason Gunthorpe
2024-08-21 13:35 ` Vasant Hegde [this message]
2024-08-21 13:35 ` [PATCH 4/5] iommu/amd: Enhance domain_alloc_user() to allocate PASID capable domain Vasant Hegde
2024-08-21 13:35 ` [PATCH 5/5] iommu/amd: Add iommu_ops->domain_alloc_paging support Vasant Hegde
2024-08-21 15:57 ` Jason Gunthorpe
2024-09-11 10:44 ` Vasant Hegde
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