Re: [PATCH v6 09/14] iommu/vt-d: Add IOMMU_HWPT_ALLOC_PASID support

[Jason Gunthorpe <jgg@nvidia.com>]

On Wed, Feb 12, 2025 at 01:00:11PM +0000, Robin Murphy wrote:
> Yup, SMMUv3 is more or less in the same boat - we *could* reasonably manage
> unpinned S2 for non-PCI devices using the stall model where the
> F_TRANSLATION or F_PERMISSION event tells us all we need, but for ATS it's
> the same thing where by the time the fault has taken a round-trip through an
> ATS response and a PRI request,

I belive there is interest in PCISIG about this topic.

> we've lost the details of exactly how it faulted (or if the PRI
> request was sent eagerly without a prior translation request, then
> we simply have no idea at all). Thus the prospective mechanism would
> be to inject a virtual PRI, wait until we see the guest issue a
> matching CMD_PRI_RESP, then sniff the IPA/GPA for the given input
> address out of the guest pagetables to see if there's anything to do
> at S2 as well/instead. Yuck.

I vaugely recall AMD HW will run the PRI through the page tables to
figure out if it is S1/S2... Vasant?

Jason