From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: baolu.lu@linux.intel.com, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Kevin Tian <kevin.tian@intel.com>, Jann Horn <jannh@google.com>,
Vasant Hegde <vasant.hegde@amd.com>,
Dave Hansen <dave.hansen@intel.com>,
Alistair Popple <apopple@nvidia.com>,
Peter Zijlstra <peterz@infradead.org>,
Uladzislau Rezki <urezki@gmail.com>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Andy Lutomirski <luto@kernel.org>,
iommu@lists.linux.dev, security@kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush
Date: Sat, 5 Jul 2025 11:50:49 +0800 [thread overview]
Message-ID: <79ea9027-179a-460b-8a91-86e38feba986@linux.intel.com> (raw)
In-Reply-To: <20250704133807.GB1410929@nvidia.com>
On 7/4/2025 9:38 PM, Jason Gunthorpe wrote:
> On Fri, Jul 04, 2025 at 09:30:56PM +0800, Lu Baolu wrote:
>> The vmalloc() and vfree() functions manage virtually contiguous, but not
>> necessarily physically contiguous, kernel memory regions. When vfree()
>> unmaps such a region, it tears down the associated kernel page table
>> entries and frees the physical pages.
>>
>> In the IOMMU Shared Virtual Addressing (SVA) context, the IOMMU hardware
>> shares and walks the CPU's page tables. Architectures like x86 share
>> static kernel address mappings across all user page tables, allowing the
>> IOMMU to access the kernel portion of these tables.
>>
>> Modern IOMMUs often cache page table entries to optimize walk performance,
>> even for intermediate page table levels. If kernel page table mappings are
>> changed (e.g., by vfree()), but the IOMMU's internal caches retain stale
>> entries, Use-After-Free (UAF) vulnerability condition arises. If these
>> freed page table pages are reallocated for a different purpose, potentially
>> by an attacker, the IOMMU could misinterpret the new data as valid page
>> table entries. This allows the IOMMU to walk into attacker-controlled
>> memory, leading to arbitrary physical memory DMA access or privilege
>> escalation.
>>
>> To mitigate this, introduce a new iommu interface to flush IOMMU caches
>> and fence pending page table walks when kernel page mappings are updated.
>> This interface should be invoked from architecture-specific code that
>> manages combined user and kernel page tables.
>>
>> Fixes: 26b25a2b98e4 ("iommu: Bind process address spaces to devices")
>> Cc:stable@vger.kernel.org
>> Co-developed-by: Jason Gunthorpe<jgg@nvidia.com>
>> Signed-off-by: Jason Gunthorpe<jgg@nvidia.com>
>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>> ---
>> arch/x86/mm/tlb.c | 2 ++
>> drivers/iommu/iommu-sva.c | 32 +++++++++++++++++++++++++++++++-
>> include/linux/iommu.h | 4 ++++
>> 3 files changed, 37 insertions(+), 1 deletion(-)
> Reported-by: Jann Horn<jannh@google.com>
>
>> @@ -1540,6 +1541,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
>> kernel_tlb_flush_range(info);
>>
>> put_flush_tlb_info();
>> + iommu_sva_invalidate_kva_range(start, end);
>> }
> This is much less call sites than I guessed!
>
>> +void iommu_sva_invalidate_kva_range(unsigned long start, unsigned long end)
>> +{
>> + struct iommu_mm_data *iommu_mm;
>> +
>> + might_sleep();
>> +
>> + if (!static_branch_unlikely(&iommu_sva_present))
>> + return;
>> +
>> + guard(mutex)(&iommu_sva_lock);
>> + list_for_each_entry(iommu_mm, &iommu_sva_mms, mm_list_elm)
>> + mmu_notifier_arch_invalidate_secondary_tlbs(iommu_mm->mm, start, end);
>> +}
>> +EXPORT_SYMBOL_GPL(iommu_sva_invalidate_kva_range);
> I don't think it needs to be exported it only arch code is calling it?
Yes. Done.
>
> Looks Ok to me:
>
> Reviewed-by: Jason Gunthorpe<jgg@nvidia.com>
Thanks,
baolu
next prev parent reply other threads:[~2025-07-05 3:50 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-04 13:30 [PATCH 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush Lu Baolu
2025-07-04 13:38 ` Jason Gunthorpe
2025-07-05 3:50 ` Baolu Lu [this message]
2025-07-05 9:06 ` Vasant Hegde
2025-07-08 5:42 ` Baolu Lu
2025-07-08 12:27 ` Jason Gunthorpe
2025-07-08 14:06 ` Jason Gunthorpe
2025-07-09 1:25 ` Baolu Lu
2025-07-09 15:51 ` Jacob Pan
2025-07-09 16:27 ` Jason Gunthorpe
2025-07-09 18:15 ` Jacob Pan
2025-07-09 18:22 ` Dave Hansen
2025-07-09 18:44 ` Jacob Pan
2025-07-09 18:54 ` Jason Gunthorpe
2025-07-14 12:39 ` David Laight
2025-07-14 13:19 ` Uladzislau Rezki
2025-07-14 14:50 ` Mike Rapoport
2025-07-15 0:05 ` Tian, Kevin
2025-07-15 1:19 ` Baolu Lu
2025-07-10 2:57 ` Baolu Lu
2025-07-10 15:28 ` Jacob Pan
2025-07-10 15:35 ` Jason Gunthorpe
2025-07-11 14:36 ` Dave Hansen
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