From: Jason Gunthorpe <jgg@ziepe.ca>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH 11/21] iommu/amd: Clean up and enhance protection domain flags
Date: Fri, 14 Jul 2023 14:25:51 -0300 [thread overview]
Message-ID: <ZLGFH6qERiRbD6cd@ziepe.ca> (raw)
In-Reply-To: <20230712141516.154144-12-vasant.hegde@amd.com>
On Wed, Jul 12, 2023 at 02:15:06PM +0000, Vasant Hegde wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
>
> With IOMMU v1 and v2 page tables per domain, and the v2 table can
> be used in various modes, keeping track of how a particular domain
> is configured becoming cumbersome.
>
> Enhance protection_domain.flags to keep track of how a domain is
> configured. Also Remove unused flags, and rename them accordingly.
>
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
> drivers/iommu/amd/amd_iommu_types.h | 14 +++++---------
> drivers/iommu/amd/io_pgtable_v2.c | 2 +-
> drivers/iommu/amd/iommu.c | 21 ++++++++++++---------
> 3 files changed, 18 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
> index 346c32343417..907af6e41ae9 100644
> --- a/drivers/iommu/amd/amd_iommu_types.h
> +++ b/drivers/iommu/amd/amd_iommu_types.h
> @@ -443,13 +443,11 @@
> #define MAX_DOMAIN_ID 65536
>
> /* Protection domain flags */
> -#define PD_DMA_OPS_MASK BIT(0) /* domain used for dma_ops */
> -#define PD_DEFAULT_MASK BIT(1) /* domain is a default dma_ops
> - domain for an IOMMU */
> -#define PD_PASSTHROUGH_MASK BIT(2) /* domain has no page
> - translation */
> -#define PD_IOMMUV2_MASK BIT(3) /* domain has gcr3 table */
> -#define PD_GIOV_MASK BIT(4) /* domain enable GIOV support */
> +#define PD_FLAG_V1DMA BIT(1) /* DMA-API mode w/ v1 page table */
> +#define PD_FLAG_V2DMA BIT(2) /* DMA-API mode w/ v2 page table */
"DMA-API" should not be part of the driver vocabulary. Does this have
anything to do with DMA-API?
Only "paging" domains should have IO page tables and an IO page table
type.
Maybe this is just misnamed?
Also, shouldn't it be an enum not flags?
> +#define PD_FLAG_PT BIT(0) /* Passthrough mode */
> +#define PD_FLAG_GCR3 BIT(3) /* domain has gcr3 table */
These seem redundant with the domain type?
Maybe a few helpers?
> +#define PD_FLAG_GIOV BIT(4) /* domain enable GIOV support */
This really shouldn't be a iommu_domain flag, this should be computed
based on what domains are attached where
Eg this seems like it should be triggered by attaching identity to the
RID with PASID enabled or something like that.
Why do you need to set it for the legacy GPU path?
Jason
next prev parent reply other threads:[~2023-07-14 17:25 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 14:14 [PATCH 00/21] iommu/amd: Preparation for SVA Support (Part 1 of 2) Vasant Hegde
2023-07-12 14:14 ` [PATCH 01/21] iommu/amd: Remove unused amd_io_pgtable.pt_root variable Vasant Hegde
2023-07-12 14:14 ` [PATCH 02/21] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h Vasant Hegde
2023-07-12 14:14 ` [PATCH 03/21] iommu/amd: Consolidate logic to allocate protection domain Vasant Hegde
2023-07-12 14:14 ` [PATCH 04/21] iommu/amd: Refactor protection domain allocation code Vasant Hegde
2023-07-12 14:15 ` [PATCH 05/21] iommu/amd/iommu_v2: Use protection_domain in struct device_state Vasant Hegde
2023-07-12 14:15 ` [PATCH 06/21] iommu/amd: Introduce helper functions for managing GCR3 table Vasant Hegde
2023-07-12 14:15 ` [PATCH 07/21] iommu/amd: Use struct protection_domain in helper functions Vasant Hegde
2023-07-14 16:57 ` Jason Gunthorpe
2023-07-12 14:15 ` [PATCH 08/21] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode Vasant Hegde
2023-07-12 14:15 ` [PATCH 09/21] iommu/amd: Miscellaneous clean up when free domain Vasant Hegde
2023-07-12 14:15 ` [PATCH 10/21] iommu/amd: Modify logic for checking GT and PPR features Vasant Hegde
2023-07-12 14:15 ` [PATCH 11/21] iommu/amd: Clean up and enhance protection domain flags Vasant Hegde
2023-07-14 17:25 ` Jason Gunthorpe [this message]
2023-07-17 1:22 ` Suthikulpanit, Suravee
2023-07-17 12:23 ` Jason Gunthorpe
2023-07-18 6:38 ` Suthikulpanit, Suravee
2023-07-18 12:36 ` Jason Gunthorpe
2023-07-28 5:43 ` Vasant Hegde
2023-07-12 14:15 ` [PATCH 12/21] iommu/amd: Use protection_domain.flags to check page table mode Vasant Hegde
2023-07-12 14:15 ` [PATCH 13/21] iommu/amd: Consolidate logic for setting up v2 API mode Vasant Hegde
2023-07-12 14:15 ` [PATCH 14/21] iommu/amd: Refactor domain allocation code for v2DMA mode Vasant Hegde
2023-07-12 14:15 ` [PATCH 15/21] iommu/amd: Setup v2 domain with max pasids Vasant Hegde
2023-07-12 14:15 ` [PATCH 16/21] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities Vasant Hegde
2023-07-12 14:15 ` [PATCH 17/21] iommu/amd: Rename ats related variables Vasant Hegde
2023-07-12 14:15 ` [PATCH 18/21] iommu/amd: Enable device ATS/PASID/PRI capabilities independently Vasant Hegde
2023-07-12 14:15 ` [PATCH 19/21] iommu/amd: Delay enabling PRI to after initializing domain Vasant Hegde
2023-07-12 14:15 ` [PATCH 20/21] iommu/amd: Initialize iommu_device->max_pasids Vasant Hegde
2023-07-12 14:15 ` [PATCH 21/21] iommu/amd: Simplify amd_iommu_device_info() Vasant Hegde
2023-07-14 17:53 ` [PATCH 00/21] iommu/amd: Preparation for SVA Support (Part 1 of 2) Jason Gunthorpe
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