[PATCH 0/2] selftests/arm64: Add cmpbr_sigill() and fix sve2p1_sigill() for hwcap test

[PATCH 0/2] selftests/arm64: Add cmpbr_sigill() and fix sve2p1_sigill() for hwcap test

[Yifan Wu]

Hi all,

This patch series adds and fixes two selftests in the arm64 hwcap
test suite.

Patch 1/2 implements the cmpbr_sigill() test to correctly detect
the presence of the CMPBR extension. The test uses the CBEQ
instruction, which is valid only if the CPU supports the extension.
If supported, a branch is taken and the UDF instruction is skipped,
avoiding a SIGILL. Otherwise, the UDF is executed and a SIGILL
is generated.

Patch 2/2 fixes the sve2p1_sigill() test to correctly detect the
FEAT_SVE2p1 feature. Previously, the test incorrectly assumed that
the presence of FEAT_SVE2.1 implied support for the BFADD
instruction, which actually depends on the FEAT_SVE_B16B16 feature.
The test is updated to use the LD1Q instruction, which is
unambiguously implied by FEAT_SVE2p1.

These changes improve the accuracy and reliability of the selftests
for arm64 hardware capability detection.

References:

CBEQ: https://developer.arm.com/documentation/ddi0602/2025-12/Base-Instructions/CB-cc---register---Compare-registers-and-branch-?lang=en
BFADD: https://developer.arm.com/documentation/ddi0602/2025-12/SVE-Instructions/BFADD--unpredicated---BFloat16-add--unpredicated--?lang=en
LD1Q: https://developer.arm.com/documentation/ddi0602/2025-12/SVE-Instructions/LD1Q--Gather-load-quadwords-?lang=en
ID_AA64ZFR0_EL1: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/ID-AA64ZFR0-EL1--SVE-Feature-ID-Register-0?lang=en

Yifan Wu (2):
  selftests/arm64: Implement cmpbr_sigill() to hwcap test
  selftest/arm64: Fix sve2p1_sigill() to hwcap test

 tools/testing/selftests/arm64/abi/hwcap.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

-- 
2.33.0

[PATCH 1/2] selftests/arm64: Implement cmpbr_sigill() to hwcap test

[Yifan Wu]

The function executes a CBEQ instruction which is valid if the CPU
supports the CMPBR extension. The CBEQ branches to skip the following
UDF instruction, and no SIGILL is generated. Otherwise, it will
generate a SIGILL.

Signed-off-by: Yifan Wu <wuyifan50@huawei.com>
---
 tools/testing/selftests/arm64/abi/hwcap.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index 9d2df1f3e6bb..0d229804a857 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -56,7 +56,10 @@ static void atomics_sigill(void)
 
 static void cmpbr_sigill(void)
 {
-	/* Not implemented, too complicated and unreliable anyway */
+	/* CBEQ x0, x0, +8 */
+	asm volatile(".inst 0x74C00040" : : : "x0");
+	/* UDF #0 */
+	asm volatile("udf #0" : : : );
 }
 
 static void crc32_sigill(void)
-- 
2.33.0

[PATCH 2/2] selftest/arm64: Fix sve2p1_sigill() to hwcap test

[Yifan Wu]

The FEAT_SVE2p1 is indicated by ID_AA64ZFR0_EL1.SVEver. However,
the BFADD requires the FEAT_SVE_B16B16, which is indicated by
ID_AA64ZFR0_EL1.B16B16. This could cause the test to incorrectly
fail on a CPU that supports FEAT_SVE2.1 but not FEAT_SVE_B16B16.

LD1Q Gather load quadwords which is decoded from SVE encodings and
implied by FEAT_SVE2p1.

Fixes: c5195b027d29 ("kselftest/arm64: Add SVE 2.1 to hwcap test")
Signed-off-by: Yifan Wu <wuyifan50@huawei.com>
---
 tools/testing/selftests/arm64/abi/hwcap.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c
index 0d229804a857..e8b22a60326c 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -478,8 +478,8 @@ static void sve2_sigill(void)
 
 static void sve2p1_sigill(void)
 {
-	/* BFADD Z0.H, Z0.H, Z0.H */
-	asm volatile(".inst 0x65000000" : : : "z0");
+	/* LD1Q Z0.Q, P0/Z, Z0.D, X0 */
+	asm volatile(".inst 0xC400A000" : : : "z0");
 }
 
 static void sve2p2_sigill(void)
-- 
2.33.0

Re: [PATCH 1/2] selftests/arm64: Implement cmpbr_sigill() to hwcap test

[Mark Brown]

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On Fri, Feb 27, 2026 at 11:19:32AM +0800, Yifan Wu wrote:

>  static void cmpbr_sigill(void)
>  {
> -	/* Not implemented, too complicated and unreliable anyway */
> +	/* CBEQ x0, x0, +8 */
> +	asm volatile(".inst 0x74C00040" : : : "x0");
> +	/* UDF #0 */
> +	asm volatile("udf #0" : : : );
>  }

I don't expect it to make a difference but it'd be nice if these were a
single asm volatile statement, just to make it absolutely clear that no
instrumentation or anything is supposed to go between the two.

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Re: [PATCH 2/2] selftest/arm64: Fix sve2p1_sigill() to hwcap test

[Mark Brown]

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On Fri, Feb 27, 2026 at 11:19:33AM +0800, Yifan Wu wrote:
> The FEAT_SVE2p1 is indicated by ID_AA64ZFR0_EL1.SVEver. However,
> the BFADD requires the FEAT_SVE_B16B16, which is indicated by
> ID_AA64ZFR0_EL1.B16B16. This could cause the test to incorrectly
> fail on a CPU that supports FEAT_SVE2.1 but not FEAT_SVE_B16B16.
> 
> LD1Q Gather load quadwords which is decoded from SVE encodings and
> implied by FEAT_SVE2p1.

Ah, good spot - I think my search for instructions to use got confused
by them mention of SVE2 in the description of BFADD.  Since this is a
fix it should really be patch 1.

> -	/* BFADD Z0.H, Z0.H, Z0.H */
> -	asm volatile(".inst 0x65000000" : : : "z0");
> +	/* LD1Q Z0.Q, P0/Z, Z0.D, X0 */

That should be:

	LD1Q {Z0.Q}, P0/Z, [Z0.D, X0]

(the existing asm has some issues which we ought to get round fixing but
may as well keep the new stuff good.)

> +	asm volatile(".inst 0xC400A000" : : : "z0");

Verified the decode with objdump.  With the above change to the comment:

Reviewed-by: Mark Brown <broonie@kernel.org> 

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Re: [PATCH 2/2] selftest/arm64: Fix sve2p1_sigill() to hwcap test

[wuyifan]

Hi Mark,

On 2/28/2026 9:39 PM, Mark Brown wrote:
> On Fri, Feb 27, 2026 at 11:19:33AM +0800, Yifan Wu wrote:
>> The FEAT_SVE2p1 is indicated by ID_AA64ZFR0_EL1.SVEver. However,
>> the BFADD requires the FEAT_SVE_B16B16, which is indicated by
>> ID_AA64ZFR0_EL1.B16B16. This could cause the test to incorrectly
>> fail on a CPU that supports FEAT_SVE2.1 but not FEAT_SVE_B16B16.
>>
>> LD1Q Gather load quadwords which is decoded from SVE encodings and
>> implied by FEAT_SVE2p1.
> Ah, good spot - I think my search for instructions to use got confused
> by them mention of SVE2 in the description of BFADD.  Since this is a
> fix it should really be patch 1.
>
>> -	/* BFADD Z0.H, Z0.H, Z0.H */
>> -	asm volatile(".inst 0x65000000" : : : "z0");
>> +	/* LD1Q Z0.Q, P0/Z, Z0.D, X0 */
> That should be:
>
> 	LD1Q {Z0.Q}, P0/Z, [Z0.D, X0]
>
> (the existing asm has some issues which we ought to get round fixing but
> may as well keep the new stuff good.)
>
>> +	asm volatile(".inst 0xC400A000" : : : "z0");
> Verified the decode with objdump.  With the above change to the comment:
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
Thanks a lot for the review and the tag! I'll update the comment and re-
order the patches in v2.

Regards,
Yifan Wu

Re: [PATCH 1/2] selftests/arm64: Implement cmpbr_sigill() to hwcap test

[wuyifan]

Hi Mark,

On 2/28/2026 9:23 PM, Mark Brown wrote:
> On Fri, Feb 27, 2026 at 11:19:32AM +0800, Yifan Wu wrote:
>
>>   static void cmpbr_sigill(void)
>>   {
>> -	/* Not implemented, too complicated and unreliable anyway */
>> +	/* CBEQ x0, x0, +8 */
>> +	asm volatile(".inst 0x74C00040" : : : "x0");
>> +	/* UDF #0 */
>> +	asm volatile("udf #0" : : : );
>>   }
> I don't expect it to make a difference but it'd be nice if these were a
> single asm volatile statement, just to make it absolutely clear that no
> instrumentation or anything is supposed to go between the two.
Thanks for the review. That's a good point, I'll combine them in v2.

Regards,
Yifan Wu