Re: [PATCH] m68k/mvme16x: Fix timer interrupts

[Finn Thain <fthain@telegraphics.com.au>]

On Thu, 18 Mar 2021, Michael Pavone wrote:

> On 3/17/21 8:05 PM, Finn Thain wrote:
> 
> > On Tue, 16 Mar 2021, Mike Pavone wrote:
> >
> >> Timer interrupts on MVME16x and MVME17x boards are broken as the CEN and
> >> COC bits are being inadvertently cleared when clearing the overflow
> >> counter. This results in no timer interrupts being delivered after the
> >> first. Initialization then hangs in calibrate_delay as the jiffies counter
> >> is not updated. OR with current register value to preserve these bits.
> >>
> >> Fixes: 19999a8b8782 ("m68k: mvme16x: Handle timer counter overflow")
> >> Signed-off-by: Michael Pavone <pavone@retrodev.com>
> > Sorry about that regression.
> >
> > Do you think that commit 7529b90d051e ("m68k: mvme147: Handle timer 
> > counter overflow") has the same problem?
> 
> I don't have an MVME147 board to test with, but based on the 
> documentation it looks like it does. The clear bit is in the same 
> register as the enable and count enable bits on the original PCCchip.
> 

OK. I will write a patch for mvme147.

BTW, assuming you did get the kernel running on your hardware, do you know 
if there's any need for the '#warning check me!' that still remains in 
arch/m68k/mvme16x/config.c and arch/m68k/mvme147/config.c?