[PATCH 0/8] media: iris: port support for Qualcomm SC7280

[PATCH 0/8] media: iris: port support for Qualcomm SC7280

[Dmitry Baryshkov]

Port Support for the Qualcomm SC7280 aka QCM6490 aka QCS6490 platform
from the existing venus driver to the newer Iris driver. The firmware on
this platform uses the older, gen1 HFI, which puts it close to SM8250
from both the hardware and interface point of view.

Test results:

$ ./fluster.py r -d GStreamer-H.264-V4L2-Gst1.0 -ts JVT-AVC_V1
...
Ran 77/135 tests successfully               in 17.010 secs

$ ./fluster.py r -d GStreamer-H.265-V4L2-Gst1.0 -ts JCT-VC-HEVC_V1 -j 1

Only WPP_E_ericsson_MAIN_2 succeeds, this needs to be investigated later

After removing several test vectors and running single-threaded:
$ ./fluster.py r -d GStreamer-VP9-V4L2-Gst1.0 -ts VP9-TEST-VECTORS -j 1
Ran 219/292 tests successfully               in 134.749 secs

Disabled tests:

            "name": "vp90-2-18-resize.ivf",
            "name": "vp90-2-21-resize_inter_1920x1080_5_1-2.webm",
            "name": "vp90-2-21-resize_inter_1920x1080_5_3-4.webm",
            "name": "vp90-2-21-resize_inter_1920x1080_7_1-2.webm",
            "name": "vp90-2-21-resize_inter_1920x1080_7_3-4.webm",
            "name": "vp90-2-21-resize_inter_320x180_5_1-2.webm",
            "name": "vp90-2-21-resize_inter_320x180_5_3-4.webm",
            "name": "vp90-2-21-resize_inter_320x180_7_1-2.webm",
            "name": "vp90-2-21-resize_inter_320x180_7_3-4.webm",
            "name": "vp90-2-21-resize_inter_640x360_5_1-2.webm",
            "name": "vp90-2-21-resize_inter_640x360_5_3-4.webm",
            "name": "vp90-2-21-resize_inter_640x360_7_1-2.webm",
            "name": "vp90-2-21-resize_inter_640x360_7_3-4.webm",

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (8):
      media: iris: turn platform caps into constants
      media: iris: turn platform data into constants
      media: iris: stop copying r/o data
      media: iris: stop encoding PIPE value into fw_caps
      media: iris: remove duplicateion between generic gen2 data and qcs8300
      media: iris: rename sm8250 platform file to gen1
      media: iris: move common register definitions to the header
      media: iris: enable support for SC7280 platform

 drivers/media/platform/qcom/iris/Makefile          |   2 +-
 drivers/media/platform/qcom/iris/iris_core.h       |   4 +-
 drivers/media/platform/qcom/iris/iris_ctrls.c      | 246 ++++-----
 drivers/media/platform/qcom/iris/iris_instance.h   |   3 +-
 .../platform/qcom/iris/iris_platform_common.h      |  25 +-
 ...iris_platform_sm8250.c => iris_platform_gen1.c} |  76 ++-
 .../media/platform/qcom/iris/iris_platform_gen2.c  |  44 +-
 .../platform/qcom/iris/iris_platform_qcs8300.h     | 550 ---------------------
 drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
 drivers/media/platform/qcom/iris/iris_vdec.c       |   5 +-
 drivers/media/platform/qcom/iris/iris_venc.c       |   5 +-
 drivers/media/platform/qcom/iris/iris_vpu2.c       | 130 +++++
 drivers/media/platform/qcom/iris/iris_vpu3x.c      |  35 --
 drivers/media/platform/qcom/iris/iris_vpu_common.c |  43 --
 drivers/media/platform/qcom/iris/iris_vpu_common.h |   1 +
 .../platform/qcom/iris/iris_vpu_register_defines.h |  56 +++
 16 files changed, 440 insertions(+), 789 deletions(-)
---
base-commit: 47a8d4b89844f5974f634b4189a39d5ccbacd81c
change-id: 20251006-iris-sc7280-fdb797f238d8

Best regards,
-- 
With best wishes
Dmitry

[PATCH 1/8] media: iris: turn platform caps into constants

[Dmitry Baryshkov]

Make all struct platform_inst_fw_cap instances constant, they are not
modified at runtime.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/iris_ctrls.c            | 2 +-
 drivers/media/platform/qcom/iris/iris_platform_common.h  | 4 ++--
 drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
 drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
 drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
index 754a5ad718bc37630bb861012301df7a2e7342a1..9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce 100644
--- a/drivers/media/platform/qcom/iris/iris_ctrls.c
+++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
@@ -301,7 +301,7 @@ int iris_ctrls_init(struct iris_inst *inst)
 
 void iris_session_init_caps(struct iris_core *core)
 {
-	struct platform_inst_fw_cap *caps;
+	const struct platform_inst_fw_cap *caps;
 	u32 i, num_cap, cap_id;
 
 	caps = core->iris_platform_data->inst_fw_caps_dec;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 58d05e0a112eed25faea027a34c719c89d6c3897..17ed86bf78bb3b0bc3f0862253fba6505ac3d164 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -215,9 +215,9 @@ struct iris_platform_data {
 	const char *fwname;
 	u32 pas_id;
 	struct platform_inst_caps *inst_caps;
-	struct platform_inst_fw_cap *inst_fw_caps_dec;
+	const struct platform_inst_fw_cap *inst_fw_caps_dec;
 	u32 inst_fw_caps_dec_size;
-	struct platform_inst_fw_cap *inst_fw_caps_enc;
+	const struct platform_inst_fw_cap *inst_fw_caps_enc;
 	u32 inst_fw_caps_enc_size;
 	struct tz_cp_config *tz_cp_config_data;
 	u32 core_arch;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 36d69cc73986b74534a2912524c8553970fd862e..cbf38e13f89e5c4c46e759fbb86777854d751552 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -19,7 +19,7 @@
 #define VIDEO_ARCH_LX 1
 #define BITRATE_MAX				245000000
 
-static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
 	{
 		.cap_id = PROFILE_H264,
 		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
@@ -203,7 +203,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
 	},
 };
 
-static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
 	{
 		.cap_id = PROFILE_H264,
 		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
index 35ea0efade73caa687d300779c5b1dc3b17a0128..87517361a1cf4b6fe53b8a1483188670df52c7e7 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
@@ -5,7 +5,7 @@
 
 #define BITRATE_MAX				245000000
 
-static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
 	{
 		.cap_id = PROFILE_H264,
 		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
@@ -189,7 +189,7 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
 	},
 };
 
-static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
 	{
 		.cap_id = PROFILE_H264,
 		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 16486284f8acccf6a95a27f6003e885226e28f4d..e29cba993fde922b579eb7e5a59ae34bb46f9f0f 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -17,7 +17,7 @@
 #define BITRATE_PEAK_DEFAULT	(BITRATE_DEFAULT * 2)
 #define BITRATE_STEP		100
 
-static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
 	{
 		.cap_id = PIPE,
 		.min = PIPE_1,
@@ -38,7 +38,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
 	},
 };
 
-static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
+static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
 	{
 		.cap_id = STAGE,
 		.min = STAGE_1,

-- 
2.47.3

[PATCH 2/8] media: iris: turn platform data into constants

[Dmitry Baryshkov]

Make all struct iris_platform_data instances constant, they are not
modified at runtime.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/iris_platform_common.h | 10 +++++-----
 drivers/media/platform/qcom/iris/iris_platform_gen2.c   |  8 ++++----
 drivers/media/platform/qcom/iris/iris_platform_sm8250.c |  2 +-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 17ed86bf78bb3b0bc3f0862253fba6505ac3d164..5ffc1874e8c6362b1c650e912c230e9c4e3bd160 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -41,11 +41,11 @@ enum pipe_type {
 	PIPE_4 = 4,
 };
 
-extern struct iris_platform_data qcs8300_data;
-extern struct iris_platform_data sm8250_data;
-extern struct iris_platform_data sm8550_data;
-extern struct iris_platform_data sm8650_data;
-extern struct iris_platform_data sm8750_data;
+extern const struct iris_platform_data qcs8300_data;
+extern const struct iris_platform_data sm8250_data;
+extern const struct iris_platform_data sm8550_data;
+extern const struct iris_platform_data sm8650_data;
+extern const struct iris_platform_data sm8750_data;
 
 enum platform_clk_type {
 	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index cbf38e13f89e5c4c46e759fbb86777854d751552..b444e816355624bca8248cce9da7adcd7caf6c5b 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -737,7 +737,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
 	BUF_SCRATCH_2,
 };
 
-struct iris_platform_data sm8550_data = {
+const struct iris_platform_data sm8550_data = {
 	.get_instance = iris_hfi_gen2_get_instance,
 	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
@@ -827,7 +827,7 @@ struct iris_platform_data sm8550_data = {
  * - controller_rst_tbl to sm8650_controller_reset_table
  * - fwname to "qcom/vpu/vpu33_p4.mbn"
  */
-struct iris_platform_data sm8650_data = {
+const struct iris_platform_data sm8650_data = {
 	.get_instance = iris_hfi_gen2_get_instance,
 	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
@@ -912,7 +912,7 @@ struct iris_platform_data sm8650_data = {
 	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 };
 
-struct iris_platform_data sm8750_data = {
+const struct iris_platform_data sm8750_data = {
 	.get_instance = iris_hfi_gen2_get_instance,
 	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
@@ -998,7 +998,7 @@ struct iris_platform_data sm8750_data = {
  * - inst_caps to platform_inst_cap_qcs8300
  * - inst_fw_caps to inst_fw_cap_qcs8300
  */
-struct iris_platform_data qcs8300_data = {
+const struct iris_platform_data qcs8300_data = {
 	.get_instance = iris_hfi_gen2_get_instance,
 	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
 	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index e29cba993fde922b579eb7e5a59ae34bb46f9f0f..66a5bdd24d8a0e98b0554a019438bf4caa1dc43c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -314,7 +314,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = {
 	BUF_SCRATCH_2,
 };
 
-struct iris_platform_data sm8250_data = {
+const struct iris_platform_data sm8250_data = {
 	.get_instance = iris_hfi_gen1_get_instance,
 	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
 	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,

-- 
2.47.3

[PATCH 3/8] media: iris: stop copying r/o data

[Dmitry Baryshkov]

Most of the platform_inst_caps data is read-only. In order to lower the
amount of memory consumed by the driver, store the value and the
corresponding indice in the read-write data and use the rest via the
pointer to r/o capability data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/iris_core.h       |   4 +-
 drivers/media/platform/qcom/iris/iris_ctrls.c      | 238 ++++++++++-----------
 drivers/media/platform/qcom/iris/iris_instance.h   |   3 +-
 .../platform/qcom/iris/iris_platform_common.h      |   8 +-
 drivers/media/platform/qcom/iris/iris_vdec.c       |   5 +-
 drivers/media/platform/qcom/iris/iris_venc.c       |   5 +-
 6 files changed, 135 insertions(+), 128 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
index fb194c967ad4f9b5e00cd74f0d41e0b827ef14db..b5037ae8c71921753c165a86a277a4a4b5083b30 100644
--- a/drivers/media/platform/qcom/iris/iris_core.h
+++ b/drivers/media/platform/qcom/iris/iris_core.h
@@ -115,8 +115,8 @@ struct iris_core {
 	struct delayed_work			sys_error_handler;
 	struct list_head			instances;
 	/* encoder and decoder have overlapping caps, so two different arrays are required */
-	struct platform_inst_fw_cap		inst_fw_caps_dec[INST_FW_CAP_MAX];
-	struct platform_inst_fw_cap		inst_fw_caps_enc[INST_FW_CAP_MAX];
+	struct platform_inst_fw_cap_value	inst_fw_caps_dec[INST_FW_CAP_MAX];
+	struct platform_inst_fw_cap_value	inst_fw_caps_enc[INST_FW_CAP_MAX];
 };
 
 int iris_core_init(struct iris_core *core);
diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
index 9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce..0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38 100644
--- a/drivers/media/platform/qcom/iris/iris_ctrls.c
+++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
@@ -194,26 +194,28 @@ static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl)
 {
 	struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler);
 	enum platform_inst_fw_cap_type cap_id;
-	struct platform_inst_fw_cap *cap;
+	unsigned int cap_idx;
 	struct vb2_queue *q;
 
-	cap = &inst->fw_caps[0];
 	cap_id = iris_get_cap_id(ctrl->id);
 	if (!iris_valid_cap_id(cap_id))
 		return -EINVAL;
 
+	cap_idx = inst->fw_caps[cap_id].idx;
+
 	q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
 	if (vb2_is_streaming(q) &&
-	    (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
+	    (!(inst->inst_fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
 		return -EINVAL;
 
-	cap[cap_id].flags |= CAP_FLAG_CLIENT_SET;
+	inst->fw_caps[cap_id].client_set = true;
 
 	inst->fw_caps[cap_id].value = ctrl->val;
 
 	if (vb2_is_streaming(q)) {
-		if (cap[cap_id].set)
-			cap[cap_id].set(inst, cap_id);
+
+		if (inst->inst_fw_caps[cap_idx].set)
+			inst->inst_fw_caps[cap_idx].set(inst, cap_id);
 	}
 
 	return 0;
@@ -225,13 +227,14 @@ static const struct v4l2_ctrl_ops iris_ctrl_ops = {
 
 int iris_ctrls_init(struct iris_inst *inst)
 {
-	struct platform_inst_fw_cap *cap = &inst->fw_caps[0];
 	u32 num_ctrls = 0, ctrl_idx = 0, idx = 0;
 	u32 v4l2_id;
 	int ret;
 
 	for (idx = 1; idx < INST_FW_CAP_MAX; idx++) {
-		if (iris_get_v4l2_id(cap[idx].cap_id))
+		unsigned int cap_idx = inst->fw_caps[idx].idx;
+
+		if (iris_get_v4l2_id(inst->inst_fw_caps[cap_idx].cap_id))
 			num_ctrls++;
 	}
 
@@ -245,9 +248,11 @@ int iris_ctrls_init(struct iris_inst *inst)
 		return ret;
 
 	for (idx = 1; idx < INST_FW_CAP_MAX; idx++) {
+		unsigned int cap_idx = inst->fw_caps[idx].idx;
+		const struct platform_inst_fw_cap *cap = &inst->inst_fw_caps[cap_idx];
 		struct v4l2_ctrl *ctrl;
 
-		v4l2_id = iris_get_v4l2_id(cap[idx].cap_id);
+		v4l2_id = iris_get_v4l2_id(cap->cap_id);
 		if (!v4l2_id)
 			continue;
 
@@ -256,21 +261,21 @@ int iris_ctrls_init(struct iris_inst *inst)
 			goto error;
 		}
 
-		if (cap[idx].flags & CAP_FLAG_MENU) {
+		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_MENU) {
 			ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler,
 						      &iris_ctrl_ops,
 						      v4l2_id,
-						      cap[idx].max,
-						      ~(cap[idx].step_or_mask),
-						      cap[idx].value);
+						      cap[cap_idx].max,
+						      ~(cap[cap_idx].step_or_mask),
+						      inst->fw_caps[idx].value);
 		} else {
 			ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler,
 						 &iris_ctrl_ops,
 						 v4l2_id,
-						 cap[idx].min,
-						 cap[idx].max,
-						 cap[idx].step_or_mask,
-						 cap[idx].value);
+						 cap[cap_idx].min,
+						 cap[cap_idx].max,
+						 cap[cap_idx].step_or_mask,
+						 inst->fw_caps[idx].value);
 		}
 		if (!ctrl) {
 			ret = -EINVAL;
@@ -312,14 +317,8 @@ void iris_session_init_caps(struct iris_core *core)
 		if (!iris_valid_cap_id(cap_id))
 			continue;
 
-		core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id;
-		core->inst_fw_caps_dec[cap_id].min = caps[i].min;
-		core->inst_fw_caps_dec[cap_id].max = caps[i].max;
-		core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask;
+		core->inst_fw_caps_dec[cap_id].idx = i;
 		core->inst_fw_caps_dec[cap_id].value = caps[i].value;
-		core->inst_fw_caps_dec[cap_id].flags = caps[i].flags;
-		core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id;
-		core->inst_fw_caps_dec[cap_id].set = caps[i].set;
 	}
 
 	caps = core->iris_platform_data->inst_fw_caps_enc;
@@ -330,29 +329,23 @@ void iris_session_init_caps(struct iris_core *core)
 		if (!iris_valid_cap_id(cap_id))
 			continue;
 
-		core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id;
-		core->inst_fw_caps_enc[cap_id].min = caps[i].min;
-		core->inst_fw_caps_enc[cap_id].max = caps[i].max;
-		core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask;
+		core->inst_fw_caps_enc[cap_id].idx = i;
 		core->inst_fw_caps_enc[cap_id].value = caps[i].value;
-		core->inst_fw_caps_enc[cap_id].flags = caps[i].flags;
-		core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id;
-		core->inst_fw_caps_enc[cap_id].set = caps[i].set;
 	}
 }
 
 static u32 iris_get_port_info(struct iris_inst *inst,
-			      enum platform_inst_fw_cap_type cap_id)
+			      unsigned int cap_idx)
 {
 	if (inst->domain == DECODER) {
-		if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
+		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT)
 			return HFI_PORT_BITSTREAM;
-		else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
+		else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT)
 			return HFI_PORT_RAW;
 	} else {
-		if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
+		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT)
 			return HFI_PORT_RAW;
-		else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
+		else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT)
 			return HFI_PORT_BITSTREAM;
 	}
 
@@ -362,12 +355,13 @@ static u32 iris_get_port_info(struct iris_inst *inst,
 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
 	u32 hfi_value = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32_ENUM,
 					     &hfi_value, sizeof(u32));
 }
@@ -375,12 +369,13 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
 	u32 hfi_value = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32,
 					     &hfi_value, sizeof(u32));
 }
@@ -389,7 +384,8 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	struct v4l2_format *inp_f = inst->fmt_src;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 height = inp_f->fmt.pix_mp.height;
 	u32 width = inp_f->fmt.pix_mp.width;
 	u32 work_mode = STAGE_2;
@@ -401,7 +397,7 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32,
 					     &work_mode, sizeof(u32));
 }
@@ -409,12 +405,13 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 work_route = inst->fw_caps[PIPE].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32,
 					     &work_route, sizeof(u32));
 }
@@ -422,19 +419,13 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
-	u32 hfi_id, hfi_value;
-
-	if (inst->codec == V4L2_PIX_FMT_H264) {
-		hfi_id = inst->fw_caps[PROFILE_H264].hfi_id;
-		hfi_value = inst->fw_caps[PROFILE_H264].value;
-	} else {
-		hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id;
-		hfi_value = inst->fw_caps[PROFILE_HEVC].value;
-	}
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
+	u32 hfi_value = inst->fw_caps[cap_id].value;
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32_ENUM,
 					     &hfi_value, sizeof(u32));
 }
@@ -442,19 +433,13 @@ int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
-	u32 hfi_id, hfi_value;
-
-	if (inst->codec == V4L2_PIX_FMT_H264) {
-		hfi_id = inst->fw_caps[LEVEL_H264].hfi_id;
-		hfi_value = inst->fw_caps[LEVEL_H264].value;
-	} else {
-		hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id;
-		hfi_value = inst->fw_caps[LEVEL_HEVC].value;
-	}
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
+	u32 hfi_value = inst->fw_caps[cap_id].value;
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32_ENUM,
 					     &hfi_value, sizeof(u32));
 }
@@ -462,20 +447,19 @@ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	struct hfi_profile_level pl;
 
-	if (inst->codec == V4L2_PIX_FMT_H264) {
-		pl.profile = inst->fw_caps[PROFILE_H264].value;
+	pl.profile = inst->fw_caps[cap_id].value;
+	if (inst->codec == V4L2_PIX_FMT_H264)
 		pl.level = inst->fw_caps[LEVEL_H264].value;
-	} else {
-		pl.profile = inst->fw_caps[PROFILE_HEVC].value;
+	else
 		pl.level = inst->fw_caps[LEVEL_HEVC].value;
-	}
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					     HFI_HOST_FLAGS_NONE,
-					     iris_get_port_info(inst, cap_id),
+					     iris_get_port_info(inst, cap_idx),
 					     HFI_PAYLOAD_U32_ENUM,
 					     &pl, sizeof(u32));
 }
@@ -484,7 +468,8 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 header_mode = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 hfi_val;
 
 	if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE)
@@ -494,7 +479,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32,
 				     &hfi_val, sizeof(u32));
 }
@@ -504,7 +489,8 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value;
 	u32 header_mode = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 hfi_val;
 
 	if (prepend_sps_pps)
@@ -516,7 +502,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32_ENUM,
 				     &hfi_val, sizeof(u32));
 }
@@ -526,7 +512,8 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value;
 	u32 bitrate = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 max_bitrate;
 
 	if (inst->codec == V4L2_PIX_FMT_HEVC)
@@ -541,7 +528,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32,
 				     &bitrate, sizeof(u32));
 }
@@ -552,12 +539,13 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type
 	u32 rc_mode = inst->fw_caps[BITRATE_MODE].value;
 	u32 peak_bitrate = inst->fw_caps[cap_id].value;
 	u32 bitrate = inst->fw_caps[BITRATE].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 
 	if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR)
 		return 0;
 
-	if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) {
+	if (inst->fw_caps[cap_id].client_set) {
 		if (peak_bitrate < bitrate)
 			peak_bitrate = bitrate;
 	} else {
@@ -568,7 +556,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32,
 				     &peak_bitrate, sizeof(u32));
 }
@@ -579,7 +567,8 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
 	u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
 	u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
 	u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 rc_mode = 0;
 
 	if (!frame_rc)
@@ -595,7 +584,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32_ENUM,
 				     &rc_mode, sizeof(u32));
 }
@@ -606,7 +595,8 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
 	u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
 	u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
 	u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 rc_mode = 0;
 
 	if (!frame_rc)
@@ -622,7 +612,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32_ENUM,
 				     &rc_mode, sizeof(u32));
 }
@@ -631,7 +621,8 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 entropy_mode = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 hfi_val;
 
 	if (inst->codec != V4L2_PIX_FMT_H264)
@@ -642,7 +633,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32,
 				     &hfi_val, sizeof(u32));
 }
@@ -651,7 +642,8 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 entropy_mode = inst->fw_caps[cap_id].value;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 profile;
 
 	if (inst->codec != V4L2_PIX_FMT_H264)
@@ -667,7 +659,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_U32,
 				     &entropy_mode, sizeof(u32));
 }
@@ -678,32 +670,33 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
 	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0;
 	u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0;
 	u32 min_qp_enable = 0, client_qp_enable = 0;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 hfi_val;
 
 	if (inst->codec == V4L2_PIX_FMT_H264) {
-		if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
+		if (inst->fw_caps[MIN_FRAME_QP_H264].client_set)
 			min_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[I_FRAME_MIN_QP_H264].client_set))
 			i_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[P_FRAME_MIN_QP_H264].client_set))
 			p_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[B_FRAME_MIN_QP_H264].client_set))
 			b_qp_enable = 1;
 	} else {
-		if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
+		if (inst->fw_caps[MIN_FRAME_QP_HEVC].client_set)
 			min_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[I_FRAME_MIN_QP_HEVC].client_set))
 			i_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[P_FRAME_MIN_QP_HEVC].client_set))
 			p_qp_enable = 1;
 		if (min_qp_enable ||
-		    (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[B_FRAME_MIN_QP_HEVC].client_set))
 			b_qp_enable = 1;
 	}
 
@@ -731,7 +724,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_32_PACKED,
 				     &hfi_val, sizeof(u32));
 }
@@ -742,32 +735,33 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
 	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0;
 	u32 max_qp_enable = 0, client_qp_enable;
 	u32 i_frame_qp, p_frame_qp, b_frame_qp;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	u32 hfi_val;
 
 	if (inst->codec == V4L2_PIX_FMT_H264) {
-		if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
+		if (inst->fw_caps[MAX_FRAME_QP_H264].client_set)
 			max_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[I_FRAME_MAX_QP_H264].client_set))
 			i_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[P_FRAME_MAX_QP_H264].client_set))
 			p_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[B_FRAME_MAX_QP_H264].client_set))
 			b_qp_enable = 1;
 	} else {
-		if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
+		if (inst->fw_caps[MAX_FRAME_QP_HEVC].client_set)
 			max_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[I_FRAME_MAX_QP_HEVC].client_set))
 			i_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[P_FRAME_MAX_QP_HEVC].client_set))
 			p_qp_enable = 1;
 		if (max_qp_enable ||
-		    (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
+		    (inst->fw_caps[B_FRAME_MAX_QP_HEVC].client_set))
 			b_qp_enable = 1;
 	}
 
@@ -796,7 +790,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_32_PACKED,
 				     &hfi_val, sizeof(u32));
 }
@@ -806,7 +800,8 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable;
 	u32 i_frame_qp, p_frame_qp, b_frame_qp;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 	struct vb2_queue *q;
 	u32 hfi_val;
 
@@ -822,18 +817,18 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 		b_qp_enable = 1;
 	} else {
 		if (inst->codec == V4L2_PIX_FMT_H264) {
-			if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[I_FRAME_QP_H264].client_set)
 				i_qp_enable = 1;
-			if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[P_FRAME_QP_H264].client_set)
 				p_qp_enable = 1;
-			if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[B_FRAME_QP_H264].client_set)
 				b_qp_enable = 1;
 		} else {
-			if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[I_FRAME_QP_HEVC].client_set)
 				i_qp_enable = 1;
-			if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[P_FRAME_QP_HEVC].client_set)
 				p_qp_enable = 1;
-			if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
+			if (inst->fw_caps[B_FRAME_QP_HEVC].client_set)
 				b_qp_enable = 1;
 		}
 	}
@@ -857,7 +852,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_32_PACKED,
 				     &hfi_val, sizeof(u32));
 }
@@ -866,7 +861,8 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
 	struct hfi_quantization_range_v2 range;
-	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
+	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
 
 	if (inst->codec == V4L2_PIX_FMT_HEVC) {
 		range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value;
@@ -878,7 +874,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 
 	return hfi_ops->session_set_property(inst, hfi_id,
 					 HFI_HOST_FLAGS_NONE,
-				     iris_get_port_info(inst, cap_id),
+				     iris_get_port_info(inst, cap_idx),
 				     HFI_PAYLOAD_32_PACKED,
 				     &range, sizeof(range));
 }
@@ -886,7 +882,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
 int iris_set_properties(struct iris_inst *inst, u32 plane)
 {
 	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
-	struct platform_inst_fw_cap *cap;
+	const struct platform_inst_fw_cap *cap;
 	int ret;
 	u32 i;
 
@@ -895,7 +891,9 @@ int iris_set_properties(struct iris_inst *inst, u32 plane)
 		return ret;
 
 	for (i = 1; i < INST_FW_CAP_MAX; i++) {
-		cap = &inst->fw_caps[i];
+		unsigned int cap_idx = inst->fw_caps[i].idx;
+
+		cap = &inst->inst_fw_caps[cap_idx];
 		if (!iris_valid_cap_id(cap->cap_id))
 			continue;
 
diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h
index 5982d7adefeab80905478b32cddba7bd4651a691..39d74bef4d188abb919c372b7529d1d0773bd96a 100644
--- a/drivers/media/platform/qcom/iris/iris_instance.h
+++ b/drivers/media/platform/qcom/iris/iris_instance.h
@@ -82,7 +82,8 @@ struct iris_inst {
 	struct completion		completion;
 	struct completion		flush_completion;
 	u32				flush_responses_pending;
-	struct platform_inst_fw_cap	fw_caps[INST_FW_CAP_MAX];
+	struct platform_inst_fw_cap_value fw_caps[INST_FW_CAP_MAX];
+	const struct platform_inst_fw_cap *inst_fw_caps;
 	struct iris_buffers		buffers[BUF_TYPE_MAX];
 	u32				fw_min_count;
 	enum iris_inst_state		state;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5ffc1874e8c6362b1c650e912c230e9c4e3bd160..104ff38219e30e6d52476d44b54338c55ef2ca7b 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -148,7 +148,7 @@ enum platform_inst_fw_cap_flags {
 	CAP_FLAG_MENU			= BIT(1),
 	CAP_FLAG_INPUT_PORT		= BIT(2),
 	CAP_FLAG_OUTPUT_PORT		= BIT(3),
-	CAP_FLAG_CLIENT_SET		= BIT(4),
+	// BIT(4)
 	CAP_FLAG_BITMASK		= BIT(5),
 	CAP_FLAG_VOLATILE		= BIT(6),
 };
@@ -165,6 +165,12 @@ struct platform_inst_fw_cap {
 		   enum platform_inst_fw_cap_type cap_id);
 };
 
+struct platform_inst_fw_cap_value {
+	unsigned int idx;
+	s64 value;
+	bool client_set;
+};
+
 struct bw_info {
 	u32 mbs_per_sec;
 	u32 bw_ddr;
diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c
index ae13c3e1b426bfd81a7b46dc6c3ff5eb5c4860cb..72559497e81c30373711e9b113582039f1fb5153 100644
--- a/drivers/media/platform/qcom/iris/iris_vdec.c
+++ b/drivers/media/platform/qcom/iris/iris_vdec.c
@@ -55,8 +55,9 @@ int iris_vdec_inst_init(struct iris_inst *inst)
 	inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
 	inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
 
-	memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0],
-	       INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap));
+	memcpy(inst->fw_caps, core->inst_fw_caps_dec,
+	       sizeof(inst->fw_caps));
+	inst->inst_fw_caps = core->iris_platform_data->inst_fw_caps_dec;
 
 	return iris_ctrls_init(inst);
 }
diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c
index 099bd5ed4ae0294725860305254c4cad1ec88d7e..3d1d481f8048305ef9a9bf0cb435ebca68563105 100644
--- a/drivers/media/platform/qcom/iris/iris_venc.c
+++ b/drivers/media/platform/qcom/iris/iris_venc.c
@@ -68,8 +68,9 @@ int iris_venc_inst_init(struct iris_inst *inst)
 	inst->operating_rate = DEFAULT_FPS;
 	inst->frame_rate = DEFAULT_FPS;
 
-	memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0],
-	       INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap));
+	memcpy(inst->fw_caps, core->inst_fw_caps_enc,
+	       sizeof(inst->fw_caps));
+	inst->inst_fw_caps = core->iris_platform_data->inst_fw_caps_enc;
 
 	return iris_ctrls_init(inst);
 }

-- 
2.47.3

[PATCH 4/8] media: iris: stop encoding PIPE value into fw_caps

[Dmitry Baryshkov]

The value of the PIPE property depends on the number of pipes available
on the platform and is frequently the only difference between several
fw_caps. In order to reduce duplciation, use num_vpp_pipe from the
iris_platform_data rather than hardcoding the value into the fw_cap.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/iris_ctrls.c            | 6 +++++-
 drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
 drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
 drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
index 0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38..8db3fa222bdb92a7ffff3dfe62d33f16c0550757 100644
--- a/drivers/media/platform/qcom/iris/iris_ctrls.c
+++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
@@ -318,7 +318,11 @@ void iris_session_init_caps(struct iris_core *core)
 			continue;
 
 		core->inst_fw_caps_dec[cap_id].idx = i;
-		core->inst_fw_caps_dec[cap_id].value = caps[i].value;
+		if (cap_id == PIPE)
+			core->inst_fw_caps_dec[cap_id].value =
+				core->iris_platform_data->num_vpp_pipe;
+		else
+			core->inst_fw_caps_dec[cap_id].value = caps[i].value;
 	}
 
 	caps = core->iris_platform_data->inst_fw_caps_enc;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index b444e816355624bca8248cce9da7adcd7caf6c5b..7ad03a800356ae9fb73bdbd6d09928d0b500cb3c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -161,9 +161,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
 	{
 		.cap_id = PIPE,
 		.min = PIPE_1,
-		.max = PIPE_4,
+		/* .max is set via platform data */
 		.step_or_mask = 1,
-		.value = PIPE_4,
+		/* .value is set via platform data */
 		.hfi_id = HFI_PROP_PIPE,
 		.set = iris_set_pipe,
 	},
diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
index 87517361a1cf4b6fe53b8a1483188670df52c7e7..612526a938eed0554fc0da99e12c26d22e04bb6e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
@@ -147,9 +147,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
 	{
 		.cap_id = PIPE,
 		.min = PIPE_1,
-		.max = PIPE_2,
+		/* .max is set via platform data */
 		.step_or_mask = 1,
-		.value = PIPE_2,
+		/* .value is set via platform data */
 		.hfi_id = HFI_PROP_PIPE,
 		.set = iris_set_pipe,
 	},
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
index 66a5bdd24d8a0e98b0554a019438bf4caa1dc43c..2b3b8bd00a6096acaae928318d9231847ec89855 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
@@ -21,9 +21,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
 	{
 		.cap_id = PIPE,
 		.min = PIPE_1,
-		.max = PIPE_4,
+		/* .max is set via platform data */
 		.step_or_mask = 1,
-		.value = PIPE_4,
+		/* .value is set via platform data */
 		.hfi_id = HFI_PROPERTY_PARAM_WORK_ROUTE,
 		.set = iris_set_pipe,
 	},

-- 
2.47.3

[PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300

[Dmitry Baryshkov]

Now as we have removed PIPE value from inst_fw_caps_dec there should be
no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
QCS8300-specific tables and use generic one instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 .../media/platform/qcom/iris/iris_platform_gen2.c  |  28 +-
 .../platform/qcom/iris/iris_platform_qcs8300.h     | 550 ---------------------
 2 files changed, 18 insertions(+), 560 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 7ad03a800356ae9fb73bdbd6d09928d0b500cb3c..5ddc579a73bbc75e3bfca5881d6eee4aa40f09c9 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -12,7 +12,6 @@
 #include "iris_vpu_buffer.h"
 #include "iris_vpu_common.h"
 
-#include "iris_platform_qcs8300.h"
 #include "iris_platform_sm8650.h"
 #include "iris_platform_sm8750.h"
 
@@ -993,11 +992,20 @@ const struct iris_platform_data sm8750_data = {
 	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 };
 
-/*
- * Shares most of SM8550 data except:
- * - inst_caps to platform_inst_cap_qcs8300
- * - inst_fw_caps to inst_fw_cap_qcs8300
- */
+static struct platform_inst_caps platform_inst_cap_qcs8300 = {
+	.min_frame_width = 96,
+	.max_frame_width = 4096,
+	.min_frame_height = 96,
+	.max_frame_height = 4096,
+	.max_mbpf = (4096 * 2176) / 256,
+	.mb_cycles_vpp = 200,
+	.mb_cycles_fw = 326389,
+	.mb_cycles_fw_vpp = 44156,
+	.num_comv = 0,
+	.max_frame_rate = MAXIMUM_FPS,
+	.max_operating_rate = MAXIMUM_FPS,
+};
+
 const struct iris_platform_data qcs8300_data = {
 	.get_instance = iris_hfi_gen2_get_instance,
 	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
@@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
 	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
 	.pas_id = IRIS_PAS_ID,
 	.inst_caps = &platform_inst_cap_qcs8300,
-	.inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
-	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
-	.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
-	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
+	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
+	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
+	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
+	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
 	.tz_cp_config_data = &tz_cp_config_sm8550,
 	.core_arch = VIDEO_ARCH_LX,
 	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
deleted file mode 100644
index 612526a938eed0554fc0da99e12c26d22e04bb6e..0000000000000000000000000000000000000000
--- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#define BITRATE_MAX				245000000
-
-static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
-	{
-		.cap_id = PROFILE_H264,
-		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
-		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
-		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
-		.hfi_id = HFI_PROP_PROFILE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = PROFILE_HEVC,
-		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
-		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-		.hfi_id = HFI_PROP_PROFILE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = PROFILE_VP9,
-		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
-		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
-		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
-		.hfi_id = HFI_PROP_PROFILE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = LEVEL_H264,
-		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
-		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
-		.value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
-		.hfi_id = HFI_PROP_LEVEL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = LEVEL_HEVC,
-		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
-		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
-		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
-		.hfi_id = HFI_PROP_LEVEL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = LEVEL_VP9,
-		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
-		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
-				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
-		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
-		.hfi_id = HFI_PROP_LEVEL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = TIER,
-		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
-		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
-		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
-		.hfi_id = HFI_PROP_TIER,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-		.set = iris_set_u32_enum,
-	},
-	{
-		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
-		.min = DEFAULT_MAX_HOST_BUF_COUNT,
-		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
-		.step_or_mask = 1,
-		.value = DEFAULT_MAX_HOST_BUF_COUNT,
-		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
-		.flags = CAP_FLAG_INPUT_PORT,
-		.set = iris_set_u32,
-	},
-	{
-		.cap_id = STAGE,
-		.min = STAGE_1,
-		.max = STAGE_2,
-		.step_or_mask = 1,
-		.value = STAGE_2,
-		.hfi_id = HFI_PROP_STAGE,
-		.set = iris_set_stage,
-	},
-	{
-		.cap_id = PIPE,
-		.min = PIPE_1,
-		/* .max is set via platform data */
-		.step_or_mask = 1,
-		/* .value is set via platform data */
-		.hfi_id = HFI_PROP_PIPE,
-		.set = iris_set_pipe,
-	},
-	{
-		.cap_id = POC,
-		.min = 0,
-		.max = 2,
-		.step_or_mask = 1,
-		.value = 1,
-		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
-	},
-	{
-		.cap_id = CODED_FRAMES,
-		.min = CODED_FRAMES_PROGRESSIVE,
-		.max = CODED_FRAMES_PROGRESSIVE,
-		.step_or_mask = 0,
-		.value = CODED_FRAMES_PROGRESSIVE,
-		.hfi_id = HFI_PROP_CODED_FRAMES,
-	},
-	{
-		.cap_id = BIT_DEPTH,
-		.min = BIT_DEPTH_8,
-		.max = BIT_DEPTH_8,
-		.step_or_mask = 1,
-		.value = BIT_DEPTH_8,
-		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
-	},
-	{
-		.cap_id = RAP_FRAME,
-		.min = 0,
-		.max = 1,
-		.step_or_mask = 1,
-		.value = 1,
-		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
-		.flags = CAP_FLAG_INPUT_PORT,
-		.set = iris_set_u32,
-	},
-};
-
-static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
-	{
-		.cap_id = PROFILE_H264,
-		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
-		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
-				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
-		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
-		.hfi_id = HFI_PROP_PROFILE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = PROFILE_HEVC,
-		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
-		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-		.hfi_id = HFI_PROP_PROFILE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = LEVEL_H264,
-		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
-		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
-				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
-		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
-		.hfi_id = HFI_PROP_LEVEL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = LEVEL_HEVC,
-		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
-		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
-				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
-		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
-		.hfi_id = HFI_PROP_LEVEL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = STAGE,
-		.min = STAGE_1,
-		.max = STAGE_2,
-		.step_or_mask = 1,
-		.value = STAGE_2,
-		.hfi_id = HFI_PROP_STAGE,
-	},
-	{
-		.cap_id = HEADER_MODE,
-		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
-		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
-				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
-		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
-		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = PREPEND_SPSPPS_TO_IDR,
-		.min = 0,
-		.max = 1,
-		.step_or_mask = 1,
-		.value = 0,
-	},
-	{
-		.cap_id = BITRATE,
-		.min = 1,
-		.max = BITRATE_MAX,
-		.step_or_mask = 1,
-		.value = BITRATE_DEFAULT,
-		.hfi_id = HFI_PROP_TOTAL_BITRATE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = BITRATE_PEAK,
-		.min = 1,
-		.max = BITRATE_MAX,
-		.step_or_mask = 1,
-		.value = BITRATE_DEFAULT,
-		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = BITRATE_MODE,
-		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
-		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
-				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
-		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
-		.hfi_id = HFI_PROP_RATE_CONTROL,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = FRAME_SKIP_MODE,
-		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
-		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
-				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
-				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
-		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = FRAME_RC_ENABLE,
-		.min = 0,
-		.max = 1,
-		.step_or_mask = 1,
-		.value = 1,
-	},
-	{
-		.cap_id = GOP_SIZE,
-		.min = 0,
-		.max = INT_MAX,
-		.step_or_mask = 1,
-		.value = 2 * DEFAULT_FPS - 1,
-		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = ENTROPY_MODE,
-		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
-		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
-		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
-				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
-		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
-		.hfi_id = HFI_PROP_CABAC_SESSION,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
-	},
-	{
-		.cap_id = MIN_FRAME_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-		.hfi_id = HFI_PROP_MIN_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT,
-	},
-	{
-		.cap_id = MIN_FRAME_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-		.hfi_id = HFI_PROP_MIN_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT,
-	},
-	{
-		.cap_id = MAX_FRAME_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-		.hfi_id = HFI_PROP_MAX_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT,
-	},
-	{
-		.cap_id = MAX_FRAME_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-		.hfi_id = HFI_PROP_MAX_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT,
-	},
-	{
-		.cap_id = I_FRAME_MIN_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = I_FRAME_MIN_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = P_FRAME_MIN_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = P_FRAME_MIN_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = B_FRAME_MIN_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = B_FRAME_MIN_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MIN_QP_8BIT,
-	},
-	{
-		.cap_id = I_FRAME_MAX_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = I_FRAME_MAX_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = P_FRAME_MAX_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = P_FRAME_MAX_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = B_FRAME_MAX_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = B_FRAME_MAX_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = MAX_QP,
-	},
-	{
-		.cap_id = I_FRAME_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = I_FRAME_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = P_FRAME_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = P_FRAME_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = B_FRAME_QP_H264,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-	{
-		.cap_id = B_FRAME_QP_HEVC,
-		.min = MIN_QP_8BIT,
-		.max = MAX_QP,
-		.step_or_mask = 1,
-		.value = DEFAULT_QP,
-		.hfi_id = HFI_PROP_QP_PACKED,
-		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
-			CAP_FLAG_DYNAMIC_ALLOWED,
-	},
-};
-
-static struct platform_inst_caps platform_inst_cap_qcs8300 = {
-	.min_frame_width = 96,
-	.max_frame_width = 4096,
-	.min_frame_height = 96,
-	.max_frame_height = 4096,
-	.max_mbpf = (4096 * 2176) / 256,
-	.mb_cycles_vpp = 200,
-	.mb_cycles_fw = 326389,
-	.mb_cycles_fw_vpp = 44156,
-	.num_comv = 0,
-	.max_frame_rate = MAXIMUM_FPS,
-	.max_operating_rate = MAXIMUM_FPS,
-};

-- 
2.47.3

[PATCH 6/8] media: iris: rename sm8250 platform file to gen1

[Dmitry Baryshkov]

In preparation to adding more Gen1 platforms, which will share a
significant amount of data, rename the SM8250 platform file to
iris_platform_gen1.c.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/Makefile                               | 2 +-
 .../platform/qcom/iris/{iris_platform_sm8250.c => iris_platform_gen1.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 13270cd6d899852dded675b33d37f5919b81ccba..fad3be044e5fe783db697a592b4f09de4d42d0d2 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -26,7 +26,7 @@ qcom-iris-objs += iris_buffer.o \
              iris_vpu_common.o \
 
 ifeq ($(CONFIG_VIDEO_QCOM_VENUS),)
-qcom-iris-objs += iris_platform_sm8250.o
+qcom-iris-objs += iris_platform_gen1.o
 endif
 
 obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
similarity index 100%
rename from drivers/media/platform/qcom/iris/iris_platform_sm8250.c
rename to drivers/media/platform/qcom/iris/iris_platform_gen1.c

-- 
2.47.3

[PATCH 7/8] media: iris: move common register definitions to the header

[Dmitry Baryshkov]

Simplify adding new platforms by moving common registers definitions
from VPU 3.x and "common" file to the header with other register
defines.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/media/platform/qcom/iris/iris_vpu3x.c      | 35 --------------
 drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 -----------------
 .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++++++
 3 files changed, 56 insertions(+), 78 deletions(-)

diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34a53c63c595f72 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -11,48 +11,13 @@
 #include "iris_vpu_common.h"
 #include "iris_vpu_register_defines.h"
 
-#define WRAPPER_TZ_BASE_OFFS			0x000C0000
-#define AON_BASE_OFFS				0x000E0000
 #define AON_MVP_NOC_RESET			0x0001F000
 
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
-#define REQ_POWER_DOWN_PREP			BIT(0)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
-#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
-#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
-#define NOC_LPI_STATUS_ACTIVE		BIT(2) /* Indicates the NOC is active */
-#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
-#define CORE_CLK_RUN				0x0
-/* VPU v3.5 */
-#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
-
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT			BIT(0)
-#define CTL_CLK_HALT				BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH				BIT(0)
-
-#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
-#define CORE_BRIDGE_SW_RESET			BIT(0)
-#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
-
-#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
-#define MSK_CORE_POWER_ON			BIT(1)
-
 #define AON_WRAPPER_MVP_NOC_RESET_REQ		(AON_MVP_NOC_RESET + 0x000)
 #define VIDEO_NOC_RESET_REQ			(BIT(0) | BIT(1))
 
 #define AON_WRAPPER_MVP_NOC_RESET_ACK		(AON_MVP_NOC_RESET + 0x004)
 
-#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
-
 #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET	(AON_BASE_OFFS + 0x18)
 #define SW_RESET				BIT(0)
 #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL	(AON_BASE_OFFS + 0x20)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8088130fb625fd 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -11,13 +11,6 @@
 #include "iris_vpu_common.h"
 #include "iris_vpu_register_defines.h"
 
-#define WRAPPER_TZ_BASE_OFFS			0x000C0000
-#define AON_BASE_OFFS				0x000E0000
-
-#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
-
-#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
-#define CLEAR_XTENSA2HOST_INTR			BIT(0)
 
 #define CTRL_INIT				(CPU_CS_BASE_OFFS + 0x48)
 #define CTRL_STATUS				(CPU_CS_BASE_OFFS + 0x4C)
@@ -35,42 +28,6 @@
 #define UC_REGION_ADDR				(CPU_CS_BASE_OFFS + 0x64)
 #define UC_REGION_SIZE				(CPU_CS_BASE_OFFS + 0x68)
 
-#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
-#define HOST2XTENSA_INTR_ENABLE			BIT(0)
-
-#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
-#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
-#define MSK_CORE_POWER_ON			BIT(1)
-
-#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
-#define CPU_IC_SOFTINT_H2A_SHFT			0x0
-
-#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
-#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
-#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
-
-#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
-#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
-#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
-
-#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
-#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
-#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
-#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
-
-#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
-#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
-#define CTL_AXI_CLK_HALT			BIT(0)
-#define CTL_CLK_HALT				BIT(1)
-
-#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
-#define RESET_HIGH				BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
-#define REQ_POWER_DOWN_PREP			BIT(0)
-
-#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
-
 static void iris_vpu_interrupt_init(struct iris_core *core)
 {
 	u32 mask_val;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe8ad445a0a13f4 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -9,9 +9,65 @@
 #define VCODEC_BASE_OFFS			0x00000000
 #define CPU_BASE_OFFS				0x000A0000
 #define WRAPPER_BASE_OFFS			0x000B0000
+#define WRAPPER_TZ_BASE_OFFS			0x000C0000
+#define AON_BASE_OFFS				0x000E0000
+
+#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
 
 #define CPU_CS_BASE_OFFS			(CPU_BASE_OFFS)
 
+#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
+#define CLEAR_XTENSA2HOST_INTR			BIT(0)
+
+#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
+#define HOST2XTENSA_INTR_ENABLE			BIT(0)
+
+#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
+#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
+#define CPU_IC_SOFTINT_H2A_SHFT			0x0
+
+#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
+#define CORE_BRIDGE_SW_RESET			BIT(0)
+#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
+
+#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
+#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
+#define MSK_CORE_POWER_ON			BIT(1)
+
+#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
+#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
+
+#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
+#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
+#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
+
 #define WRAPPER_CORE_POWER_STATUS		(WRAPPER_BASE_OFFS + 0x80)
+#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
+#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
+#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
+#define REQ_POWER_DOWN_PREP			BIT(0)
+
+#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
+#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
+#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
+#define NOC_LPI_STATUS_ACTIVE			BIT(2) /* Indicates the NOC is active */
+
+#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
+
+#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
+#define CORE_CLK_RUN				0x0
+
+#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
+
+#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
+#define CTL_AXI_CLK_HALT			BIT(0)
+#define CTL_CLK_HALT				BIT(1)
+
+#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
+#define RESET_HIGH				BIT(0)
+
+#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
+#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
 
 #endif

-- 
2.47.3

[PATCH 8/8] media: iris: enable support for SC7280 platform

[Dmitry Baryshkov]

As a part of migrating code from the old Venus driver to the new Iris
one, add support for the SC7280 platform. It is very similar to SM8250,
but it (currently) uses no reset controls (there is an optional
GCC-generated reset, it will be added later) and no AON registers
region. The Venus driver names this platform "IRIS2_1", so the ops in
the driver are also now called iris_vpu21_ops.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 .../platform/qcom/iris/iris_platform_common.h      |   3 +
 .../media/platform/qcom/iris/iris_platform_gen1.c  |  66 +++++++++++
 drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
 drivers/media/platform/qcom/iris/iris_vpu2.c       | 130 +++++++++++++++++++++
 drivers/media/platform/qcom/iris/iris_vpu_common.h |   1 +
 5 files changed, 204 insertions(+)

diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 104ff38219e30e6d52476d44b54338c55ef2ca7b..36e33eb05a6918de590feca37b41c07a92e9c434 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -42,6 +42,7 @@ enum pipe_type {
 };
 
 extern const struct iris_platform_data qcs8300_data;
+extern const struct iris_platform_data sc7280_data;
 extern const struct iris_platform_data sm8250_data;
 extern const struct iris_platform_data sm8550_data;
 extern const struct iris_platform_data sm8650_data;
@@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data;
 enum platform_clk_type {
 	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
 	IRIS_CTRL_CLK,
+	IRIS_AHB_CLK,
 	IRIS_HW_CLK,
+	IRIS_HW_AXI_CLK,
 	IRIS_AXI1_CLK,
 	IRIS_CTRL_FREERUN_CLK,
 	IRIS_HW_FREERUN_CLK,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
index 2b3b8bd00a6096acaae928318d9231847ec89855..d5288a71a6a8289e5ecf69b6f38231500f2bf8b4 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
@@ -364,3 +364,69 @@ const struct iris_platform_data sm8250_data = {
 	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
 	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
 };
+
+static const struct bw_info sc7280_bw_table_dec[] = {
+	{ ((3840 * 2160) / 256) * 60, 1896000, },
+	{ ((3840 * 2160) / 256) * 30,  968000, },
+	{ ((1920 * 1080) / 256) * 60,  618000, },
+	{ ((1920 * 1080) / 256) * 30,  318000, },
+};
+
+static const char * const sc7280_opp_pd_table[] = { "cx" };
+
+static const struct platform_clk_data sc7280_clk_table[] = {
+	{IRIS_CTRL_CLK,    "core"         },
+	{IRIS_AXI_CLK,     "bus"          },
+	{IRIS_AHB_CLK,     "iface"        },
+	{IRIS_HW_CLK,      "vcodec_core"  },
+	{IRIS_HW_AXI_CLK,  "vcodec_bus"   },
+};
+
+const struct iris_platform_data sc7280_data = {
+	.get_instance = iris_hfi_gen1_get_instance,
+	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
+	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
+	.get_vpu_buffer_size = iris_vpu_buf_size,
+	.vpu_ops = &iris_vpu21_ops,
+	.set_preset_registers = iris_set_sm8250_preset_registers,
+	.icc_tbl = sm8250_icc_table,
+	.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
+	.bw_tbl_dec = sc7280_bw_table_dec,
+	.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
+	.pmdomain_tbl = sm8250_pmdomain_table,
+	.pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
+	.opp_pd_tbl = sc7280_opp_pd_table,
+	.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
+	.clk_tbl = sc7280_clk_table,
+	.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
+	/* Upper bound of DMA address range */
+	.dma_mask = 0xe0000000 - 1,
+	.fwname = "qcom/vpu/vpu20_p1.mbn",
+	.pas_id = IRIS_PAS_ID,
+	.inst_caps = &platform_inst_cap_sm8250,
+	.inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
+	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
+	.inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
+	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
+	.tz_cp_config_data = &tz_cp_config_sm8250,
+	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+	.num_vpp_pipe = 4,
+	.max_session_count = 16,
+	.max_core_mbpf = NUM_MBS_8K,
+	.max_core_mbps = ((7680 * 4320) / 256) * 60,
+	.dec_input_config_params_default =
+		sm8250_vdec_input_config_param_default,
+	.dec_input_config_params_default_size =
+		ARRAY_SIZE(sm8250_vdec_input_config_param_default),
+	.enc_input_config_params = sm8250_venc_input_config_param,
+	.enc_input_config_params_size =
+		ARRAY_SIZE(sm8250_venc_input_config_param),
+
+	.dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
+	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
+	.dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
+	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
+
+	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
+	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 00e99be16e087c4098f930151fd76cd381d721ce..9bc9b34c2576581635fa8d87eed1965657eb3eb3 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -357,6 +357,10 @@ static const struct of_device_id iris_dt_match[] = {
 		.data = &qcs8300_data,
 	},
 #if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS))
+	{
+		.compatible = "qcom,sc7280-venus",
+		.data = &sc7280_data,
+	},
 	{
 		.compatible = "qcom,sm8250-venus",
 		.data = &sm8250_data,
diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c
index de7d142316d2dc9ab0c4ad9cc8161c87ac949b4c..73fae652cfea6b729d4b8f9346a345a88b068394 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu2.c
@@ -3,9 +3,15 @@
  * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <linux/bits.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+
 #include "iris_instance.h"
 #include "iris_vpu_common.h"
 
+#include "iris_vpu_register_defines.h"
+
 static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size)
 {
 	struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
@@ -32,6 +38,122 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size)
 	return max(vpp_freq, vsp_freq);
 }
 
+/* iris_vpu_power_off_hw + IRIS_HW_AXI_CLK */
+static void iris_vpu21_power_off_hw(struct iris_core *core)
+{
+	dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
+	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+	iris_disable_unprepare_clock(core, IRIS_HW_AXI_CLK);
+	iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+}
+
+/* iris_vpu_power_on_hw + IRIS_HW_AXI_CLK */
+static int iris_vpu21_power_on_hw(struct iris_core *core)
+{
+	int ret;
+
+	ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+	if (ret)
+		return ret;
+
+	ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+	if (ret)
+		goto err_disable_power;
+
+	ret = iris_prepare_enable_clock(core, IRIS_HW_AXI_CLK);
+	if (ret)
+		goto err_disable_hw_clock;
+
+	ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
+	if (ret)
+		goto err_disable_hw_axi_clock;
+
+	return 0;
+
+err_disable_hw_axi_clock:
+	iris_disable_unprepare_clock(core, IRIS_HW_AXI_CLK);
+err_disable_hw_clock:
+	iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+err_disable_power:
+	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+
+	return ret;
+}
+
+/* iris_vpu_power_on_controller + IRIS_AHB_CLK */
+static int iris_vpu21_power_on_controller(struct iris_core *core)
+{
+	int ret;
+
+	ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+	if (ret)
+		return ret;
+
+	ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+	if (ret)
+		goto err_disable_power;
+
+	ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
+	if (ret)
+		goto err_disable_axi_clock;
+
+	ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK);
+	if (ret)
+		goto err_disable_ctrl_clock;
+
+	return 0;
+
+err_disable_ctrl_clock:
+	iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+err_disable_axi_clock:
+	iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+err_disable_power:
+	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+	return ret;
+}
+
+/*
+ * This is the same as iris_vpu_power_off_controller except
+ * AON_WRAPPER_MVP_NOC_LPI_CONTROL / AON_WRAPPER_MVP_NOC_LPI_STATUS programming
+ * and with added IRIS_AHB_CLK handling
+ */
+static int iris_vpu21_power_off_controller(struct iris_core *core)
+{
+	u32 val = 0;
+	int ret;
+
+	writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
+
+	writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
+
+	ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
+				 val, val & BIT(0), 200, 2000);
+	if (ret)
+		goto disable_power;
+
+	writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
+
+	ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
+				 val, val == 0, 200, 2000);
+	if (ret)
+		goto disable_power;
+
+	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
+	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
+	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
+	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
+	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
+
+disable_power:
+	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
+	iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+	iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+	return 0;
+}
+
 const struct vpu_ops iris_vpu2_ops = {
 	.power_off_hw = iris_vpu_power_off_hw,
 	.power_on_hw = iris_vpu_power_on_hw,
@@ -39,3 +161,11 @@ const struct vpu_ops iris_vpu2_ops = {
 	.power_on_controller = iris_vpu_power_on_controller,
 	.calc_freq = iris_vpu2_calc_freq,
 };
+
+const struct vpu_ops iris_vpu21_ops = {
+	.power_off_hw = iris_vpu21_power_off_hw,
+	.power_on_hw = iris_vpu21_power_on_hw,
+	.power_off_controller = iris_vpu21_power_off_controller,
+	.power_on_controller = iris_vpu21_power_on_controller,
+	.calc_freq = iris_vpu2_calc_freq,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index d636e287457adf0c44540af5c85cfa69decbca8b..6589fecbfeeec75d21759048afeca7fb42e65492 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -9,6 +9,7 @@
 struct iris_core;
 
 extern const struct vpu_ops iris_vpu2_ops;
+extern const struct vpu_ops iris_vpu21_ops;
 extern const struct vpu_ops iris_vpu3_ops;
 extern const struct vpu_ops iris_vpu33_ops;
 extern const struct vpu_ops iris_vpu35_ops;

-- 
2.47.3

Re: [PATCH 4/8] media: iris: stop encoding PIPE value into fw_caps

[Konrad Dybcio]

On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> The value of the PIPE property depends on the number of pipes available
> on the platform and is frequently the only difference between several
> fw_caps. In order to reduce duplciation, use num_vpp_pipe from the
> iris_platform_data rather than hardcoding the value into the fw_cap.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/media/platform/qcom/iris/iris_ctrls.c            | 6 +++++-
>  drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
>  drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
>  drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
>  4 files changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> index 0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38..8db3fa222bdb92a7ffff3dfe62d33f16c0550757 100644
> --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> @@ -318,7 +318,11 @@ void iris_session_init_caps(struct iris_core *core)
>  			continue;
>  
>  		core->inst_fw_caps_dec[cap_id].idx = i;
> -		core->inst_fw_caps_dec[cap_id].value = caps[i].value;
> +		if (cap_id == PIPE)
> +			core->inst_fw_caps_dec[cap_id].value =
> +				core->iris_platform_data->num_vpp_pipe;
> +		else
> +			core->inst_fw_caps_dec[cap_id].value = caps[i].value;

I really hope this if-else won't grow in the future

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300

[Konrad Dybcio]

On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> Now as we have removed PIPE value from inst_fw_caps_dec there should be
> no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
> QCS8300-specific tables and use generic one instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

[...]

> +static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> +	.min_frame_width = 96,
> +	.max_frame_width = 4096,
> +	.min_frame_height = 96,
> +	.max_frame_height = 4096,
> +	.max_mbpf = (4096 * 2176) / 256,
> +	.mb_cycles_vpp = 200,
> +	.mb_cycles_fw = 326389,
> +	.mb_cycles_fw_vpp = 44156,
> +	.num_comv = 0,
> +	.max_frame_rate = MAXIMUM_FPS,
> +	.max_operating_rate = MAXIMUM_FPS,
> +};
> +
>  const struct iris_platform_data qcs8300_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
>  	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
>  	.pas_id = IRIS_PAS_ID,
>  	.inst_caps = &platform_inst_cap_qcs8300,
> -	.inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
> -	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> -	.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> -	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> +	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> +	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> +	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> +	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),

8550 enc data has a .set() under a number of caps (was qcs8300 tested?)
and also additionally defines:

 * INPUT_BUF_HOST_MAX_COUNT
 * OUTPUT_BUF_HOST_MAX_COUNT

values of which should probably be cross-checked (they say "DEFAULT"
so it's probably OK, but just so you know)

dec is 1 : 1

Konrad

Re: [PATCH 6/8] media: iris: rename sm8250 platform file to gen1

[Konrad Dybcio]

On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> In preparation to adding more Gen1 platforms, which will share a
> significant amount of data, rename the SM8250 platform file to
> iris_platform_gen1.c.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Konrad Dybcio]

On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> As a part of migrating code from the old Venus driver to the new Iris
> one, add support for the SC7280 platform. It is very similar to SM8250,
> but it (currently) uses no reset controls (there is an optional
> GCC-generated reset, it will be added later) and no AON registers
> region. The Venus driver names this platform "IRIS2_1", so the ops in

Which we've learnt in the past is "IRIS2, 1-pipe"

> the driver are also now called iris_vpu21_ops.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  .../platform/qcom/iris/iris_platform_common.h      |   3 +
>  .../media/platform/qcom/iris/iris_platform_gen1.c  |  66 +++++++++++
>  drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
>  drivers/media/platform/qcom/iris/iris_vpu2.c       | 130 +++++++++++++++++++++
>  drivers/media/platform/qcom/iris/iris_vpu_common.h |   1 +
>  5 files changed, 204 insertions(+)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 104ff38219e30e6d52476d44b54338c55ef2ca7b..36e33eb05a6918de590feca37b41c07a92e9c434 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -42,6 +42,7 @@ enum pipe_type {
>  };
>  
>  extern const struct iris_platform_data qcs8300_data;
> +extern const struct iris_platform_data sc7280_data;
>  extern const struct iris_platform_data sm8250_data;
>  extern const struct iris_platform_data sm8550_data;
>  extern const struct iris_platform_data sm8650_data;
> @@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data;
>  enum platform_clk_type {
>  	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
>  	IRIS_CTRL_CLK,
> +	IRIS_AHB_CLK,

Interestingly, 8250 also has an AHB clock, but the clock driver keeps it
always-on..

>  	IRIS_HW_CLK,
> +	IRIS_HW_AXI_CLK,

This exists on SC7280 and SM6350, perhaps as a result of the bus topology

>  	IRIS_AXI1_CLK,
>  	IRIS_CTRL_FREERUN_CLK,
>  	IRIS_HW_FREERUN_CLK,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> index 2b3b8bd00a6096acaae928318d9231847ec89855..d5288a71a6a8289e5ecf69b6f38231500f2bf8b4 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> @@ -364,3 +364,69 @@ const struct iris_platform_data sm8250_data = {
>  	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
>  	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
>  };
> +
> +static const struct bw_info sc7280_bw_table_dec[] = {
> +	{ ((3840 * 2160) / 256) * 60, 1896000, },
> +	{ ((3840 * 2160) / 256) * 30,  968000, },
> +	{ ((1920 * 1080) / 256) * 60,  618000, },
> +	{ ((1920 * 1080) / 256) * 30,  318000, },
> +};
> +
> +static const char * const sc7280_opp_pd_table[] = { "cx" };

Wonder why this is different..

Oh, I can bet good money SM8250's Venus isn't fed off of MX alone..

Let's check the sauce..

It was always supposed to be M*MC*X with MX just for the VIDEO_CC
PLLs..

[...]

> +/*
> + * This is the same as iris_vpu_power_off_controller except
> + * AON_WRAPPER_MVP_NOC_LPI_CONTROL / AON_WRAPPER_MVP_NOC_LPI_STATUS programming
> + * and with added IRIS_AHB_CLK handling
> + */
> +static int iris_vpu21_power_off_controller(struct iris_core *core)

This is 1 : 1 the existing sm8250 code except...> +{
> +	u32 val = 0;
> +	int ret;
> +
> +	writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
> +
> +	writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> +
> +	ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
> +				 val, val & BIT(0), 200, 2000);
> +	if (ret)
> +		goto disable_power;
> +
> +	writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
> +
> +	ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
> +				 val, val == 0, 200, 2000);
> +	if (ret)
> +		goto disable_power;
> +
> +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
> +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> +
> +disable_power:
> +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);

..for this line

but this could be added to that one instead, since both clk APIs and the
Iris wrappers around it are happy to consume a null pointer (funnily
enough this one returns !void and is never checked)

similar story for other func additions

Konrad

Re: [PATCH 1/8] media: iris: turn platform caps into constants

[Bryan O'Donoghue]

On 08/10/2025 05:32, Dmitry Baryshkov wrote:
> Make all struct platform_inst_fw_cap instances constant, they are not
> modified at runtime.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>   drivers/media/platform/qcom/iris/iris_ctrls.c            | 2 +-
>   drivers/media/platform/qcom/iris/iris_platform_common.h  | 4 ++--
>   drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
>   drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
>   drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
>   5 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> index 754a5ad718bc37630bb861012301df7a2e7342a1..9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce 100644
> --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> @@ -301,7 +301,7 @@ int iris_ctrls_init(struct iris_inst *inst)
> 
>   void iris_session_init_caps(struct iris_core *core)
>   {
> -	struct platform_inst_fw_cap *caps;
> +	const struct platform_inst_fw_cap *caps;
>   	u32 i, num_cap, cap_id;
> 
>   	caps = core->iris_platform_data->inst_fw_caps_dec;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 58d05e0a112eed25faea027a34c719c89d6c3897..17ed86bf78bb3b0bc3f0862253fba6505ac3d164 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -215,9 +215,9 @@ struct iris_platform_data {
>   	const char *fwname;
>   	u32 pas_id;
>   	struct platform_inst_caps *inst_caps;
> -	struct platform_inst_fw_cap *inst_fw_caps_dec;
> +	const struct platform_inst_fw_cap *inst_fw_caps_dec;
>   	u32 inst_fw_caps_dec_size;
> -	struct platform_inst_fw_cap *inst_fw_caps_enc;
> +	const struct platform_inst_fw_cap *inst_fw_caps_enc;
>   	u32 inst_fw_caps_enc_size;
>   	struct tz_cp_config *tz_cp_config_data;
>   	u32 core_arch;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 36d69cc73986b74534a2912524c8553970fd862e..cbf38e13f89e5c4c46e759fbb86777854d751552 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -19,7 +19,7 @@
>   #define VIDEO_ARCH_LX 1
>   #define BITRATE_MAX				245000000
> 
> -static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
>   	{
>   		.cap_id = PROFILE_H264,
>   		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> @@ -203,7 +203,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
>   	},
>   };
> 
> -static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
>   	{
>   		.cap_id = PROFILE_H264,
>   		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> index 35ea0efade73caa687d300779c5b1dc3b17a0128..87517361a1cf4b6fe53b8a1483188670df52c7e7 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> @@ -5,7 +5,7 @@
> 
>   #define BITRATE_MAX				245000000
> 
> -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
>   	{
>   		.cap_id = PROFILE_H264,
>   		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> @@ -189,7 +189,7 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
>   	},
>   };
> 
> -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
>   	{
>   		.cap_id = PROFILE_H264,
>   		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 16486284f8acccf6a95a27f6003e885226e28f4d..e29cba993fde922b579eb7e5a59ae34bb46f9f0f 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -17,7 +17,7 @@
>   #define BITRATE_PEAK_DEFAULT	(BITRATE_DEFAULT * 2)
>   #define BITRATE_STEP		100
> 
> -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
>   	{
>   		.cap_id = PIPE,
>   		.min = PIPE_1,
> @@ -38,7 +38,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
>   	},
>   };
> 
> -static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
>   	{
>   		.cap_id = STAGE,
>   		.min = STAGE_1,
> 
> --
> 2.47.3
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 2/8] media: iris: turn platform data into constants

[Bryan O'Donoghue]

On 08/10/2025 05:33, Dmitry Baryshkov wrote:
> Make all struct iris_platform_data instances constant, they are not
> modified at runtime.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>   drivers/media/platform/qcom/iris/iris_platform_common.h | 10 +++++-----
>   drivers/media/platform/qcom/iris/iris_platform_gen2.c   |  8 ++++----
>   drivers/media/platform/qcom/iris/iris_platform_sm8250.c |  2 +-
>   3 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 17ed86bf78bb3b0bc3f0862253fba6505ac3d164..5ffc1874e8c6362b1c650e912c230e9c4e3bd160 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -41,11 +41,11 @@ enum pipe_type {
>   	PIPE_4 = 4,
>   };
> 
> -extern struct iris_platform_data qcs8300_data;
> -extern struct iris_platform_data sm8250_data;
> -extern struct iris_platform_data sm8550_data;
> -extern struct iris_platform_data sm8650_data;
> -extern struct iris_platform_data sm8750_data;
> +extern const struct iris_platform_data qcs8300_data;
> +extern const struct iris_platform_data sm8250_data;
> +extern const struct iris_platform_data sm8550_data;
> +extern const struct iris_platform_data sm8650_data;
> +extern const struct iris_platform_data sm8750_data;
> 
>   enum platform_clk_type {
>   	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index cbf38e13f89e5c4c46e759fbb86777854d751552..b444e816355624bca8248cce9da7adcd7caf6c5b 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -737,7 +737,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
>   	BUF_SCRATCH_2,
>   };
> 
> -struct iris_platform_data sm8550_data = {
> +const struct iris_platform_data sm8550_data = {
>   	.get_instance = iris_hfi_gen2_get_instance,
>   	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>   	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -827,7 +827,7 @@ struct iris_platform_data sm8550_data = {
>    * - controller_rst_tbl to sm8650_controller_reset_table
>    * - fwname to "qcom/vpu/vpu33_p4.mbn"
>    */
> -struct iris_platform_data sm8650_data = {
> +const struct iris_platform_data sm8650_data = {
>   	.get_instance = iris_hfi_gen2_get_instance,
>   	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>   	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -912,7 +912,7 @@ struct iris_platform_data sm8650_data = {
>   	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>   };
> 
> -struct iris_platform_data sm8750_data = {
> +const struct iris_platform_data sm8750_data = {
>   	.get_instance = iris_hfi_gen2_get_instance,
>   	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>   	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -998,7 +998,7 @@ struct iris_platform_data sm8750_data = {
>    * - inst_caps to platform_inst_cap_qcs8300
>    * - inst_fw_caps to inst_fw_cap_qcs8300
>    */
> -struct iris_platform_data qcs8300_data = {
> +const struct iris_platform_data qcs8300_data = {
>   	.get_instance = iris_hfi_gen2_get_instance,
>   	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>   	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index e29cba993fde922b579eb7e5a59ae34bb46f9f0f..66a5bdd24d8a0e98b0554a019438bf4caa1dc43c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -314,7 +314,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = {
>   	BUF_SCRATCH_2,
>   };
> 
> -struct iris_platform_data sm8250_data = {
> +const struct iris_platform_data sm8250_data = {
>   	.get_instance = iris_hfi_gen1_get_instance,
>   	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
>   	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
> 
> --
> 2.47.3
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 4/8] media: iris: stop encoding PIPE value into fw_caps

[Dmitry Baryshkov]

On Wed, Oct 08, 2025 at 10:03:49AM +0200, Konrad Dybcio wrote:
> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> > The value of the PIPE property depends on the number of pipes available
> > on the platform and is frequently the only difference between several
> > fw_caps. In order to reduce duplciation, use num_vpp_pipe from the
> > iris_platform_data rather than hardcoding the value into the fw_cap.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >  drivers/media/platform/qcom/iris/iris_ctrls.c            | 6 +++++-
> >  drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
> >  drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
> >  drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
> >  4 files changed, 11 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> > index 0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38..8db3fa222bdb92a7ffff3dfe62d33f16c0550757 100644
> > --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> > +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> > @@ -318,7 +318,11 @@ void iris_session_init_caps(struct iris_core *core)
> >  			continue;
> >  
> >  		core->inst_fw_caps_dec[cap_id].idx = i;
> > -		core->inst_fw_caps_dec[cap_id].value = caps[i].value;
> > +		if (cap_id == PIPE)
> > +			core->inst_fw_caps_dec[cap_id].value =
> > +				core->iris_platform_data->num_vpp_pipe;
> > +		else
> > +			core->inst_fw_caps_dec[cap_id].value = caps[i].value;
> 
> I really hope this if-else won't grow in the future

It really means that PIPE and several other caps should be converted to
explicit code sequences. I think, only V4L2 controls should be a part of
the caps array. Everything else should eventually migrate out. But it's
not a subject of this patch.

> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300

[Dmitry Baryshkov]

On Wed, Oct 08, 2025 at 10:07:47AM +0200, Konrad Dybcio wrote:
> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> > Now as we have removed PIPE value from inst_fw_caps_dec there should be
> > no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
> > QCS8300-specific tables and use generic one instead.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> 
> [...]
> 
> > +static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> > +	.min_frame_width = 96,
> > +	.max_frame_width = 4096,
> > +	.min_frame_height = 96,
> > +	.max_frame_height = 4096,
> > +	.max_mbpf = (4096 * 2176) / 256,
> > +	.mb_cycles_vpp = 200,
> > +	.mb_cycles_fw = 326389,
> > +	.mb_cycles_fw_vpp = 44156,
> > +	.num_comv = 0,
> > +	.max_frame_rate = MAXIMUM_FPS,
> > +	.max_operating_rate = MAXIMUM_FPS,
> > +};
> > +
> >  const struct iris_platform_data qcs8300_data = {
> >  	.get_instance = iris_hfi_gen2_get_instance,
> >  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> > @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
> >  	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> >  	.pas_id = IRIS_PAS_ID,
> >  	.inst_caps = &platform_inst_cap_qcs8300,
> > -	.inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
> > -	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> > -	.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> > -	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> > +	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> > +	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> > +	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> > +	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> 
> 8550 enc data has a .set() under a number of caps (was qcs8300 tested?)

Welcome to a non-conflict merge issue. Commit d22037f3fd33 ("media:
iris: Set platform capabilities to firmware for encoder video device")
added .set callbacks, while commit 6bdfa3f947a7 ("media: iris: Add
platform-specific capabilities for encoder video device") extended
QCS8300 config. Nobody noticed that the second file should also be
updated, which is yet another reason for merging those two structures.

> and also additionally defines:
> 
>  * INPUT_BUF_HOST_MAX_COUNT
>  * OUTPUT_BUF_HOST_MAX_COUNT

Good question. I hope the defaults should be fine...

> 
> values of which should probably be cross-checked (they say "DEFAULT"
> so it's probably OK, but just so you know)
> 
> dec is 1 : 1
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Dmitry Baryshkov]

On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote:
> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> > As a part of migrating code from the old Venus driver to the new Iris
> > one, add support for the SC7280 platform. It is very similar to SM8250,
> > but it (currently) uses no reset controls (there is an optional
> > GCC-generated reset, it will be added later) and no AON registers
> > region. The Venus driver names this platform "IRIS2_1", so the ops in
> 
> Which we've learnt in the past is "IRIS2, 1-pipe"

Well, I'm open for better suggestions. iris_vpu2_no_aon_ops?

> 
> > the driver are also now called iris_vpu21_ops.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >  .../platform/qcom/iris/iris_platform_common.h      |   3 +
> >  .../media/platform/qcom/iris/iris_platform_gen1.c  |  66 +++++++++++
> >  drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
> >  drivers/media/platform/qcom/iris/iris_vpu2.c       | 130 +++++++++++++++++++++
> >  drivers/media/platform/qcom/iris/iris_vpu_common.h |   1 +
> >  5 files changed, 204 insertions(+)
> > 
> > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> > index 104ff38219e30e6d52476d44b54338c55ef2ca7b..36e33eb05a6918de590feca37b41c07a92e9c434 100644
> > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> > @@ -42,6 +42,7 @@ enum pipe_type {
> >  };
> >  
> >  extern const struct iris_platform_data qcs8300_data;
> > +extern const struct iris_platform_data sc7280_data;
> >  extern const struct iris_platform_data sm8250_data;
> >  extern const struct iris_platform_data sm8550_data;
> >  extern const struct iris_platform_data sm8650_data;
> > @@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data;
> >  enum platform_clk_type {
> >  	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> >  	IRIS_CTRL_CLK,
> > +	IRIS_AHB_CLK,
> 
> Interestingly, 8250 also has an AHB clock, but the clock driver keeps it
> always-on..
> 
> >  	IRIS_HW_CLK,
> > +	IRIS_HW_AXI_CLK,
> 
> This exists on SC7280 and SM6350, perhaps as a result of the bus topology

These parts are still a bit unclear to me (as well as resets usage for
sc7280).

> 
> >  	IRIS_AXI1_CLK,
> >  	IRIS_CTRL_FREERUN_CLK,
> >  	IRIS_HW_FREERUN_CLK,
> > diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> > index 2b3b8bd00a6096acaae928318d9231847ec89855..d5288a71a6a8289e5ecf69b6f38231500f2bf8b4 100644
> > --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> > +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> > @@ -364,3 +364,69 @@ const struct iris_platform_data sm8250_data = {
> >  	.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
> >  	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
> >  };
> > +
> > +static const struct bw_info sc7280_bw_table_dec[] = {
> > +	{ ((3840 * 2160) / 256) * 60, 1896000, },
> > +	{ ((3840 * 2160) / 256) * 30,  968000, },
> > +	{ ((1920 * 1080) / 256) * 60,  618000, },
> > +	{ ((1920 * 1080) / 256) * 30,  318000, },
> > +};
> > +
> > +static const char * const sc7280_opp_pd_table[] = { "cx" };
> 
> Wonder why this is different..
> 
> Oh, I can bet good money SM8250's Venus isn't fed off of MX alone..
> 
> Let's check the sauce..
> 
> It was always supposed to be M*MC*X with MX just for the VIDEO_CC
> PLLs..
> 
> [...]
> 
> > +/*
> > + * This is the same as iris_vpu_power_off_controller except
> > + * AON_WRAPPER_MVP_NOC_LPI_CONTROL / AON_WRAPPER_MVP_NOC_LPI_STATUS programming
> > + * and with added IRIS_AHB_CLK handling
> > + */
> > +static int iris_vpu21_power_off_controller(struct iris_core *core)
> 
> This is 1 : 1 the existing sm8250 code except...> +{
> > +	u32 val = 0;
> > +	int ret;
> > +
> > +	writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
> > +
> > +	writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> > +
> > +	ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
> > +				 val, val & BIT(0), 200, 2000);
> > +	if (ret)
> > +		goto disable_power;
> > +
> > +	writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
> > +
> > +	ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
> > +				 val, val == 0, 200, 2000);
> > +	if (ret)
> > +		goto disable_power;
> > +
> > +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
> > +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> > +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> > +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> > +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> > +
> > +disable_power:
> > +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
> 
> ..for this line

Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL /
AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in
iris_platform_data.

> 
> but this could be added to that one instead, since both clk APIs and the
> Iris wrappers around it are happy to consume a null pointer (funnily
> enough this one returns !void and is never checked)
> 
> similar story for other func additions

In fact, initially I had them merged, but then I couldn't find an
elegant way to handle AON regs. I can squash them back, if that's the
consensus. Any idea regarding AON regs?

-- 
With best wishes
Dmitry

Re: [PATCH 3/8] media: iris: stop copying r/o data

[Bryan O'Donoghue]

On 08/10/2025 05:33, Dmitry Baryshkov wrote:
> Most of the platform_inst_caps data is read-only. In order to lower the
> amount of memory consumed by the driver, store the value and the
> corresponding indice in the read-write data and use the rest via the
> pointer to r/o capability data.

corresponding index

> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>   drivers/media/platform/qcom/iris/iris_core.h       |   4 +-
>   drivers/media/platform/qcom/iris/iris_ctrls.c      | 238 ++++++++++-----------
>   drivers/media/platform/qcom/iris/iris_instance.h   |   3 +-
>   .../platform/qcom/iris/iris_platform_common.h      |   8 +-
>   drivers/media/platform/qcom/iris/iris_vdec.c       |   5 +-
>   drivers/media/platform/qcom/iris/iris_venc.c       |   5 +-
>   6 files changed, 135 insertions(+), 128 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
> index fb194c967ad4f9b5e00cd74f0d41e0b827ef14db..b5037ae8c71921753c165a86a277a4a4b5083b30 100644
> --- a/drivers/media/platform/qcom/iris/iris_core.h
> +++ b/drivers/media/platform/qcom/iris/iris_core.h
> @@ -115,8 +115,8 @@ struct iris_core {
>   	struct delayed_work			sys_error_handler;
>   	struct list_head			instances;
>   	/* encoder and decoder have overlapping caps, so two different arrays are required */
> -	struct platform_inst_fw_cap		inst_fw_caps_dec[INST_FW_CAP_MAX];
> -	struct platform_inst_fw_cap		inst_fw_caps_enc[INST_FW_CAP_MAX];
> +	struct platform_inst_fw_cap_value	inst_fw_caps_dec[INST_FW_CAP_MAX];
> +	struct platform_inst_fw_cap_value	inst_fw_caps_enc[INST_FW_CAP_MAX];
>   };
> 
>   int iris_core_init(struct iris_core *core);
> diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> index 9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce..0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38 100644
> --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> @@ -194,26 +194,28 @@ static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl)
>   {
>   	struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler);
>   	enum platform_inst_fw_cap_type cap_id;
> -	struct platform_inst_fw_cap *cap;
> +	unsigned int cap_idx;
>   	struct vb2_queue *q;
> 
> -	cap = &inst->fw_caps[0];
>   	cap_id = iris_get_cap_id(ctrl->id);
>   	if (!iris_valid_cap_id(cap_id))
>   		return -EINVAL;
> 
> +	cap_idx = inst->fw_caps[cap_id].idx;
> +
>   	q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
>   	if (vb2_is_streaming(q) &&
> -	    (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
> +	    (!(inst->inst_fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
>   		return -EINVAL;
> 
> -	cap[cap_id].flags |= CAP_FLAG_CLIENT_SET;
> +	inst->fw_caps[cap_id].client_set = true;

Why drop just this one bit - CAP_FLAG_CLIENT_SET.

Code seems neater with that bit retained in fw_caps to me, you have 
fewer LOC changed that way too.

> 
>   	inst->fw_caps[cap_id].value = ctrl->val;
> 
>   	if (vb2_is_streaming(q)) {
> -		if (cap[cap_id].set)
> -			cap[cap_id].set(inst, cap_id);
> +
> +		if (inst->inst_fw_caps[cap_idx].set)
> +			inst->inst_fw_caps[cap_idx].set(inst, cap_id);
>   	}
> 
>   	return 0;
> @@ -225,13 +227,14 @@ static const struct v4l2_ctrl_ops iris_ctrl_ops = {
> 
>   int iris_ctrls_init(struct iris_inst *inst)
>   {
> -	struct platform_inst_fw_cap *cap = &inst->fw_caps[0];
>   	u32 num_ctrls = 0, ctrl_idx = 0, idx = 0;
>   	u32 v4l2_id;
>   	int ret;
> 
>   	for (idx = 1; idx < INST_FW_CAP_MAX; idx++) {
> -		if (iris_get_v4l2_id(cap[idx].cap_id))
> +		unsigned int cap_idx = inst->fw_caps[idx].idx;
> +
> +		if (iris_get_v4l2_id(inst->inst_fw_caps[cap_idx].cap_id))
>   			num_ctrls++;
>   	}
> 
> @@ -245,9 +248,11 @@ int iris_ctrls_init(struct iris_inst *inst)
>   		return ret;
> 
>   	for (idx = 1; idx < INST_FW_CAP_MAX; idx++) {
> +		unsigned int cap_idx = inst->fw_caps[idx].idx;
> +		const struct platform_inst_fw_cap *cap = &inst->inst_fw_caps[cap_idx];
>   		struct v4l2_ctrl *ctrl;
> 
> -		v4l2_id = iris_get_v4l2_id(cap[idx].cap_id);
> +		v4l2_id = iris_get_v4l2_id(cap->cap_id);
>   		if (!v4l2_id)
>   			continue;
> 
> @@ -256,21 +261,21 @@ int iris_ctrls_init(struct iris_inst *inst)
>   			goto error;
>   		}
> 
> -		if (cap[idx].flags & CAP_FLAG_MENU) {
> +		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_MENU) {
>   			ctrl = v4l2_ctrl_new_std_menu(&inst->ctrl_handler,
>   						      &iris_ctrl_ops,
>   						      v4l2_id,
> -						      cap[idx].max,
> -						      ~(cap[idx].step_or_mask),
> -						      cap[idx].value);
> +						      cap[cap_idx].max,
> +						      ~(cap[cap_idx].step_or_mask),
> +						      inst->fw_caps[idx].value);
>   		} else {
>   			ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler,
>   						 &iris_ctrl_ops,
>   						 v4l2_id,
> -						 cap[idx].min,
> -						 cap[idx].max,
> -						 cap[idx].step_or_mask,
> -						 cap[idx].value);
> +						 cap[cap_idx].min,
> +						 cap[cap_idx].max,
> +						 cap[cap_idx].step_or_mask,
> +						 inst->fw_caps[idx].value);
>   		}
>   		if (!ctrl) {
>   			ret = -EINVAL;
> @@ -312,14 +317,8 @@ void iris_session_init_caps(struct iris_core *core)
>   		if (!iris_valid_cap_id(cap_id))
>   			continue;
> 
> -		core->inst_fw_caps_dec[cap_id].cap_id = caps[i].cap_id;
> -		core->inst_fw_caps_dec[cap_id].min = caps[i].min;
> -		core->inst_fw_caps_dec[cap_id].max = caps[i].max;
> -		core->inst_fw_caps_dec[cap_id].step_or_mask = caps[i].step_or_mask;
> +		core->inst_fw_caps_dec[cap_id].idx = i;
>   		core->inst_fw_caps_dec[cap_id].value = caps[i].value;
> -		core->inst_fw_caps_dec[cap_id].flags = caps[i].flags;
> -		core->inst_fw_caps_dec[cap_id].hfi_id = caps[i].hfi_id;
> -		core->inst_fw_caps_dec[cap_id].set = caps[i].set;
>   	}
> 
>   	caps = core->iris_platform_data->inst_fw_caps_enc;
> @@ -330,29 +329,23 @@ void iris_session_init_caps(struct iris_core *core)
>   		if (!iris_valid_cap_id(cap_id))
>   			continue;
> 
> -		core->inst_fw_caps_enc[cap_id].cap_id = caps[i].cap_id;
> -		core->inst_fw_caps_enc[cap_id].min = caps[i].min;
> -		core->inst_fw_caps_enc[cap_id].max = caps[i].max;
> -		core->inst_fw_caps_enc[cap_id].step_or_mask = caps[i].step_or_mask;
> +		core->inst_fw_caps_enc[cap_id].idx = i;
>   		core->inst_fw_caps_enc[cap_id].value = caps[i].value;
> -		core->inst_fw_caps_enc[cap_id].flags = caps[i].flags;
> -		core->inst_fw_caps_enc[cap_id].hfi_id = caps[i].hfi_id;
> -		core->inst_fw_caps_enc[cap_id].set = caps[i].set;
>   	}
>   }
> 
>   static u32 iris_get_port_info(struct iris_inst *inst,
> -			      enum platform_inst_fw_cap_type cap_id)
> +			      unsigned int cap_idx)
>   {
>   	if (inst->domain == DECODER) {
> -		if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
> +		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT)
>   			return HFI_PORT_BITSTREAM;
> -		else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
> +		else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT)
>   			return HFI_PORT_RAW;
>   	} else {
> -		if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT)
> +		if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT)
>   			return HFI_PORT_RAW;
> -		else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT)
> +		else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT)
>   			return HFI_PORT_BITSTREAM;
>   	}
> 
> @@ -362,12 +355,13 @@ static u32 iris_get_port_info(struct iris_inst *inst,
>   int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
>   	u32 hfi_value = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32_ENUM,
>   					     &hfi_value, sizeof(u32));
>   }
> @@ -375,12 +369,13 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
>   int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
>   	u32 hfi_value = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32,
>   					     &hfi_value, sizeof(u32));
>   }
> @@ -389,7 +384,8 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	struct v4l2_format *inp_f = inst->fmt_src;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 height = inp_f->fmt.pix_mp.height;
>   	u32 width = inp_f->fmt.pix_mp.width;
>   	u32 work_mode = STAGE_2;
> @@ -401,7 +397,7 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32,
>   					     &work_mode, sizeof(u32));
>   }
> @@ -409,12 +405,13 @@ int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
>   int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 work_route = inst->fw_caps[PIPE].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32,
>   					     &work_route, sizeof(u32));
>   }
> @@ -422,19 +419,13 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> -	u32 hfi_id, hfi_value;
> -
> -	if (inst->codec == V4L2_PIX_FMT_H264) {
> -		hfi_id = inst->fw_caps[PROFILE_H264].hfi_id;
> -		hfi_value = inst->fw_caps[PROFILE_H264].value;
> -	} else {
> -		hfi_id = inst->fw_caps[PROFILE_HEVC].hfi_id;
> -		hfi_value = inst->fw_caps[PROFILE_HEVC].value;
> -	}
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> +	u32 hfi_value = inst->fw_caps[cap_id].value;
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32_ENUM,
>   					     &hfi_value, sizeof(u32));
>   }
> @@ -442,19 +433,13 @@ int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
>   int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> -	u32 hfi_id, hfi_value;
> -
> -	if (inst->codec == V4L2_PIX_FMT_H264) {
> -		hfi_id = inst->fw_caps[LEVEL_H264].hfi_id;
> -		hfi_value = inst->fw_caps[LEVEL_H264].value;
> -	} else {
> -		hfi_id = inst->fw_caps[LEVEL_HEVC].hfi_id;
> -		hfi_value = inst->fw_caps[LEVEL_HEVC].value;
> -	}
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> +	u32 hfi_value = inst->fw_caps[cap_id].value;
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32_ENUM,
>   					     &hfi_value, sizeof(u32));
>   }
> @@ -462,20 +447,19 @@ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id
>   int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	struct hfi_profile_level pl;
> 
> -	if (inst->codec == V4L2_PIX_FMT_H264) {
> -		pl.profile = inst->fw_caps[PROFILE_H264].value;
> +	pl.profile = inst->fw_caps[cap_id].value;
> +	if (inst->codec == V4L2_PIX_FMT_H264)
>   		pl.level = inst->fw_caps[LEVEL_H264].value;
> -	} else {
> -		pl.profile = inst->fw_caps[PROFILE_HEVC].value;
> +	else
>   		pl.level = inst->fw_caps[LEVEL_HEVC].value;
> -	}
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					     HFI_HOST_FLAGS_NONE,
> -					     iris_get_port_info(inst, cap_id),
> +					     iris_get_port_info(inst, cap_idx),
>   					     HFI_PAYLOAD_U32_ENUM,
>   					     &pl, sizeof(u32));
>   }
> @@ -484,7 +468,8 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 header_mode = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 hfi_val;
> 
>   	if (header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE)
> @@ -494,7 +479,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap_
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -504,7 +489,8 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 prepend_sps_pps = inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value;
>   	u32 header_mode = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 hfi_val;
> 
>   	if (prepend_sps_pps)
> @@ -516,7 +502,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap_
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32_ENUM,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -526,7 +512,8 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 entropy_mode = inst->fw_caps[ENTROPY_MODE].value;
>   	u32 bitrate = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 max_bitrate;
> 
>   	if (inst->codec == V4L2_PIX_FMT_HEVC)
> @@ -541,7 +528,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32,
>   				     &bitrate, sizeof(u32));
>   }
> @@ -552,12 +539,13 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type
>   	u32 rc_mode = inst->fw_caps[BITRATE_MODE].value;
>   	u32 peak_bitrate = inst->fw_caps[cap_id].value;
>   	u32 bitrate = inst->fw_caps[BITRATE].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> 
>   	if (rc_mode != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR)
>   		return 0;
> 
> -	if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) {
> +	if (inst->fw_caps[cap_id].client_set) {
>   		if (peak_bitrate < bitrate)
>   			peak_bitrate = bitrate;
>   	} else {
> @@ -568,7 +556,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_type
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32,
>   				     &peak_bitrate, sizeof(u32));
>   }
> @@ -579,7 +567,8 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
>   	u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
>   	u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
>   	u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 rc_mode = 0;
> 
>   	if (!frame_rc)
> @@ -595,7 +584,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32_ENUM,
>   				     &rc_mode, sizeof(u32));
>   }
> @@ -606,7 +595,8 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
>   	u32 bitrate_mode = inst->fw_caps[BITRATE_MODE].value;
>   	u32 frame_rc = inst->fw_caps[FRAME_RC_ENABLE].value;
>   	u32 frame_skip = inst->fw_caps[FRAME_SKIP_MODE].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 rc_mode = 0;
> 
>   	if (!frame_rc)
> @@ -622,7 +612,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32_ENUM,
>   				     &rc_mode, sizeof(u32));
>   }
> @@ -631,7 +621,8 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 entropy_mode = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 hfi_val;
> 
>   	if (inst->codec != V4L2_PIX_FMT_H264)
> @@ -642,7 +633,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_fw_cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -651,7 +642,8 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 entropy_mode = inst->fw_caps[cap_id].value;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 profile;
> 
>   	if (inst->codec != V4L2_PIX_FMT_H264)
> @@ -667,7 +659,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_fw_cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_U32,
>   				     &entropy_mode, sizeof(u32));
>   }
> @@ -678,32 +670,33 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
>   	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0;
>   	u32 i_frame_qp = 0, p_frame_qp = 0, b_frame_qp = 0;
>   	u32 min_qp_enable = 0, client_qp_enable = 0;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 hfi_val;
> 
>   	if (inst->codec == V4L2_PIX_FMT_H264) {
> -		if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
> +		if (inst->fw_caps[MIN_FRAME_QP_H264].client_set)
>   			min_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[I_FRAME_MIN_QP_H264].client_set))
>   			i_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[P_FRAME_MIN_QP_H264].client_set))
>   			p_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[B_FRAME_MIN_QP_H264].client_set))
>   			b_qp_enable = 1;
>   	} else {
> -		if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
> +		if (inst->fw_caps[MIN_FRAME_QP_HEVC].client_set)
>   			min_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[I_FRAME_MIN_QP_HEVC].client_set))
>   			i_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[P_FRAME_MIN_QP_HEVC].client_set))
>   			p_qp_enable = 1;
>   		if (min_qp_enable ||
> -		    (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[B_FRAME_MIN_QP_HEVC].client_set))
>   			b_qp_enable = 1;
>   	}
> 
> @@ -731,7 +724,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_32_PACKED,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -742,32 +735,33 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
>   	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0;
>   	u32 max_qp_enable = 0, client_qp_enable;
>   	u32 i_frame_qp, p_frame_qp, b_frame_qp;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	u32 hfi_val;
> 
>   	if (inst->codec == V4L2_PIX_FMT_H264) {
> -		if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
> +		if (inst->fw_caps[MAX_FRAME_QP_H264].client_set)
>   			max_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[I_FRAME_MAX_QP_H264].client_set))
>   			i_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[P_FRAME_MAX_QP_H264].client_set))
>   			p_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[B_FRAME_MAX_QP_H264].client_set))
>   			b_qp_enable = 1;
>   	} else {
> -		if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
> +		if (inst->fw_caps[MAX_FRAME_QP_HEVC].client_set)
>   			max_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[I_FRAME_MAX_QP_HEVC].client_set))
>   			i_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[P_FRAME_MAX_QP_HEVC].client_set))
>   			p_qp_enable = 1;
>   		if (max_qp_enable ||
> -		    (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET))
> +		    (inst->fw_caps[B_FRAME_MAX_QP_HEVC].client_set))
>   			b_qp_enable = 1;
>   	}
> 
> @@ -796,7 +790,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_i
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_32_PACKED,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -806,7 +800,8 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	u32 i_qp_enable = 0, p_qp_enable = 0, b_qp_enable = 0, client_qp_enable;
>   	u32 i_frame_qp, p_frame_qp, b_frame_qp;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
>   	struct vb2_queue *q;
>   	u32 hfi_val;
> 
> @@ -822,18 +817,18 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
>   		b_qp_enable = 1;
>   	} else {
>   		if (inst->codec == V4L2_PIX_FMT_H264) {
> -			if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[I_FRAME_QP_H264].client_set)
>   				i_qp_enable = 1;
> -			if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[P_FRAME_QP_H264].client_set)
>   				p_qp_enable = 1;
> -			if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[B_FRAME_QP_H264].client_set)
>   				b_qp_enable = 1;
>   		} else {
> -			if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[I_FRAME_QP_HEVC].client_set)
>   				i_qp_enable = 1;
> -			if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[P_FRAME_QP_HEVC].client_set)
>   				p_qp_enable = 1;
> -			if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)
> +			if (inst->fw_caps[B_FRAME_QP_HEVC].client_set)
>   				b_qp_enable = 1;
>   		}
>   	}
> @@ -857,7 +852,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_32_PACKED,
>   				     &hfi_val, sizeof(u32));
>   }
> @@ -866,7 +861,8 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
>   	struct hfi_quantization_range_v2 range;
> -	u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
> +	unsigned int cap_idx = inst->fw_caps[cap_id].idx;
> +	u32 hfi_id = inst->inst_fw_caps[cap_idx].hfi_id;
> 
>   	if (inst->codec == V4L2_PIX_FMT_HEVC) {
>   		range.min_qp.qp_packed = inst->fw_caps[MIN_FRAME_QP_HEVC].value;
> @@ -878,7 +874,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
> 
>   	return hfi_ops->session_set_property(inst, hfi_id,
>   					 HFI_HOST_FLAGS_NONE,
> -				     iris_get_port_info(inst, cap_id),
> +				     iris_get_port_info(inst, cap_idx),
>   				     HFI_PAYLOAD_32_PACKED,
>   				     &range, sizeof(range));
>   }
> @@ -886,7 +882,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap
>   int iris_set_properties(struct iris_inst *inst, u32 plane)
>   {
>   	const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
> -	struct platform_inst_fw_cap *cap;
> +	const struct platform_inst_fw_cap *cap;
>   	int ret;
>   	u32 i;
> 
> @@ -895,7 +891,9 @@ int iris_set_properties(struct iris_inst *inst, u32 plane)
>   		return ret;
> 
>   	for (i = 1; i < INST_FW_CAP_MAX; i++) {
> -		cap = &inst->fw_caps[i];
> +		unsigned int cap_idx = inst->fw_caps[i].idx;
> +
> +		cap = &inst->inst_fw_caps[cap_idx];
>   		if (!iris_valid_cap_id(cap->cap_id))
>   			continue;
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h
> index 5982d7adefeab80905478b32cddba7bd4651a691..39d74bef4d188abb919c372b7529d1d0773bd96a 100644
> --- a/drivers/media/platform/qcom/iris/iris_instance.h
> +++ b/drivers/media/platform/qcom/iris/iris_instance.h
> @@ -82,7 +82,8 @@ struct iris_inst {
>   	struct completion		completion;
>   	struct completion		flush_completion;
>   	u32				flush_responses_pending;
> -	struct platform_inst_fw_cap	fw_caps[INST_FW_CAP_MAX];
> +	struct platform_inst_fw_cap_value fw_caps[INST_FW_CAP_MAX];
> +	const struct platform_inst_fw_cap *inst_fw_caps;
>   	struct iris_buffers		buffers[BUF_TYPE_MAX];
>   	u32				fw_min_count;
>   	enum iris_inst_state		state;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 5ffc1874e8c6362b1c650e912c230e9c4e3bd160..104ff38219e30e6d52476d44b54338c55ef2ca7b 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -148,7 +148,7 @@ enum platform_inst_fw_cap_flags {
>   	CAP_FLAG_MENU			= BIT(1),
>   	CAP_FLAG_INPUT_PORT		= BIT(2),
>   	CAP_FLAG_OUTPUT_PORT		= BIT(3),
> -	CAP_FLAG_CLIENT_SET		= BIT(4),
> +	// BIT(4)

/* BIT(4) */

>   	CAP_FLAG_BITMASK		= BIT(5),
>   	CAP_FLAG_VOLATILE		= BIT(6),
>   };
> @@ -165,6 +165,12 @@ struct platform_inst_fw_cap {
>   		   enum platform_inst_fw_cap_type cap_id);
>   };
> 
> +struct platform_inst_fw_cap_value {
> +	unsigned int idx;
> +	s64 value;
> +	bool client_set;
> +};
> +
>   struct bw_info {
>   	u32 mbs_per_sec;
>   	u32 bw_ddr;
> diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c
> index ae13c3e1b426bfd81a7b46dc6c3ff5eb5c4860cb..72559497e81c30373711e9b113582039f1fb5153 100644
> --- a/drivers/media/platform/qcom/iris/iris_vdec.c
> +++ b/drivers/media/platform/qcom/iris/iris_vdec.c
> @@ -55,8 +55,9 @@ int iris_vdec_inst_init(struct iris_inst *inst)
>   	inst->buffers[BUF_OUTPUT].min_count = iris_vpu_buf_count(inst, BUF_OUTPUT);
>   	inst->buffers[BUF_OUTPUT].size = f->fmt.pix_mp.plane_fmt[0].sizeimage;
> 
> -	memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0],
> -	       INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap));
> +	memcpy(inst->fw_caps, core->inst_fw_caps_dec,
> +	       sizeof(inst->fw_caps));
> +	inst->inst_fw_caps = core->iris_platform_data->inst_fw_caps_dec;
> 
>   	return iris_ctrls_init(inst);
>   }
> diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c
> index 099bd5ed4ae0294725860305254c4cad1ec88d7e..3d1d481f8048305ef9a9bf0cb435ebca68563105 100644
> --- a/drivers/media/platform/qcom/iris/iris_venc.c
> +++ b/drivers/media/platform/qcom/iris/iris_venc.c
> @@ -68,8 +68,9 @@ int iris_venc_inst_init(struct iris_inst *inst)
>   	inst->operating_rate = DEFAULT_FPS;
>   	inst->frame_rate = DEFAULT_FPS;
> 
> -	memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0],
> -	       INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap));
> +	memcpy(inst->fw_caps, core->inst_fw_caps_enc,
> +	       sizeof(inst->fw_caps));
> +	inst->inst_fw_caps = core->iris_platform_data->inst_fw_caps_enc;
> 
>   	return iris_ctrls_init(inst);
>   }
> 
> --
> 2.47.3
> 

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Bryan O'Donoghue]

On 08/10/2025 05:33, Dmitry Baryshkov wrote:
> Simplify adding new platforms by moving common registers definitions
> from VPU 3.x and "common" file to the header with other register
> defines.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>   drivers/media/platform/qcom/iris/iris_vpu3x.c      | 35 --------------
>   drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 -----------------
>   .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++++++
>   3 files changed, 56 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34a53c63c595f72 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,13 @@
>   #include "iris_vpu_common.h"
>   #include "iris_vpu_register_defines.h"
> 
> -#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> -#define AON_BASE_OFFS				0x000E0000
>   #define AON_MVP_NOC_RESET			0x0001F000
> 
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP			BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE		BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
> -#define CORE_CLK_RUN				0x0
> -/* VPU v3.5 */
> -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
> -
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT			BIT(0)
> -#define CTL_CLK_HALT				BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH				BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET			BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
> -
> -#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> -#define MSK_CORE_POWER_ON			BIT(1)
> -
>   #define AON_WRAPPER_MVP_NOC_RESET_REQ		(AON_MVP_NOC_RESET + 0x000)
>   #define VIDEO_NOC_RESET_REQ			(BIT(0) | BIT(1))
> 
>   #define AON_WRAPPER_MVP_NOC_RESET_ACK		(AON_MVP_NOC_RESET + 0x004)
> 
> -#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
> -
>   #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET	(AON_BASE_OFFS + 0x18)
>   #define SW_RESET				BIT(0)
>   #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL	(AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8088130fb625fd 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,13 +11,6 @@
>   #include "iris_vpu_common.h"
>   #include "iris_vpu_register_defines.h"
> 
> -#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> -#define AON_BASE_OFFS				0x000E0000
> -
> -#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
> -
> -#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
> -#define CLEAR_XTENSA2HOST_INTR			BIT(0)
> 
>   #define CTRL_INIT				(CPU_CS_BASE_OFFS + 0x48)
>   #define CTRL_STATUS				(CPU_CS_BASE_OFFS + 0x4C)
> @@ -35,42 +28,6 @@
>   #define UC_REGION_ADDR				(CPU_CS_BASE_OFFS + 0x64)
>   #define UC_REGION_SIZE				(CPU_CS_BASE_OFFS + 0x68)
> 
> -#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
> -#define HOST2XTENSA_INTR_ENABLE			BIT(0)
> -
> -#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> -#define MSK_CORE_POWER_ON			BIT(1)
> -
> -#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
> -#define CPU_IC_SOFTINT_H2A_SHFT			0x0
> -
> -#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
> -#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
> -#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
> -
> -#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
> -#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
> -#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> -
> -#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT			BIT(0)
> -#define CTL_CLK_HALT				BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH				BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP			BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
> -
>   static void iris_vpu_interrupt_init(struct iris_core *core)
>   {
>   	u32 mask_val;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe8ad445a0a13f4 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,65 @@
>   #define VCODEC_BASE_OFFS			0x00000000
>   #define CPU_BASE_OFFS				0x000A0000
>   #define WRAPPER_BASE_OFFS			0x000B0000
> +#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> +#define AON_BASE_OFFS				0x000E0000
> +
> +#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
> 
>   #define CPU_CS_BASE_OFFS			(CPU_BASE_OFFS)
> 
> +#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
> +#define CLEAR_XTENSA2HOST_INTR			BIT(0)
> +
> +#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
> +#define HOST2XTENSA_INTR_ENABLE			BIT(0)
> +
> +#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
> +#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
> +#define CPU_IC_SOFTINT_H2A_SHFT			0x0
> +
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
> +#define CORE_BRIDGE_SW_RESET			BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
> +
> +#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> +#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> +#define MSK_CORE_POWER_ON			BIT(1)
> +
> +#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
> +#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
> +
> +#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
> +#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
> +#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
> +
>   #define WRAPPER_CORE_POWER_STATUS		(WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> +#define REQ_POWER_DOWN_PREP			BIT(0)
> +
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> +#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE			BIT(2) /* Indicates the NOC is active */
> +
> +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
> +
> +#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
> +#define CORE_CLK_RUN				0x0
> +
> +#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
> +
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CTL_AXI_CLK_HALT			BIT(0)
> +#define CTL_CLK_HALT				BIT(1)
> +
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> +#define RESET_HIGH				BIT(0)
> +
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
> 
>   #endif
> 
> --
> 2.47.3
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 3/8] media: iris: stop copying r/o data

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 12:48:00AM +0100, Bryan O'Donoghue wrote:
> On 08/10/2025 05:33, Dmitry Baryshkov wrote:
> > Most of the platform_inst_caps data is read-only. In order to lower the
> > amount of memory consumed by the driver, store the value and the
> > corresponding indice in the read-write data and use the rest via the
> > pointer to r/o capability data.
> 
> corresponding index

Ack

> 
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >   drivers/media/platform/qcom/iris/iris_core.h       |   4 +-
> >   drivers/media/platform/qcom/iris/iris_ctrls.c      | 238 ++++++++++-----------
> >   drivers/media/platform/qcom/iris/iris_instance.h   |   3 +-
> >   .../platform/qcom/iris/iris_platform_common.h      |   8 +-
> >   drivers/media/platform/qcom/iris/iris_vdec.c       |   5 +-
> >   drivers/media/platform/qcom/iris/iris_venc.c       |   5 +-
> >   6 files changed, 135 insertions(+), 128 deletions(-)
> > 
> > diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
> > index fb194c967ad4f9b5e00cd74f0d41e0b827ef14db..b5037ae8c71921753c165a86a277a4a4b5083b30 100644
> > --- a/drivers/media/platform/qcom/iris/iris_core.h
> > +++ b/drivers/media/platform/qcom/iris/iris_core.h
> > @@ -115,8 +115,8 @@ struct iris_core {
> >   	struct delayed_work			sys_error_handler;
> >   	struct list_head			instances;
> >   	/* encoder and decoder have overlapping caps, so two different arrays are required */
> > -	struct platform_inst_fw_cap		inst_fw_caps_dec[INST_FW_CAP_MAX];
> > -	struct platform_inst_fw_cap		inst_fw_caps_enc[INST_FW_CAP_MAX];
> > +	struct platform_inst_fw_cap_value	inst_fw_caps_dec[INST_FW_CAP_MAX];
> > +	struct platform_inst_fw_cap_value	inst_fw_caps_enc[INST_FW_CAP_MAX];
> >   };
> > 
> >   int iris_core_init(struct iris_core *core);
> > diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> > index 9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce..0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38 100644
> > --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> > +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> > @@ -194,26 +194,28 @@ static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl)
> >   {
> >   	struct iris_inst *inst = container_of(ctrl->handler, struct iris_inst, ctrl_handler);
> >   	enum platform_inst_fw_cap_type cap_id;
> > -	struct platform_inst_fw_cap *cap;
> > +	unsigned int cap_idx;
> >   	struct vb2_queue *q;
> > 
> > -	cap = &inst->fw_caps[0];
> >   	cap_id = iris_get_cap_id(ctrl->id);
> >   	if (!iris_valid_cap_id(cap_id))
> >   		return -EINVAL;
> > 
> > +	cap_idx = inst->fw_caps[cap_id].idx;
> > +
> >   	q = v4l2_m2m_get_src_vq(inst->m2m_ctx);
> >   	if (vb2_is_streaming(q) &&
> > -	    (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
> > +	    (!(inst->inst_fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED)))
> >   		return -EINVAL;
> > 
> > -	cap[cap_id].flags |= CAP_FLAG_CLIENT_SET;
> > +	inst->fw_caps[cap_id].client_set = true;
> 
> Why drop just this one bit - CAP_FLAG_CLIENT_SET.
> 
> Code seems neater with that bit retained in fw_caps to me, you have fewer
> LOC changed that way too.

The problem is that all other flags are read-only and they stay in
the constant struct platform_inst_fw_cap. The CAP_FLAG_CLIENT_SET is
dynamic and it is set for each instance. Initially I kept the flag and
copied the whole flag set, but it resulted in a bigger patch, because
all cap.flags lookups were now using inst->cap[id].flag (and there are
more than just CAP_FLAG_CLIENT_SET). In the end I decided that it's not
worth copying r/o flags, but instead we should separate r/o and r/w
data. Thus CAP_FLAG_CLIENT_SET ended up being a bool field. I think it's
more logical and easier to follow the code like this. If there are
multiple flags like this. we can always change the code to add
INST_FLAG_CLIENT_SET.

> 
> > 
> >   	inst->fw_caps[cap_id].value = ctrl->val;
> > 
> >   	if (vb2_is_streaming(q)) {
> > -		if (cap[cap_id].set)
> > -			cap[cap_id].set(inst, cap_id);
> > +
> > +		if (inst->inst_fw_caps[cap_idx].set)
> > +			inst->inst_fw_caps[cap_idx].set(inst, cap_id);
> >   	}
> > 
> >   	return 0;

-- 
With best wishes
Dmitry

Re: [PATCH 1/8] media: iris: turn platform caps into constants

[Dikshita Agarwal]

On 10/8/2025 10:02 AM, Dmitry Baryshkov wrote:
> Make all struct platform_inst_fw_cap instances constant, they are not
> modified at runtime.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/media/platform/qcom/iris/iris_ctrls.c            | 2 +-
>  drivers/media/platform/qcom/iris/iris_platform_common.h  | 4 ++--
>  drivers/media/platform/qcom/iris/iris_platform_gen2.c    | 4 ++--
>  drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++--
>  drivers/media/platform/qcom/iris/iris_platform_sm8250.c  | 4 ++--
>  5 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> index 754a5ad718bc37630bb861012301df7a2e7342a1..9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce 100644
> --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> @@ -301,7 +301,7 @@ int iris_ctrls_init(struct iris_inst *inst)
>  
>  void iris_session_init_caps(struct iris_core *core)
>  {
> -	struct platform_inst_fw_cap *caps;
> +	const struct platform_inst_fw_cap *caps;
>  	u32 i, num_cap, cap_id;
>  
>  	caps = core->iris_platform_data->inst_fw_caps_dec;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 58d05e0a112eed25faea027a34c719c89d6c3897..17ed86bf78bb3b0bc3f0862253fba6505ac3d164 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -215,9 +215,9 @@ struct iris_platform_data {
>  	const char *fwname;
>  	u32 pas_id;
>  	struct platform_inst_caps *inst_caps;
> -	struct platform_inst_fw_cap *inst_fw_caps_dec;
> +	const struct platform_inst_fw_cap *inst_fw_caps_dec;
>  	u32 inst_fw_caps_dec_size;
> -	struct platform_inst_fw_cap *inst_fw_caps_enc;
> +	const struct platform_inst_fw_cap *inst_fw_caps_enc;
>  	u32 inst_fw_caps_enc_size;
>  	struct tz_cp_config *tz_cp_config_data;
>  	u32 core_arch;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 36d69cc73986b74534a2912524c8553970fd862e..cbf38e13f89e5c4c46e759fbb86777854d751552 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -19,7 +19,7 @@
>  #define VIDEO_ARCH_LX 1
>  #define BITRATE_MAX				245000000
>  
> -static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
>  	{
>  		.cap_id = PROFILE_H264,
>  		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> @@ -203,7 +203,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
>  	},
>  };
>  
> -static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
>  	{
>  		.cap_id = PROFILE_H264,
>  		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> index 35ea0efade73caa687d300779c5b1dc3b17a0128..87517361a1cf4b6fe53b8a1483188670df52c7e7 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> @@ -5,7 +5,7 @@
>  
>  #define BITRATE_MAX				245000000
>  
> -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
>  	{
>  		.cap_id = PROFILE_H264,
>  		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> @@ -189,7 +189,7 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
>  	},
>  };
>  
> -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
>  	{
>  		.cap_id = PROFILE_H264,
>  		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index 16486284f8acccf6a95a27f6003e885226e28f4d..e29cba993fde922b579eb7e5a59ae34bb46f9f0f 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -17,7 +17,7 @@
>  #define BITRATE_PEAK_DEFAULT	(BITRATE_DEFAULT * 2)
>  #define BITRATE_STEP		100
>  
> -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
>  	{
>  		.cap_id = PIPE,
>  		.min = PIPE_1,
> @@ -38,7 +38,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
>  	},
>  };
>  
> -static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
> +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
>  	{
>  		.cap_id = STAGE,
>  		.min = STAGE_1,
> 

Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

Thanks,
Dikshita

Re: [PATCH 2/8] media: iris: turn platform data into constants

[Dikshita Agarwal]

On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> Make all struct iris_platform_data instances constant, they are not
> modified at runtime.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/media/platform/qcom/iris/iris_platform_common.h | 10 +++++-----
>  drivers/media/platform/qcom/iris/iris_platform_gen2.c   |  8 ++++----
>  drivers/media/platform/qcom/iris/iris_platform_sm8250.c |  2 +-
>  3 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 17ed86bf78bb3b0bc3f0862253fba6505ac3d164..5ffc1874e8c6362b1c650e912c230e9c4e3bd160 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -41,11 +41,11 @@ enum pipe_type {
>  	PIPE_4 = 4,
>  };
>  
> -extern struct iris_platform_data qcs8300_data;
> -extern struct iris_platform_data sm8250_data;
> -extern struct iris_platform_data sm8550_data;
> -extern struct iris_platform_data sm8650_data;
> -extern struct iris_platform_data sm8750_data;
> +extern const struct iris_platform_data qcs8300_data;
> +extern const struct iris_platform_data sm8250_data;
> +extern const struct iris_platform_data sm8550_data;
> +extern const struct iris_platform_data sm8650_data;
> +extern const struct iris_platform_data sm8750_data;
>  
>  enum platform_clk_type {
>  	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index cbf38e13f89e5c4c46e759fbb86777854d751552..b444e816355624bca8248cce9da7adcd7caf6c5b 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -737,7 +737,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
>  	BUF_SCRATCH_2,
>  };
>  
> -struct iris_platform_data sm8550_data = {
> +const struct iris_platform_data sm8550_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>  	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -827,7 +827,7 @@ struct iris_platform_data sm8550_data = {
>   * - controller_rst_tbl to sm8650_controller_reset_table
>   * - fwname to "qcom/vpu/vpu33_p4.mbn"
>   */
> -struct iris_platform_data sm8650_data = {
> +const struct iris_platform_data sm8650_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>  	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -912,7 +912,7 @@ struct iris_platform_data sm8650_data = {
>  	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>  };
>  
> -struct iris_platform_data sm8750_data = {
> +const struct iris_platform_data sm8750_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>  	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> @@ -998,7 +998,7 @@ struct iris_platform_data sm8750_data = {
>   * - inst_caps to platform_inst_cap_qcs8300
>   * - inst_fw_caps to inst_fw_cap_qcs8300
>   */
> -struct iris_platform_data qcs8300_data = {
> +const struct iris_platform_data qcs8300_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>  	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> index e29cba993fde922b579eb7e5a59ae34bb46f9f0f..66a5bdd24d8a0e98b0554a019438bf4caa1dc43c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> @@ -314,7 +314,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] = {
>  	BUF_SCRATCH_2,
>  };
>  
> -struct iris_platform_data sm8250_data = {
> +const struct iris_platform_data sm8250_data = {
>  	.get_instance = iris_hfi_gen1_get_instance,
>  	.init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
>  	.init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
> 

Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

Thanks,
Dikshita

Re: [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300

[Dikshita Agarwal]

On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> Now as we have removed PIPE value from inst_fw_caps_dec there should be
> no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
> QCS8300-specific tables and use generic one instead.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  .../media/platform/qcom/iris/iris_platform_gen2.c  |  28 +-
>  .../platform/qcom/iris/iris_platform_qcs8300.h     | 550 ---------------------
>  2 files changed, 18 insertions(+), 560 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 7ad03a800356ae9fb73bdbd6d09928d0b500cb3c..5ddc579a73bbc75e3bfca5881d6eee4aa40f09c9 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -12,7 +12,6 @@
>  #include "iris_vpu_buffer.h"
>  #include "iris_vpu_common.h"
>  
> -#include "iris_platform_qcs8300.h"
>  #include "iris_platform_sm8650.h"
>  #include "iris_platform_sm8750.h"
>  
> @@ -993,11 +992,20 @@ const struct iris_platform_data sm8750_data = {
>  	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>  };
>  
> -/*
> - * Shares most of SM8550 data except:
> - * - inst_caps to platform_inst_cap_qcs8300
> - * - inst_fw_caps to inst_fw_cap_qcs8300
> - */
> +static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> +	.min_frame_width = 96,
> +	.max_frame_width = 4096,
> +	.min_frame_height = 96,
> +	.max_frame_height = 4096,
> +	.max_mbpf = (4096 * 2176) / 256,
> +	.mb_cycles_vpp = 200,
> +	.mb_cycles_fw = 326389,
> +	.mb_cycles_fw_vpp = 44156,
> +	.num_comv = 0,
> +	.max_frame_rate = MAXIMUM_FPS,
> +	.max_operating_rate = MAXIMUM_FPS,
> +};
> +
Agree with removing the fw_caps and using the generic ones.

But inst_caps should still be in separate header file for qcs8300, to keep
design consistent across SOCs.

Thanks,
Dikshita

>  const struct iris_platform_data qcs8300_data = {
>  	.get_instance = iris_hfi_gen2_get_instance,
>  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
>  	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
>  	.pas_id = IRIS_PAS_ID,
>  	.inst_caps = &platform_inst_cap_qcs8300,
> -	.inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
> -	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> -	.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> -	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> +	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> +	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> +	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> +	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>  	.tz_cp_config_data = &tz_cp_config_sm8550,
>  	.core_arch = VIDEO_ARCH_LX,
>  	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> deleted file mode 100644
> index 612526a938eed0554fc0da99e12c26d22e04bb6e..0000000000000000000000000000000000000000
> --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> +++ /dev/null
> @@ -1,550 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> - */
> -
> -#define BITRATE_MAX				245000000
> -
> -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
> -	{
> -		.cap_id = PROFILE_H264,
> -		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> -		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
> -		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> -		.hfi_id = HFI_PROP_PROFILE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = PROFILE_HEVC,
> -		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> -		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> -		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> -		.hfi_id = HFI_PROP_PROFILE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = PROFILE_VP9,
> -		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> -		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
> -		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> -		.hfi_id = HFI_PROP_PROFILE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = LEVEL_H264,
> -		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> -		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
> -		.value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
> -		.hfi_id = HFI_PROP_LEVEL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = LEVEL_HEVC,
> -		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> -		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> -		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
> -		.hfi_id = HFI_PROP_LEVEL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = LEVEL_VP9,
> -		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
> -		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
> -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
> -		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> -		.hfi_id = HFI_PROP_LEVEL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = TIER,
> -		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
> -		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
> -		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> -		.hfi_id = HFI_PROP_TIER,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -		.set = iris_set_u32_enum,
> -	},
> -	{
> -		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
> -		.min = DEFAULT_MAX_HOST_BUF_COUNT,
> -		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_MAX_HOST_BUF_COUNT,
> -		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> -		.flags = CAP_FLAG_INPUT_PORT,
> -		.set = iris_set_u32,
> -	},
> -	{
> -		.cap_id = STAGE,
> -		.min = STAGE_1,
> -		.max = STAGE_2,
> -		.step_or_mask = 1,
> -		.value = STAGE_2,
> -		.hfi_id = HFI_PROP_STAGE,
> -		.set = iris_set_stage,
> -	},
> -	{
> -		.cap_id = PIPE,
> -		.min = PIPE_1,
> -		/* .max is set via platform data */
> -		.step_or_mask = 1,
> -		/* .value is set via platform data */
> -		.hfi_id = HFI_PROP_PIPE,
> -		.set = iris_set_pipe,
> -	},
> -	{
> -		.cap_id = POC,
> -		.min = 0,
> -		.max = 2,
> -		.step_or_mask = 1,
> -		.value = 1,
> -		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
> -	},
> -	{
> -		.cap_id = CODED_FRAMES,
> -		.min = CODED_FRAMES_PROGRESSIVE,
> -		.max = CODED_FRAMES_PROGRESSIVE,
> -		.step_or_mask = 0,
> -		.value = CODED_FRAMES_PROGRESSIVE,
> -		.hfi_id = HFI_PROP_CODED_FRAMES,
> -	},
> -	{
> -		.cap_id = BIT_DEPTH,
> -		.min = BIT_DEPTH_8,
> -		.max = BIT_DEPTH_8,
> -		.step_or_mask = 1,
> -		.value = BIT_DEPTH_8,
> -		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
> -	},
> -	{
> -		.cap_id = RAP_FRAME,
> -		.min = 0,
> -		.max = 1,
> -		.step_or_mask = 1,
> -		.value = 1,
> -		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
> -		.flags = CAP_FLAG_INPUT_PORT,
> -		.set = iris_set_u32,
> -	},
> -};
> -
> -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
> -	{
> -		.cap_id = PROFILE_H264,
> -		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> -		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
> -		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> -		.hfi_id = HFI_PROP_PROFILE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = PROFILE_HEVC,
> -		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> -		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
> -		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> -		.hfi_id = HFI_PROP_PROFILE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = LEVEL_H264,
> -		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> -		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
> -		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
> -		.hfi_id = HFI_PROP_LEVEL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = LEVEL_HEVC,
> -		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> -		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> -		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> -		.hfi_id = HFI_PROP_LEVEL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = STAGE,
> -		.min = STAGE_1,
> -		.max = STAGE_2,
> -		.step_or_mask = 1,
> -		.value = STAGE_2,
> -		.hfi_id = HFI_PROP_STAGE,
> -	},
> -	{
> -		.cap_id = HEADER_MODE,
> -		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> -		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> -				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> -		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> -		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = PREPEND_SPSPPS_TO_IDR,
> -		.min = 0,
> -		.max = 1,
> -		.step_or_mask = 1,
> -		.value = 0,
> -	},
> -	{
> -		.cap_id = BITRATE,
> -		.min = 1,
> -		.max = BITRATE_MAX,
> -		.step_or_mask = 1,
> -		.value = BITRATE_DEFAULT,
> -		.hfi_id = HFI_PROP_TOTAL_BITRATE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = BITRATE_PEAK,
> -		.min = 1,
> -		.max = BITRATE_MAX,
> -		.step_or_mask = 1,
> -		.value = BITRATE_DEFAULT,
> -		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = BITRATE_MODE,
> -		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> -		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> -				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> -		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> -		.hfi_id = HFI_PROP_RATE_CONTROL,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = FRAME_SKIP_MODE,
> -		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> -		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> -				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
> -				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> -		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = FRAME_RC_ENABLE,
> -		.min = 0,
> -		.max = 1,
> -		.step_or_mask = 1,
> -		.value = 1,
> -	},
> -	{
> -		.cap_id = GOP_SIZE,
> -		.min = 0,
> -		.max = INT_MAX,
> -		.step_or_mask = 1,
> -		.value = 2 * DEFAULT_FPS - 1,
> -		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = ENTROPY_MODE,
> -		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> -		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> -				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> -		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> -		.hfi_id = HFI_PROP_CABAC_SESSION,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> -	},
> -	{
> -		.cap_id = MIN_FRAME_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT,
> -	},
> -	{
> -		.cap_id = MIN_FRAME_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT,
> -	},
> -	{
> -		.cap_id = MAX_FRAME_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT,
> -	},
> -	{
> -		.cap_id = MAX_FRAME_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT,
> -	},
> -	{
> -		.cap_id = I_FRAME_MIN_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = I_FRAME_MIN_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = P_FRAME_MIN_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = P_FRAME_MIN_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = B_FRAME_MIN_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = B_FRAME_MIN_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MIN_QP_8BIT,
> -	},
> -	{
> -		.cap_id = I_FRAME_MAX_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = I_FRAME_MAX_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = P_FRAME_MAX_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = P_FRAME_MAX_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = B_FRAME_MAX_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = B_FRAME_MAX_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = MAX_QP,
> -	},
> -	{
> -		.cap_id = I_FRAME_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = I_FRAME_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = P_FRAME_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = P_FRAME_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = B_FRAME_QP_H264,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -	{
> -		.cap_id = B_FRAME_QP_HEVC,
> -		.min = MIN_QP_8BIT,
> -		.max = MAX_QP,
> -		.step_or_mask = 1,
> -		.value = DEFAULT_QP,
> -		.hfi_id = HFI_PROP_QP_PACKED,
> -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> -			CAP_FLAG_DYNAMIC_ALLOWED,
> -	},
> -};
> -
> -static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> -	.min_frame_width = 96,
> -	.max_frame_width = 4096,
> -	.min_frame_height = 96,
> -	.max_frame_height = 4096,
> -	.max_mbpf = (4096 * 2176) / 256,
> -	.mb_cycles_vpp = 200,
> -	.mb_cycles_fw = 326389,
> -	.mb_cycles_fw_vpp = 44156,
> -	.num_comv = 0,
> -	.max_frame_rate = MAXIMUM_FPS,
> -	.max_operating_rate = MAXIMUM_FPS,
> -};
> 

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Dikshita Agarwal]

On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> Simplify adding new platforms by moving common registers definitions
> from VPU 3.x and "common" file to the header with other register
> defines.
> 

Similar to
https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
?

Thanks,
Dikshita
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/media/platform/qcom/iris/iris_vpu3x.c      | 35 --------------
>  drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 -----------------
>  .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++++++
>  3 files changed, 56 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34a53c63c595f72 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,13 @@
>  #include "iris_vpu_common.h"
>  #include "iris_vpu_register_defines.h"
>  
> -#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> -#define AON_BASE_OFFS				0x000E0000
>  #define AON_MVP_NOC_RESET			0x0001F000
>  
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP			BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE		BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
> -#define CORE_CLK_RUN				0x0
> -/* VPU v3.5 */
> -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
> -
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT			BIT(0)
> -#define CTL_CLK_HALT				BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH				BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET			BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
> -
> -#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> -#define MSK_CORE_POWER_ON			BIT(1)
> -
>  #define AON_WRAPPER_MVP_NOC_RESET_REQ		(AON_MVP_NOC_RESET + 0x000)
>  #define VIDEO_NOC_RESET_REQ			(BIT(0) | BIT(1))
>  
>  #define AON_WRAPPER_MVP_NOC_RESET_ACK		(AON_MVP_NOC_RESET + 0x004)
>  
> -#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
> -
>  #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET	(AON_BASE_OFFS + 0x18)
>  #define SW_RESET				BIT(0)
>  #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL	(AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8088130fb625fd 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,13 +11,6 @@
>  #include "iris_vpu_common.h"
>  #include "iris_vpu_register_defines.h"
>  
> -#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> -#define AON_BASE_OFFS				0x000E0000
> -
> -#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
> -
> -#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
> -#define CLEAR_XTENSA2HOST_INTR			BIT(0)
>  
>  #define CTRL_INIT				(CPU_CS_BASE_OFFS + 0x48)
>  #define CTRL_STATUS				(CPU_CS_BASE_OFFS + 0x4C)
> @@ -35,42 +28,6 @@
>  #define UC_REGION_ADDR				(CPU_CS_BASE_OFFS + 0x64)
>  #define UC_REGION_SIZE				(CPU_CS_BASE_OFFS + 0x68)
>  
> -#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
> -#define HOST2XTENSA_INTR_ENABLE			BIT(0)
> -
> -#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> -#define MSK_CORE_POWER_ON			BIT(1)
> -
> -#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
> -#define CPU_IC_SOFTINT_H2A_SHFT			0x0
> -
> -#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
> -#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
> -#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
> -
> -#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
> -#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
> -#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> -
> -#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT			BIT(0)
> -#define CTL_CLK_HALT				BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH				BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP			BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
> -
>  static void iris_vpu_interrupt_init(struct iris_core *core)
>  {
>  	u32 mask_val;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe8ad445a0a13f4 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,65 @@
>  #define VCODEC_BASE_OFFS			0x00000000
>  #define CPU_BASE_OFFS				0x000A0000
>  #define WRAPPER_BASE_OFFS			0x000B0000
> +#define WRAPPER_TZ_BASE_OFFS			0x000C0000
> +#define AON_BASE_OFFS				0x000E0000
> +
> +#define VCODEC_SS_IDLE_STATUSN			(VCODEC_BASE_OFFS + 0x70)
>  
>  #define CPU_CS_BASE_OFFS			(CPU_BASE_OFFS)
>  
> +#define CPU_CS_A2HSOFTINTCLR			(CPU_CS_BASE_OFFS + 0x1C)
> +#define CLEAR_XTENSA2HOST_INTR			BIT(0)
> +
> +#define CPU_CS_H2XSOFTINTEN			(CPU_CS_BASE_OFFS + 0x148)
> +#define HOST2XTENSA_INTR_ENABLE			BIT(0)
> +
> +#define CPU_IC_BASE_OFFS			(CPU_BASE_OFFS)
> +#define CPU_IC_SOFTINT				(CPU_IC_BASE_OFFS + 0x150)
> +#define CPU_IC_SOFTINT_H2A_SHFT			0x0
> +
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET		(CPU_CS_BASE_OFFS + 0x160)
> +#define CORE_BRIDGE_SW_RESET			BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE		BIT(1)
> +
> +#define CPU_CS_X2RPMH				(CPU_CS_BASE_OFFS + 0x168)
> +#define MSK_SIGNAL_FROM_TENSILICA		BIT(0)
> +#define MSK_CORE_POWER_ON			BIT(1)
> +
> +#define WRAPPER_INTR_STATUS			(WRAPPER_BASE_OFFS + 0x0C)
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK		BIT(3)
> +#define WRAPPER_INTR_STATUS_A2H_BMSK		BIT(2)
> +
> +#define WRAPPER_INTR_MASK			(WRAPPER_BASE_OFFS + 0x10)
> +#define WRAPPER_INTR_MASK_A2HWD_BMSK		BIT(3)
> +#define WRAPPER_INTR_MASK_A2HCPU_BMSK		BIT(2)
> +
>  #define WRAPPER_CORE_POWER_STATUS		(WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS + 0x5C)
> +#define REQ_POWER_DOWN_PREP			BIT(0)
> +
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS + 0x60)
> +#define NOC_LPI_STATUS_DONE			BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY			BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE			BIT(2) /* Indicates the NOC is active */
> +
> +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)
> +
> +#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)
> +#define CORE_CLK_RUN				0x0
> +
> +#define WRAPPER_TZ_CPU_STATUS			(WRAPPER_TZ_BASE_OFFS + 0x10)
> +
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CTL_AXI_CLK_HALT			BIT(0)
> +#define CTL_CLK_HALT				BIT(1)
> +
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET		(WRAPPER_TZ_BASE_OFFS + 0x18)
> +#define RESET_HIGH				BIT(0)
> +
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL		(AON_BASE_OFFS)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS		(AON_BASE_OFFS + 0x4)
>  
>  #endif
> 

Re: [PATCH 6/8] media: iris: rename sm8250 platform file to gen1

[Dikshita Agarwal]

On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> In preparation to adding more Gen1 platforms, which will share a
> significant amount of data, rename the SM8250 platform file to
> iris_platform_gen1.c.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
>  drivers/media/platform/qcom/iris/Makefile                               | 2 +-
>  .../platform/qcom/iris/{iris_platform_sm8250.c => iris_platform_gen1.c} | 0
>  2 files changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
> index 13270cd6d899852dded675b33d37f5919b81ccba..fad3be044e5fe783db697a592b4f09de4d42d0d2 100644
> --- a/drivers/media/platform/qcom/iris/Makefile
> +++ b/drivers/media/platform/qcom/iris/Makefile
> @@ -26,7 +26,7 @@ qcom-iris-objs += iris_buffer.o \
>               iris_vpu_common.o \
>  
>  ifeq ($(CONFIG_VIDEO_QCOM_VENUS),)
> -qcom-iris-objs += iris_platform_sm8250.o
> +qcom-iris-objs += iris_platform_gen1.o
>  endif
>  
>  obj-$(CONFIG_VIDEO_QCOM_IRIS) += qcom-iris.o
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> similarity index 100%
> rename from drivers/media/platform/qcom/iris/iris_platform_sm8250.c
> rename to drivers/media/platform/qcom/iris/iris_platform_gen1.c
> 

Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

Thanks,
Dikshita

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Konrad Dybcio]

On 10/8/25 9:25 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote:
>> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
>>> As a part of migrating code from the old Venus driver to the new Iris
>>> one, add support for the SC7280 platform. It is very similar to SM8250,
>>> but it (currently) uses no reset controls (there is an optional
>>> GCC-generated reset, it will be added later) and no AON registers
>>> region. The Venus driver names this platform "IRIS2_1", so the ops in
>>
>> Which we've learnt in the past is "IRIS2, 1-pipe"
> 
> Well, I'm open for better suggestions. iris_vpu2_no_aon_ops?

[...]

>>> +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
>>> +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>>> +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>>> +
>>> +disable_power:
>>> +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
>>
>> ..for this line
> 
> Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL /
> AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in
> iris_platform_data.
> 
>>
>> but this could be added to that one instead, since both clk APIs and the
>> Iris wrappers around it are happy to consume a null pointer (funnily
>> enough this one returns !void and is never checked)
>>
>> similar story for other func additions
> 
> In fact, initially I had them merged, but then I couldn't find an
> elegant way to handle AON regs. I can squash them back, if that's the
> consensus. Any idea regarding AON regs?

Digging in techpack/video, I found:

commit c543f70aca8d40c593b8ad342d42e913a422c552
Author: Priyanka Gujjula <pgujjula@codeaurora.org>
Date:   Fri Feb 14 13:38:31 2020 +0530

    msm: vidc: Skip AON register programming for lagoon
    
    AON register programming is used to set NOC to low
    power mode during IRIS2 power off sequence. However
    AON register memory map is not applicable and hence
    skipping AON register programming for lagoon.
    
    Change-Id: Ib63248d118ed9fecfa5fa87925e8f69625dc1ba8
    Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>


lagoon being a downstream codename of the aforementioned sm6350

Meaning yeah it's bus topology.. so I think an if-statement within
a common flow would be what we want here..

perhaps

if (core->iris_platform_data->num_vpp_pipe == 1)

just like venus and downstream do for the most part, and kick the
can down the road.. In an unlikely event someone decides to implement
IRIS2_1 on a brand new SoC, we can delay our worries..

Konrad

Re: [PATCH 1/8] media: iris: turn platform caps into constants

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 11:38:54AM +0530, Dikshita Agarwal wrote:
> 
> On 10/8/2025 10:02 AM, Dmitry Baryshkov wrote:
> > Make all struct platform_inst_fw_cap instances constant, they are not
> > modified at runtime.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> >  
> > -static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
> > +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
> >  	{
> >  		.cap_id = STAGE,
> >  		.min = STAGE_1,
> > 
> 
> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

Please trim the messages you reply to. There is little point in
scrolling the whole patch (looking for comments) to find the R-B at the
end.

-- 
With best wishes
Dmitry

Re: [PATCH 5/8] media: iris: remove duplicateion between generic gen2 data and qcs8300

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 11:40:00AM +0530, Dikshita Agarwal wrote:
> 
> 
> On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> > Now as we have removed PIPE value from inst_fw_caps_dec there should be
> > no difference between inst_fw_caps of QCS8300 and SM8550+. Drop the
> > QCS8300-specific tables and use generic one instead.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> >  .../media/platform/qcom/iris/iris_platform_gen2.c  |  28 +-
> >  .../platform/qcom/iris/iris_platform_qcs8300.h     | 550 ---------------------
> >  2 files changed, 18 insertions(+), 560 deletions(-)
> > 
> > diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> > index 7ad03a800356ae9fb73bdbd6d09928d0b500cb3c..5ddc579a73bbc75e3bfca5881d6eee4aa40f09c9 100644
> > --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> > +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> > @@ -12,7 +12,6 @@
> >  #include "iris_vpu_buffer.h"
> >  #include "iris_vpu_common.h"
> >  
> > -#include "iris_platform_qcs8300.h"
> >  #include "iris_platform_sm8650.h"
> >  #include "iris_platform_sm8750.h"
> >  
> > @@ -993,11 +992,20 @@ const struct iris_platform_data sm8750_data = {
> >  	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> >  };
> >  
> > -/*
> > - * Shares most of SM8550 data except:
> > - * - inst_caps to platform_inst_cap_qcs8300
> > - * - inst_fw_caps to inst_fw_cap_qcs8300
> > - */
> > +static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> > +	.min_frame_width = 96,
> > +	.max_frame_width = 4096,
> > +	.min_frame_height = 96,
> > +	.max_frame_height = 4096,
> > +	.max_mbpf = (4096 * 2176) / 256,
> > +	.mb_cycles_vpp = 200,
> > +	.mb_cycles_fw = 326389,
> > +	.mb_cycles_fw_vpp = 44156,
> > +	.num_comv = 0,
> > +	.max_frame_rate = MAXIMUM_FPS,
> > +	.max_operating_rate = MAXIMUM_FPS,
> > +};
> > +
> Agree with removing the fw_caps and using the generic ones.
> 
> But inst_caps should still be in separate header file for qcs8300, to keep
> design consistent across SOCs.

Ack, I will modify it accordinfly. Should the platform data be a part of
a separate header too? What is the expected split between the files?

> 
> Thanks,
> Dikshita
> 
> >  const struct iris_platform_data qcs8300_data = {
> >  	.get_instance = iris_hfi_gen2_get_instance,
> >  	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> > @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data = {
> >  	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> >  	.pas_id = IRIS_PAS_ID,
> >  	.inst_caps = &platform_inst_cap_qcs8300,
> > -	.inst_fw_caps_dec = inst_fw_cap_qcs8300_dec,
> > -	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_qcs8300_dec),
> > -	.inst_fw_caps_enc = inst_fw_cap_qcs8300_enc,
> > -	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_qcs8300_enc),
> > +	.inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
> > +	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
> > +	.inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
> > +	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
> >  	.tz_cp_config_data = &tz_cp_config_sm8550,
> >  	.core_arch = VIDEO_ARCH_LX,
> >  	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> > diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> > deleted file mode 100644
> > index 612526a938eed0554fc0da99e12c26d22e04bb6e..0000000000000000000000000000000000000000
> > --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h
> > +++ /dev/null
> > @@ -1,550 +0,0 @@
> > -/* SPDX-License-Identifier: GPL-2.0-only */
> > -/*
> > - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> > - */
> > -
> > -#define BITRATE_MAX				245000000
> > -
> > -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] = {
> > -	{
> > -		.cap_id = PROFILE_H264,
> > -		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> > -		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
> > -		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> > -		.hfi_id = HFI_PROP_PROFILE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = PROFILE_HEVC,
> > -		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> > -		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> > -		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> > -		.hfi_id = HFI_PROP_PROFILE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = PROFILE_VP9,
> > -		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> > -		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
> > -		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> > -		.hfi_id = HFI_PROP_PROFILE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = LEVEL_H264,
> > -		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> > -		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2),
> > -		.value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1,
> > -		.hfi_id = HFI_PROP_LEVEL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = LEVEL_HEVC,
> > -		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> > -		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> > -		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1,
> > -		.hfi_id = HFI_PROP_LEVEL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = LEVEL_VP9,
> > -		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
> > -		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) |
> > -				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0),
> > -		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_6_0,
> > -		.hfi_id = HFI_PROP_LEVEL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = TIER,
> > -		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
> > -		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
> > -		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> > -		.hfi_id = HFI_PROP_TIER,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -		.set = iris_set_u32_enum,
> > -	},
> > -	{
> > -		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
> > -		.min = DEFAULT_MAX_HOST_BUF_COUNT,
> > -		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_MAX_HOST_BUF_COUNT,
> > -		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> > -		.flags = CAP_FLAG_INPUT_PORT,
> > -		.set = iris_set_u32,
> > -	},
> > -	{
> > -		.cap_id = STAGE,
> > -		.min = STAGE_1,
> > -		.max = STAGE_2,
> > -		.step_or_mask = 1,
> > -		.value = STAGE_2,
> > -		.hfi_id = HFI_PROP_STAGE,
> > -		.set = iris_set_stage,
> > -	},
> > -	{
> > -		.cap_id = PIPE,
> > -		.min = PIPE_1,
> > -		/* .max is set via platform data */
> > -		.step_or_mask = 1,
> > -		/* .value is set via platform data */
> > -		.hfi_id = HFI_PROP_PIPE,
> > -		.set = iris_set_pipe,
> > -	},
> > -	{
> > -		.cap_id = POC,
> > -		.min = 0,
> > -		.max = 2,
> > -		.step_or_mask = 1,
> > -		.value = 1,
> > -		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
> > -	},
> > -	{
> > -		.cap_id = CODED_FRAMES,
> > -		.min = CODED_FRAMES_PROGRESSIVE,
> > -		.max = CODED_FRAMES_PROGRESSIVE,
> > -		.step_or_mask = 0,
> > -		.value = CODED_FRAMES_PROGRESSIVE,
> > -		.hfi_id = HFI_PROP_CODED_FRAMES,
> > -	},
> > -	{
> > -		.cap_id = BIT_DEPTH,
> > -		.min = BIT_DEPTH_8,
> > -		.max = BIT_DEPTH_8,
> > -		.step_or_mask = 1,
> > -		.value = BIT_DEPTH_8,
> > -		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
> > -	},
> > -	{
> > -		.cap_id = RAP_FRAME,
> > -		.min = 0,
> > -		.max = 1,
> > -		.step_or_mask = 1,
> > -		.value = 1,
> > -		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
> > -		.flags = CAP_FLAG_INPUT_PORT,
> > -		.set = iris_set_u32,
> > -	},
> > -};
> > -
> > -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] = {
> > -	{
> > -		.cap_id = PROFILE_H264,
> > -		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> > -		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
> > -		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> > -		.hfi_id = HFI_PROP_PROFILE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = PROFILE_HEVC,
> > -		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> > -		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
> > -		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> > -		.hfi_id = HFI_PROP_PROFILE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = LEVEL_H264,
> > -		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> > -		.max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0),
> > -		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
> > -		.hfi_id = HFI_PROP_LEVEL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = LEVEL_HEVC,
> > -		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> > -		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) |
> > -				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2),
> > -		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> > -		.hfi_id = HFI_PROP_LEVEL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = STAGE,
> > -		.min = STAGE_1,
> > -		.max = STAGE_2,
> > -		.step_or_mask = 1,
> > -		.value = STAGE_2,
> > -		.hfi_id = HFI_PROP_STAGE,
> > -	},
> > -	{
> > -		.cap_id = HEADER_MODE,
> > -		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> > -		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> > -				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> > -		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> > -		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = PREPEND_SPSPPS_TO_IDR,
> > -		.min = 0,
> > -		.max = 1,
> > -		.step_or_mask = 1,
> > -		.value = 0,
> > -	},
> > -	{
> > -		.cap_id = BITRATE,
> > -		.min = 1,
> > -		.max = BITRATE_MAX,
> > -		.step_or_mask = 1,
> > -		.value = BITRATE_DEFAULT,
> > -		.hfi_id = HFI_PROP_TOTAL_BITRATE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = BITRATE_PEAK,
> > -		.min = 1,
> > -		.max = BITRATE_MAX,
> > -		.step_or_mask = 1,
> > -		.value = BITRATE_DEFAULT,
> > -		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = BITRATE_MODE,
> > -		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> > -		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> > -				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> > -		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> > -		.hfi_id = HFI_PROP_RATE_CONTROL,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = FRAME_SKIP_MODE,
> > -		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> > -		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> > -				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
> > -				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> > -		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = FRAME_RC_ENABLE,
> > -		.min = 0,
> > -		.max = 1,
> > -		.step_or_mask = 1,
> > -		.value = 1,
> > -	},
> > -	{
> > -		.cap_id = GOP_SIZE,
> > -		.min = 0,
> > -		.max = INT_MAX,
> > -		.step_or_mask = 1,
> > -		.value = 2 * DEFAULT_FPS - 1,
> > -		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = ENTROPY_MODE,
> > -		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> > -		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> > -		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> > -				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> > -		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> > -		.hfi_id = HFI_PROP_CABAC_SESSION,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> > -	},
> > -	{
> > -		.cap_id = MIN_FRAME_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT,
> > -	},
> > -	{
> > -		.cap_id = MIN_FRAME_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT,
> > -	},
> > -	{
> > -		.cap_id = MAX_FRAME_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT,
> > -	},
> > -	{
> > -		.cap_id = MAX_FRAME_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_MIN_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_MIN_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_MIN_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_MIN_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_MIN_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_MIN_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MIN_QP_8BIT,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_MAX_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_MAX_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_MAX_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_MAX_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_MAX_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_MAX_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = MAX_QP,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = I_FRAME_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = P_FRAME_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_QP_H264,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -	{
> > -		.cap_id = B_FRAME_QP_HEVC,
> > -		.min = MIN_QP_8BIT,
> > -		.max = MAX_QP,
> > -		.step_or_mask = 1,
> > -		.value = DEFAULT_QP,
> > -		.hfi_id = HFI_PROP_QP_PACKED,
> > -		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> > -			CAP_FLAG_DYNAMIC_ALLOWED,
> > -	},
> > -};
> > -
> > -static struct platform_inst_caps platform_inst_cap_qcs8300 = {
> > -	.min_frame_width = 96,
> > -	.max_frame_width = 4096,
> > -	.min_frame_height = 96,
> > -	.max_frame_height = 4096,
> > -	.max_mbpf = (4096 * 2176) / 256,
> > -	.mb_cycles_vpp = 200,
> > -	.mb_cycles_fw = 326389,
> > -	.mb_cycles_fw_vpp = 44156,
> > -	.num_comv = 0,
> > -	.max_frame_rate = MAXIMUM_FPS,
> > -	.max_operating_rate = MAXIMUM_FPS,
> > -};
> > 

-- 
With best wishes
Dmitry

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 11:40:25AM +0530, Dikshita Agarwal wrote:
> 
> 
> On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> > Simplify adding new platforms by moving common registers definitions
> > from VPU 3.x and "common" file to the header with other register
> > defines.
> > 
> 
> Similar to
> https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
> ?

Yes, but moving more registers. I can rebase on top of that series if it
lands first. Or I can just pick that patch into the series, to remove
the dependency. What would be yours / Bryan's preference?


-- 
With best wishes
Dmitry

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 11:19:31AM +0200, Konrad Dybcio wrote:
> On 10/8/25 9:25 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote:
> >> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> >>> As a part of migrating code from the old Venus driver to the new Iris
> >>> one, add support for the SC7280 platform. It is very similar to SM8250,
> >>> but it (currently) uses no reset controls (there is an optional
> >>> GCC-generated reset, it will be added later) and no AON registers
> >>> region. The Venus driver names this platform "IRIS2_1", so the ops in
> >>
> >> Which we've learnt in the past is "IRIS2, 1-pipe"
> > 
> > Well, I'm open for better suggestions. iris_vpu2_no_aon_ops?
> 
> [...]
> 
> >>> +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
> >>> +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> >>> +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> >>> +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> >>> +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> >>> +
> >>> +disable_power:
> >>> +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
> >>
> >> ..for this line
> > 
> > Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL /
> > AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in
> > iris_platform_data.
> > 
> >>
> >> but this could be added to that one instead, since both clk APIs and the
> >> Iris wrappers around it are happy to consume a null pointer (funnily
> >> enough this one returns !void and is never checked)
> >>
> >> similar story for other func additions
> > 
> > In fact, initially I had them merged, but then I couldn't find an
> > elegant way to handle AON regs. I can squash them back, if that's the
> > consensus. Any idea regarding AON regs?
> 
> Digging in techpack/video, I found:
> 
> commit c543f70aca8d40c593b8ad342d42e913a422c552
> Author: Priyanka Gujjula <pgujjula@codeaurora.org>
> Date:   Fri Feb 14 13:38:31 2020 +0530
> 
>     msm: vidc: Skip AON register programming for lagoon
>     
>     AON register programming is used to set NOC to low
>     power mode during IRIS2 power off sequence. However
>     AON register memory map is not applicable and hence
>     skipping AON register programming for lagoon.
>     
>     Change-Id: Ib63248d118ed9fecfa5fa87925e8f69625dc1ba8
>     Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
> 
> 
> lagoon being a downstream codename of the aforementioned sm6350
> 
> Meaning yeah it's bus topology.. so I think an if-statement within
> a common flow would be what we want here..
> 
> perhaps
> 
> if (core->iris_platform_data->num_vpp_pipe == 1)
> 
> just like venus and downstream do for the most part, and kick the
> can down the road.. In an unlikely event someone decides to implement
> IRIS2_1 on a brand new SoC, we can delay our worries..

But this function is being used for VPU3 devices too, if I'm not
mistaken. So it becomes a bit ugly... Also I'm not sure if this is
really related to a num of VPP pipes or the CVP.

> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Konrad Dybcio]

On 10/9/25 5:00 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 09, 2025 at 11:19:31AM +0200, Konrad Dybcio wrote:
>> On 10/8/25 9:25 PM, Dmitry Baryshkov wrote:
>>> On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote:
>>>> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
>>>>> As a part of migrating code from the old Venus driver to the new Iris
>>>>> one, add support for the SC7280 platform. It is very similar to SM8250,
>>>>> but it (currently) uses no reset controls (there is an optional
>>>>> GCC-generated reset, it will be added later) and no AON registers
>>>>> region. The Venus driver names this platform "IRIS2_1", so the ops in
>>>>
>>>> Which we've learnt in the past is "IRIS2, 1-pipe"
>>>
>>> Well, I'm open for better suggestions. iris_vpu2_no_aon_ops?
>>
>> [...]
>>
>>>>> +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
>>>>> +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>>>>> +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
>>>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
>>>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
>>>>> +
>>>>> +disable_power:
>>>>> +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
>>>>
>>>> ..for this line
>>>
>>> Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL /
>>> AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in
>>> iris_platform_data.
>>>
>>>>
>>>> but this could be added to that one instead, since both clk APIs and the
>>>> Iris wrappers around it are happy to consume a null pointer (funnily
>>>> enough this one returns !void and is never checked)
>>>>
>>>> similar story for other func additions
>>>
>>> In fact, initially I had them merged, but then I couldn't find an
>>> elegant way to handle AON regs. I can squash them back, if that's the
>>> consensus. Any idea regarding AON regs?
>>
>> Digging in techpack/video, I found:
>>
>> commit c543f70aca8d40c593b8ad342d42e913a422c552
>> Author: Priyanka Gujjula <pgujjula@codeaurora.org>
>> Date:   Fri Feb 14 13:38:31 2020 +0530
>>
>>     msm: vidc: Skip AON register programming for lagoon
>>     
>>     AON register programming is used to set NOC to low
>>     power mode during IRIS2 power off sequence. However
>>     AON register memory map is not applicable and hence
>>     skipping AON register programming for lagoon.
>>     
>>     Change-Id: Ib63248d118ed9fecfa5fa87925e8f69625dc1ba8
>>     Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
>>
>>
>> lagoon being a downstream codename of the aforementioned sm6350
>>
>> Meaning yeah it's bus topology.. so I think an if-statement within
>> a common flow would be what we want here..
>>
>> perhaps
>>
>> if (core->iris_platform_data->num_vpp_pipe == 1)
>>
>> just like venus and downstream do for the most part, and kick the
>> can down the road.. In an unlikely event someone decides to implement
>> IRIS2_1 on a brand new SoC, we can delay our worries..
> 
> But this function is being used for VPU3 devices too, if I'm not
> mistaken. So it becomes a bit ugly... Also I'm not sure if this is
> really related to a num of VPP pipes or the CVP.

Oh.. hm.. maybe we can add a .aon_shutdown op? I'm not sure how
to proceed either

Konrad

Re: [PATCH 8/8] media: iris: enable support for SC7280 platform

[Dmitry Baryshkov]

On Thu, Oct 09, 2025 at 05:49:45PM +0200, Konrad Dybcio wrote:
> On 10/9/25 5:00 PM, Dmitry Baryshkov wrote:
> > On Thu, Oct 09, 2025 at 11:19:31AM +0200, Konrad Dybcio wrote:
> >> On 10/8/25 9:25 PM, Dmitry Baryshkov wrote:
> >>> On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote:
> >>>> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote:
> >>>>> As a part of migrating code from the old Venus driver to the new Iris
> >>>>> one, add support for the SC7280 platform. It is very similar to SM8250,
> >>>>> but it (currently) uses no reset controls (there is an optional
> >>>>> GCC-generated reset, it will be added later) and no AON registers
> >>>>> region. The Venus driver names this platform "IRIS2_1", so the ops in
> >>>>
> >>>> Which we've learnt in the past is "IRIS2, 1-pipe"
> >>>
> >>> Well, I'm open for better suggestions. iris_vpu2_no_aon_ops?
> >>
> >> [...]
> >>
> >>>>> +	writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
> >>>>> +	       core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> >>>>> +	writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> >>>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
> >>>>> +	writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
> >>>>> +
> >>>>> +disable_power:
> >>>>> +	iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
> >>>>
> >>>> ..for this line
> >>>
> >>> Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL /
> >>> AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in
> >>> iris_platform_data.
> >>>
> >>>>
> >>>> but this could be added to that one instead, since both clk APIs and the
> >>>> Iris wrappers around it are happy to consume a null pointer (funnily
> >>>> enough this one returns !void and is never checked)
> >>>>
> >>>> similar story for other func additions
> >>>
> >>> In fact, initially I had them merged, but then I couldn't find an
> >>> elegant way to handle AON regs. I can squash them back, if that's the
> >>> consensus. Any idea regarding AON regs?
> >>
> >> Digging in techpack/video, I found:
> >>
> >> commit c543f70aca8d40c593b8ad342d42e913a422c552
> >> Author: Priyanka Gujjula <pgujjula@codeaurora.org>
> >> Date:   Fri Feb 14 13:38:31 2020 +0530
> >>
> >>     msm: vidc: Skip AON register programming for lagoon
> >>     
> >>     AON register programming is used to set NOC to low
> >>     power mode during IRIS2 power off sequence. However
> >>     AON register memory map is not applicable and hence
> >>     skipping AON register programming for lagoon.
> >>     
> >>     Change-Id: Ib63248d118ed9fecfa5fa87925e8f69625dc1ba8
> >>     Signed-off-by: Priyanka Gujjula <pgujjula@codeaurora.org>
> >>
> >>
> >> lagoon being a downstream codename of the aforementioned sm6350
> >>
> >> Meaning yeah it's bus topology.. so I think an if-statement within
> >> a common flow would be what we want here..
> >>
> >> perhaps
> >>
> >> if (core->iris_platform_data->num_vpp_pipe == 1)
> >>
> >> just like venus and downstream do for the most part, and kick the
> >> can down the road.. In an unlikely event someone decides to implement
> >> IRIS2_1 on a brand new SoC, we can delay our worries..
> > 
> > But this function is being used for VPU3 devices too, if I'm not
> > mistaken. So it becomes a bit ugly... Also I'm not sure if this is
> > really related to a num of VPP pipes or the CVP.
> 
> Oh.. hm.. maybe we can add a .aon_shutdown op? I'm not sure how
> to proceed either

I think, if you want to merge those codepaths, I can add .no_aon flag to
platform data, unless maintainers disagree with this proposeal.

-- 
With best wishes
Dmitry

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Vikash Garodia]

On 10/9/2025 8:18 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 09, 2025 at 11:40:25AM +0530, Dikshita Agarwal wrote:
>>
>>
>> On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
>>> Simplify adding new platforms by moving common registers definitions
>>> from VPU 3.x and "common" file to the header with other register
>>> defines.
>>>
>>
>> Similar to
>> https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
>> ?
> 
> Yes, but moving more registers. I can rebase on top of that series if it
> lands first. Or I can just pick that patch into the series, to remove
> the dependency. What would be yours / Bryan's preference?
> 

My vote would be to rebase this one on top of earlier one.

Regards,
Vikash

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Dmitry Baryshkov]

On Tue, Oct 14, 2025 at 02:43:56PM +0530, Vikash Garodia wrote:
> 
> On 10/9/2025 8:18 PM, Dmitry Baryshkov wrote:
> > On Thu, Oct 09, 2025 at 11:40:25AM +0530, Dikshita Agarwal wrote:
> >>
> >>
> >> On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> >>> Simplify adding new platforms by moving common registers definitions
> >>> from VPU 3.x and "common" file to the header with other register
> >>> defines.
> >>>
> >>
> >> Similar to
> >> https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
> >> ?
> > 
> > Yes, but moving more registers. I can rebase on top of that series if it
> > lands first. Or I can just pick that patch into the series, to remove
> > the dependency. What would be yours / Bryan's preference?
> > 
> 
> My vote would be to rebase this one on top of earlier one.

Ack, I will rebase. Seeing that none of the patches in that series are
in R-B state, I will probably pick up just that patch into this series.
I hope it's fine with everybody.

-- 
With best wishes
Dmitry

Re: [PATCH 7/8] media: iris: move common register definitions to the header

[Vikash Garodia]

On 10/14/2025 3:21 PM, Dmitry Baryshkov wrote:
> On Tue, Oct 14, 2025 at 02:43:56PM +0530, Vikash Garodia wrote:
>>
>> On 10/9/2025 8:18 PM, Dmitry Baryshkov wrote:
>>> On Thu, Oct 09, 2025 at 11:40:25AM +0530, Dikshita Agarwal wrote:
>>>>
>>>>
>>>> On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
>>>>> Simplify adding new platforms by moving common registers definitions
>>>>> from VPU 3.x and "common" file to the header with other register
>>>>> defines.
>>>>>
>>>>
>>>> Similar to
>>>> https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
>>>> ?
>>>
>>> Yes, but moving more registers. I can rebase on top of that series if it
>>> lands first. Or I can just pick that patch into the series, to remove
>>> the dependency. What would be yours / Bryan's preference?
>>>
>>
>> My vote would be to rebase this one on top of earlier one.
> 
> Ack, I will rebase. Seeing that none of the patches in that series are
> in R-B state, I will probably pick up just that patch into this series.
> I hope it's fine with everybody.
> 

Should be good. I can keep the patch in my series as well, in my next rev, so
whichever lands first, Bryan can simply drop the patch in later series.

Regards,
Vikash