* Re: [PATCH RESEND v8 16/21] media: i2c: maxim-serdes: add MAX96724 driver [not found] ` <20251208-gmsl2-3_serdes-v8-16-7b8d457e2e04@analog.com> @ 2026-03-07 17:03 ` Cory Keitz 0 siblings, 0 replies; 2+ messages in thread From: Cory Keitz @ 2026-03-07 17:03 UTC (permalink / raw) To: dumitru.ceclan Cc: Tomi Valkeinen, Mauro Carvalho Chehab, Sakari Ailus, Laurent Pinchart, Julien Massot, Rob Herring, Niklas Söderlund, Greg Kroah-Hartman, linux-media, linux-kernel, devicetree, linux-gpio, linux-staging, mitrutzceclan, Cosmin Tanislav, Niklas Söderlund On Mon, Dec 08, 2025 at 04:13:08PM +0200, Dumitru Ceclan via B4 Relay wrote: > +static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy) > +{ > + struct max96724_priv *priv = des_to_priv(des); > + bool is_cphy = phy->bus_type == V4L2_MBUS_CSI2_CPHY; > + unsigned int num_data_lanes = phy->mipi.num_data_lanes; > + unsigned int dpll_freq = phy->link_frequency * 2; This unconditionally doubles the link frequency for the DPLL, which is correct for D-PHY (DDR clocking) but incorrect for C-PHY. Per the MAX96724 User Guide: D-PHY: "Clock freq is half; Data rate is equivalent bps/lane." e.g. 00010 = 200MHz DPLL, 200Mbps/lane data rate. C-PHY: "2.28bits/symbol." e.g. 00010 = 200MHz DPLL, 456Mbps/lane data rate. For C-PHY the DPLL value equals the symbol rate, which is the link frequency directly. Should be: unsigned int dpll_freq = is_cphy ? phy->link_frequency : phy->link_frequency * 2; The same pattern exists in max9296a_init_phy() in patch 17. I've tested the full series (backported to 6.6) with the above fix on SA8775P + MAX96724 + MAX96717 with C-PHY 3-trio @ 700MHz. Tested-by: Cory Keitz <ckeitz@amazon.com> ^ permalink raw reply [flat|nested] 2+ messages in thread
[parent not found: <20251208-gmsl2-3_serdes-v8-14-7b8d457e2e04@analog.com>]
* Re: [PATCH RESEND v8 14/21] media: i2c: add Maxim GMSL2/3 deserializer framework [not found] ` <20251208-gmsl2-3_serdes-v8-14-7b8d457e2e04@analog.com> @ 2026-03-10 16:35 ` Cory Keitz 0 siblings, 0 replies; 2+ messages in thread From: Cory Keitz @ 2026-03-10 16:35 UTC (permalink / raw) To: dumitru.ceclan Cc: Tomi Valkeinen, Mauro Carvalho Chehab, Sakari Ailus, Laurent Pinchart, Julien Massot, Rob Herring, Niklas Söderlund, Greg Kroah-Hartman, linux-media, linux-kernel, devicetree, linux-gpio, linux-staging, mitrutzceclan, Cosmin Tanislav On Mon, Dec 08, 2025 at 04:13:06PM +0200, Dumitru Ceclan via B4 Relay wrote: > +#define MAX_DES_LINK_FREQUENCY_MIN 100000000ull > +#define MAX_DES_LINK_FREQUENCY_DEFAULT 750000000ull > +#define MAX_DES_LINK_FREQUENCY_MAX 1250000000ull Related to my comments on patch 16 [1], I believe this should be set differently between DPHY and CPHY. As I test more cameras I've patched this to allow CPHY link frequencies up to 2500MHz. I'm also wondering whether these should be driver-specific rather than defined at the framework level to allow for higher capacities in future silicon. [1] https://lore.kernel.org/linux-media/aaxWATynXaVFglvS@bcd074ae11bb/ -- R, Cory ^ permalink raw reply [flat|nested] 2+ messages in thread
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2026-03-07 17:03 ` [PATCH RESEND v8 16/21] media: i2c: maxim-serdes: add MAX96724 driver Cory Keitz
[not found] ` <20251208-gmsl2-3_serdes-v8-14-7b8d457e2e04@analog.com>
2026-03-10 16:35 ` [PATCH RESEND v8 14/21] media: i2c: add Maxim GMSL2/3 deserializer framework Cory Keitz
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