* [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-01-20 8:29 ` Krzysztof Kozlowski
2023-01-19 12:48 ` [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support Garmin.Chang
` (18 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add the new binding documentation for system clock
and functional clock on MediaTek MT8188.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
.../bindings/clock/mediatek,mt8188-clock.yaml | 71 ++
.../clock/mediatek,mt8188-sys-clock.yaml | 55 ++
.../dt-bindings/clock/mediatek,mt8188-clk.h | 733 ++++++++++++++++++
3 files changed, 859 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
new file mode 100644
index 000000000000..d7214d97b2ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT8188
+
+maintainers:
+ - Garmin Chang <garmin.chang@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-vppsys0
+ - mediatek,mt8188-vppsys1
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11283000 {
+ compatible = "mediatek,mt8188-imp-iic-wrap-c";
+ reg = <0x11283000 0x1000>;
+ #clock-cells = <1>;
+ };
+
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
new file mode 100644
index 000000000000..4cf8d3af9803
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT8188
+
+maintainers:
+ - Garmin Chang <garmin.chang@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The apmixedsys provides most of PLLs which generated from SoC 26m.
+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+ The mcusys provides mux control to select the clock source in AP MCU.
+ The device nodes also provide the system control capacity for configuration.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000000 {
+ compatible = "mediatek,mt8188-topckgen", "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h
new file mode 100644
index 000000000000..3e37373ca459
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h
@@ -0,0 +1,733 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Garmin Chang <garmin.chang@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8188_H
+#define _DT_BINDINGS_CLK_MT8188_H
+
+/* TOPCKGEN */
+#define CLK_TOP_AXI 0
+#define CLK_TOP_SPM 1
+#define CLK_TOP_SCP 2
+#define CLK_TOP_BUS_AXIMEM 3
+#define CLK_TOP_VPP 4
+#define CLK_TOP_ETHDR 5
+#define CLK_TOP_IPE 6
+#define CLK_TOP_CAM 7
+#define CLK_TOP_CCU 8
+#define CLK_TOP_CCU_AHB 9
+#define CLK_TOP_IMG 10
+#define CLK_TOP_CAMTM 11
+#define CLK_TOP_DSP 12
+#define CLK_TOP_DSP1 13
+#define CLK_TOP_DSP2 14
+#define CLK_TOP_DSP3 15
+#define CLK_TOP_DSP4 16
+#define CLK_TOP_DSP5 17
+#define CLK_TOP_DSP6 18
+#define CLK_TOP_DSP7 19
+#define CLK_TOP_MFG_CORE_TMP 20
+#define CLK_TOP_CAMTG 21
+#define CLK_TOP_CAMTG2 22
+#define CLK_TOP_CAMTG3 23
+#define CLK_TOP_UART 24
+#define CLK_TOP_SPI 25
+#define CLK_TOP_MSDC50_0_HCLK 26
+#define CLK_TOP_MSDC50_0 27
+#define CLK_TOP_MSDC30_1 28
+#define CLK_TOP_MSDC30_2 29
+#define CLK_TOP_INTDIR 30
+#define CLK_TOP_AUD_INTBUS 31
+#define CLK_TOP_AUDIO_H 32
+#define CLK_TOP_PWRAP_ULPOSC 33
+#define CLK_TOP_ATB 34
+#define CLK_TOP_SSPM 35
+#define CLK_TOP_DP 36
+#define CLK_TOP_EDP 37
+#define CLK_TOP_DPI 38
+#define CLK_TOP_DISP_PWM0 39
+#define CLK_TOP_DISP_PWM1 40
+#define CLK_TOP_USB_TOP 41
+#define CLK_TOP_SSUSB_XHCI 42
+#define CLK_TOP_USB_TOP_2P 43
+#define CLK_TOP_SSUSB_XHCI_2P 44
+#define CLK_TOP_USB_TOP_3P 45
+#define CLK_TOP_SSUSB_XHCI_3P 46
+#define CLK_TOP_I2C 47
+#define CLK_TOP_SENINF 48
+#define CLK_TOP_SENINF1 49
+#define CLK_TOP_GCPU 50
+#define CLK_TOP_VENC 51
+#define CLK_TOP_VDEC 52
+#define CLK_TOP_PWM 53
+#define CLK_TOP_MCUPM 54
+#define CLK_TOP_SPMI_P_MST 55
+#define CLK_TOP_SPMI_M_MST 56
+#define CLK_TOP_DVFSRC 57
+#define CLK_TOP_TL 58
+#define CLK_TOP_AES_MSDCFDE 59
+#define CLK_TOP_DSI_OCC 60
+#define CLK_TOP_WPE_VPP 61
+#define CLK_TOP_HDCP 62
+#define CLK_TOP_HDCP_24M 63
+#define CLK_TOP_HDMI_APB 64
+#define CLK_TOP_SNPS_ETH_250M 65
+#define CLK_TOP_SNPS_ETH_62P4M_PTP 66
+#define CLK_TOP_SNPS_ETH_50M_RMII 67
+#define CLK_TOP_ADSP 68
+#define CLK_TOP_AUDIO_LOCAL_BUS 69
+#define CLK_TOP_ASM_H 70
+#define CLK_TOP_ASM_L 71
+#define CLK_TOP_APLL1 72
+#define CLK_TOP_APLL2 73
+#define CLK_TOP_APLL3 74
+#define CLK_TOP_APLL4 75
+#define CLK_TOP_APLL5 76
+#define CLK_TOP_I2SO1 77
+#define CLK_TOP_I2SO2 78
+#define CLK_TOP_I2SI1 79
+#define CLK_TOP_I2SI2 80
+#define CLK_TOP_DPTX 81
+#define CLK_TOP_AUD_IEC 82
+#define CLK_TOP_A1SYS_HP 83
+#define CLK_TOP_A2SYS 84
+#define CLK_TOP_A3SYS 85
+#define CLK_TOP_A4SYS 86
+#define CLK_TOP_ECC 87
+#define CLK_TOP_SPINOR 88
+#define CLK_TOP_ULPOSC 89
+#define CLK_TOP_SRCK 90
+#define CLK_TOP_MFG_CK_FAST_REF 91
+#define CLK_TOP_MFGPLL 92
+#define CLK_TOP_MAINPLL 93
+#define CLK_TOP_MAINPLL_D3 94
+#define CLK_TOP_MAINPLL_D4 95
+#define CLK_TOP_MAINPLL_D4_D2 96
+#define CLK_TOP_MAINPLL_D4_D4 97
+#define CLK_TOP_MAINPLL_D4_D8 98
+#define CLK_TOP_MAINPLL_D5 99
+#define CLK_TOP_MAINPLL_D5_D2 100
+#define CLK_TOP_MAINPLL_D5_D4 101
+#define CLK_TOP_MAINPLL_D5_D8 102
+#define CLK_TOP_MAINPLL_D6 103
+#define CLK_TOP_MAINPLL_D6_D2 104
+#define CLK_TOP_MAINPLL_D6_D4 105
+#define CLK_TOP_MAINPLL_D6_D8 106
+#define CLK_TOP_MAINPLL_D7 107
+#define CLK_TOP_MAINPLL_D7_D2 108
+#define CLK_TOP_MAINPLL_D7_D4 109
+#define CLK_TOP_MAINPLL_D7_D8 110
+#define CLK_TOP_MAINPLL_D9 111
+#define CLK_TOP_UNIVPLL 112
+#define CLK_TOP_UNIVPLL_D2 113
+#define CLK_TOP_UNIVPLL_D3 114
+#define CLK_TOP_UNIVPLL_D4 115
+#define CLK_TOP_UNIVPLL_D4_D2 116
+#define CLK_TOP_UNIVPLL_D4_D4 117
+#define CLK_TOP_UNIVPLL_D4_D8 118
+#define CLK_TOP_UNIVPLL_D5 119
+#define CLK_TOP_UNIVPLL_D5_D2 120
+#define CLK_TOP_UNIVPLL_D5_D4 121
+#define CLK_TOP_UNIVPLL_D5_D8 122
+#define CLK_TOP_UNIVPLL_D6 123
+#define CLK_TOP_UNIVPLL_D6_D2 124
+#define CLK_TOP_UNIVPLL_D6_D4 125
+#define CLK_TOP_UNIVPLL_D6_D8 126
+#define CLK_TOP_UNIVPLL_D7 127
+#define CLK_TOP_UNIVPLL_192M 128
+#define CLK_TOP_UNIVPLL_192M_D4 129
+#define CLK_TOP_UNIVPLL_192M_D8 130
+#define CLK_TOP_UNIVPLL_192M_D10 131
+#define CLK_TOP_UNIVPLL_192M_D16 132
+#define CLK_TOP_UNIVPLL_192M_D32 133
+#define CLK_TOP_IMGPLL 134
+#define CLK_TOP_APLL1_D3 135
+#define CLK_TOP_APLL1_D4 136
+#define CLK_TOP_APLL2_D3 137
+#define CLK_TOP_APLL2_D4 138
+#define CLK_TOP_APLL3_D4 139
+#define CLK_TOP_APLL4_D4 140
+#define CLK_TOP_APLL5_D4 141
+#define CLK_TOP_MMPLL 142
+#define CLK_TOP_MMPLL_D4 143
+#define CLK_TOP_MMPLL_D4_D2 144
+#define CLK_TOP_MMPLL_D5 145
+#define CLK_TOP_MMPLL_D5_D2 146
+#define CLK_TOP_MMPLL_D5_D4 147
+#define CLK_TOP_MMPLL_D6 148
+#define CLK_TOP_MMPLL_D6_D2 149
+#define CLK_TOP_MMPLL_D7 150
+#define CLK_TOP_MMPLL_D9 151
+#define CLK_TOP_TVDPLL1 152
+#define CLK_TOP_TVDPLL1_D2 153
+#define CLK_TOP_TVDPLL1_D4 154
+#define CLK_TOP_TVDPLL1_D8 155
+#define CLK_TOP_TVDPLL1_D16 156
+#define CLK_TOP_TVDPLL2 157
+#define CLK_TOP_TVDPLL2_D2 158
+#define CLK_TOP_TVDPLL2_D4 159
+#define CLK_TOP_TVDPLL2_D8 160
+#define CLK_TOP_TVDPLL2_D16 161
+#define CLK_TOP_MSDCPLL 162
+#define CLK_TOP_MSDCPLL_D2 163
+#define CLK_TOP_MSDCPLL_D16 164
+#define CLK_TOP_ETHPLL 165
+#define CLK_TOP_ETHPLL_D2 166
+#define CLK_TOP_ETHPLL_D4 167
+#define CLK_TOP_ETHPLL_D8 168
+#define CLK_TOP_ETHPLL_D10 169
+#define CLK_TOP_ADSPPLL 170
+#define CLK_TOP_ADSPPLL_D2 171
+#define CLK_TOP_ADSPPLL_D4 172
+#define CLK_TOP_ADSPPLL_D8 173
+#define CLK_TOP_ULPOSC1 174
+#define CLK_TOP_ULPOSC1_D2 175
+#define CLK_TOP_ULPOSC1_D4 176
+#define CLK_TOP_ULPOSC1_D8 177
+#define CLK_TOP_ULPOSC1_D7 178
+#define CLK_TOP_ULPOSC1_D10 179
+#define CLK_TOP_ULPOSC1_D16 180
+#define CLK_TOP_MPHONE_SLAVE_BCK 181
+#define CLK_TOP_PAD_FPC 182
+#define CLK_TOP_466M_FMEM 183
+#define CLK_TOP_PEXTP_PIPE 184
+#define CLK_TOP_DSI_PHY 185
+#define CLK_TOP_APLL12_CK_DIV0 186
+#define CLK_TOP_APLL12_CK_DIV1 187
+#define CLK_TOP_APLL12_CK_DIV2 188
+#define CLK_TOP_APLL12_CK_DIV3 189
+#define CLK_TOP_APLL12_CK_DIV4 190
+#define CLK_TOP_APLL12_CK_DIV9 191
+#define CLK_TOP_CFGREG_CLOCK_EN_VPP0 192
+#define CLK_TOP_CFGREG_CLOCK_EN_VPP1 193
+#define CLK_TOP_CFGREG_CLOCK_EN_VDO0 194
+#define CLK_TOP_CFGREG_CLOCK_EN_VDO1 195
+#define CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS 196
+#define CLK_TOP_CFGREG_F26M_VPP0 197
+#define CLK_TOP_CFGREG_F26M_VPP1 198
+#define CLK_TOP_CFGREG_F26M_VDO0 199
+#define CLK_TOP_CFGREG_F26M_VDO1 200
+#define CLK_TOP_CFGREG_AUD_F26M_AUD 201
+#define CLK_TOP_CFGREG_UNIPLL_SES 202
+#define CLK_TOP_CFGREG_F_PCIE_PHY_REF 203
+#define CLK_TOP_SSUSB_TOP_REF 204
+#define CLK_TOP_SSUSB_PHY_REF 205
+#define CLK_TOP_SSUSB_TOP_P1_REF 206
+#define CLK_TOP_SSUSB_PHY_P1_REF 207
+#define CLK_TOP_SSUSB_TOP_P2_REF 208
+#define CLK_TOP_SSUSB_PHY_P2_REF 209
+#define CLK_TOP_SSUSB_TOP_P3_REF 210
+#define CLK_TOP_SSUSB_PHY_P3_REF 211
+#define CLK_TOP_NR_CLK 212
+
+/* INFRACFG_AO */
+#define CLK_INFRA_AO_PMIC_TMR 0
+#define CLK_INFRA_AO_PMIC_AP 1
+#define CLK_INFRA_AO_PMIC_MD 2
+#define CLK_INFRA_AO_PMIC_CONN 3
+#define CLK_INFRA_AO_SEJ 4
+#define CLK_INFRA_AO_APXGPT 5
+#define CLK_INFRA_AO_GCE 6
+#define CLK_INFRA_AO_GCE2 7
+#define CLK_INFRA_AO_THERM 8
+#define CLK_INFRA_AO_PWM_HCLK 9
+#define CLK_INFRA_AO_PWM1 10
+#define CLK_INFRA_AO_PWM2 11
+#define CLK_INFRA_AO_PWM3 12
+#define CLK_INFRA_AO_PWM4 13
+#define CLK_INFRA_AO_PWM 14
+#define CLK_INFRA_AO_UART0 15
+#define CLK_INFRA_AO_UART1 16
+#define CLK_INFRA_AO_UART2 17
+#define CLK_INFRA_AO_UART3 18
+#define CLK_INFRA_AO_UART4 19
+#define CLK_INFRA_AO_GCE_26M 20
+#define CLK_INFRA_AO_CQ_DMA_FPC 21
+#define CLK_INFRA_AO_UART5 22
+#define CLK_INFRA_AO_HDMI_26M 23
+#define CLK_INFRA_AO_SPI0 24
+#define CLK_INFRA_AO_MSDC0 25
+#define CLK_INFRA_AO_MSDC1 26
+#define CLK_INFRA_AO_MSDC2 27
+#define CLK_INFRA_AO_MSDC0_SRC 28
+#define CLK_INFRA_AO_DVFSRC 29
+#define CLK_INFRA_AO_TRNG 30
+#define CLK_INFRA_AO_AUXADC 31
+#define CLK_INFRA_AO_CPUM 32
+#define CLK_INFRA_AO_HDMI_32K 33
+#define CLK_INFRA_AO_CEC_66M_HCLK 34
+#define CLK_INFRA_AO_PCIE_TL_26M 35
+#define CLK_INFRA_AO_MSDC1_SRC 36
+#define CLK_INFRA_AO_CEC_66M_BCLK 37
+#define CLK_INFRA_AO_PCIE_TL_96M 38
+#define CLK_INFRA_AO_DEVICE_APC 39
+#define CLK_INFRA_AO_ECC_66M_HCLK 40
+#define CLK_INFRA_AO_DEBUGSYS 41
+#define CLK_INFRA_AO_AUDIO 42
+#define CLK_INFRA_AO_PCIE_TL_32K 43
+#define CLK_INFRA_AO_DBG_TRACE 44
+#define CLK_INFRA_AO_DRAMC_F26M 45
+#define CLK_INFRA_AO_IRTX 46
+#define CLK_INFRA_AO_DISP_PWM 47
+#define CLK_INFRA_AO_CLDMA_BCLK 48
+#define CLK_INFRA_AO_AUDIO_26M_BCLK 49
+#define CLK_INFRA_AO_SPI1 50
+#define CLK_INFRA_AO_SPI2 51
+#define CLK_INFRA_AO_SPI3 52
+#define CLK_INFRA_AO_FSSPM 53
+#define CLK_INFRA_AO_SSPM_BUS_HCLK 54
+#define CLK_INFRA_AO_APDMA_BCLK 55
+#define CLK_INFRA_AO_SPI4 56
+#define CLK_INFRA_AO_SPI5 57
+#define CLK_INFRA_AO_CQ_DMA 58
+#define CLK_INFRA_AO_MSDC0_SELF 59
+#define CLK_INFRA_AO_MSDC1_SELF 60
+#define CLK_INFRA_AO_MSDC2_SELF 61
+#define CLK_INFRA_AO_I2S_DMA 62
+#define CLK_INFRA_AO_AP_MSDC0 63
+#define CLK_INFRA_AO_MD_MSDC0 64
+#define CLK_INFRA_AO_MSDC30_2 65
+#define CLK_INFRA_AO_GCPU 66
+#define CLK_INFRA_AO_PCIE_PERI_26M 67
+#define CLK_INFRA_AO_GCPU_66M_BCLK 68
+#define CLK_INFRA_AO_GCPU_133M_BCLK 69
+#define CLK_INFRA_AO_DISP_PWM1 70
+#define CLK_INFRA_AO_FBIST2FPC 71
+#define CLK_INFRA_AO_DEVICE_APC_SYNC 72
+#define CLK_INFRA_AO_PCIE_P1_PERI_26M 73
+#define CLK_INFRA_AO_133M_MCLK_CK 74
+#define CLK_INFRA_AO_66M_MCLK_CK 75
+#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 76
+#define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P 77
+#define CLK_INFRA_AO_NR_CLK 78
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ETHPLL 0
+#define CLK_APMIXED_MSDCPLL 1
+#define CLK_APMIXED_TVDPLL1 2
+#define CLK_APMIXED_TVDPLL2 3
+#define CLK_APMIXED_MMPLL 4
+#define CLK_APMIXED_MAINPLL 5
+#define CLK_APMIXED_IMGPLL 6
+#define CLK_APMIXED_UNIVPLL 7
+#define CLK_APMIXED_ADSPPLL 8
+#define CLK_APMIXED_APLL1 9
+#define CLK_APMIXED_APLL2 10
+#define CLK_APMIXED_APLL3 11
+#define CLK_APMIXED_APLL4 12
+#define CLK_APMIXED_APLL5 13
+#define CLK_APMIXED_MFGPLL 14
+#define CLK_APMIXED_PLL_SSUSB26M_EN 15
+#define CLK_APMIXED_NR_CLK 16
+
+/* AUDIODSP */
+#define CLK_AUDIODSP_AUDIO26M 0
+#define CLK_AUDIODSP_NR_CLK 1
+
+/* PERICFG_AO */
+#define CLK_PERI_AO_ETHERNET 0
+#define CLK_PERI_AO_ETHERNET_BUS 1
+#define CLK_PERI_AO_FLASHIF_BUS 2
+#define CLK_PERI_AO_FLASHIF_26M 3
+#define CLK_PERI_AO_FLASHIFLASHCK 4
+#define CLK_PERI_AO_SSUSB_2P_BUS 5
+#define CLK_PERI_AO_SSUSB_2P_XHCI 6
+#define CLK_PERI_AO_SSUSB_3P_BUS 7
+#define CLK_PERI_AO_SSUSB_3P_XHCI 8
+#define CLK_PERI_AO_SSUSB_BUS 9
+#define CLK_PERI_AO_SSUSB_XHCI 10
+#define CLK_PERI_AO_ETHERNET_MAC 11
+#define CLK_PERI_AO_PCIE_P0_FMEM 12
+#define CLK_PERI_AO_NR_CLK 13
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 0
+#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2 1
+#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3 2
+#define CLK_IMP_IIC_WRAP_C_NR_CLK 3
+
+/* IMP_IIC_WRAP_W */
+#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1 0
+#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4 1
+#define CLK_IMP_IIC_WRAP_W_NR_CLK 2
+
+/* IMP_IIC_WRAP_EN */
+#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 0
+#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6 1
+#define CLK_IMP_IIC_WRAP_EN_NR_CLK 2
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D 0
+#define CLK_MFGCFG_NR_CLK 1
+
+/* VPPSYS0 */
+#define CLK_VPP0_MDP_FG 0
+#define CLK_VPP0_STITCH 1
+#define CLK_VPP0_PADDING 2
+#define CLK_VPP0_MDP_TCC 3
+#define CLK_VPP0_WARP0_ASYNC_TX 4
+#define CLK_VPP0_WARP1_ASYNC_TX 5
+#define CLK_VPP0_MUTEX 6
+#define CLK_VPP02VPP1_RELAY 7
+#define CLK_VPP0_VPP12VPP0_ASYNC 8
+#define CLK_VPP0_MMSYSRAM_TOP 9
+#define CLK_VPP0_MDP_AAL 10
+#define CLK_VPP0_MDP_RSZ 11
+#define CLK_VPP0_SMI_COMMON_MMSRAM 12
+#define CLK_VPP0_GALS_VDO0_LARB0_MMSRAM 13
+#define CLK_VPP0_GALS_VDO0_LARB1_MMSRAM 14
+#define CLK_VPP0_GALS_VENCSYS_MMSRAM 15
+#define CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM 16
+#define CLK_VPP0_GALS_INFRA_MMSRAM 17
+#define CLK_VPP0_GALS_CAMSYS_MMSRAM 18
+#define CLK_VPP0_GALS_VPP1_LARB5_MMSRAM 19
+#define CLK_VPP0_GALS_VPP1_LARB6_MMSRAM 20
+#define CLK_VPP0_SMI_REORDER_MMSRAM 21
+#define CLK_VPP0_SMI_IOMMU 22
+#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23
+#define CLK_VPP0_MDP_RDMA 24
+#define CLK_VPP0_MDP_WROT 25
+#define CLK_VPP0_GALS_EMI0_EMI1 26
+#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27
+#define CLK_VPP0_SMI_RSI 28
+#define CLK_VPP0_SMI_COMMON_LARB4 29
+#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30
+#define CLK_VPP0_GALS_VPP1_WPESYS 31
+#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32
+#define CLK_VPP0_FAKE_ENG 33
+#define CLK_VPP0_MDP_HDR 34
+#define CLK_VPP0_MDP_TDSHP 35
+#define CLK_VPP0_MDP_COLOR 36
+#define CLK_VPP0_MDP_OVL 37
+#define CLK_VPP0_DSIP_RDMA 38
+#define CLK_VPP0_DISP_WDMA 39
+#define CLK_VPP0_MDP_HMS 40
+#define CLK_VPP0_WARP0_RELAY 41
+#define CLK_VPP0_WARP0_ASYNC 42
+#define CLK_VPP0_WARP1_RELAY 43
+#define CLK_VPP0_WARP1_ASYNC 44
+#define CLK_VPP0_NR_CLK 45
+
+/* WPESYS */
+#define CLK_WPE_TOP_WPE_VPP0 0
+#define CLK_WPE_TOP_SMI_LARB7 1
+#define CLK_WPE_TOP_WPESYS_EVENT_TX 2
+#define CLK_WPE_TOP_SMI_LARB7_PCLK_EN 3
+#define CLK_WPE_TOP_NR_CLK 4
+
+/* WPESYS_VPP0 */
+#define CLK_WPE_VPP0_VECI 0
+#define CLK_WPE_VPP0_VEC2I 1
+#define CLK_WPE_VPP0_VEC3I 2
+#define CLK_WPE_VPP0_WPEO 3
+#define CLK_WPE_VPP0_MSKO 4
+#define CLK_WPE_VPP0_VGEN 5
+#define CLK_WPE_VPP0_EXT 6
+#define CLK_WPE_VPP0_VFC 7
+#define CLK_WPE_VPP0_CACH0_TOP 8
+#define CLK_WPE_VPP0_CACH0_DMA 9
+#define CLK_WPE_VPP0_CACH1_TOP 10
+#define CLK_WPE_VPP0_CACH1_DMA 11
+#define CLK_WPE_VPP0_CACH2_TOP 12
+#define CLK_WPE_VPP0_CACH2_DMA 13
+#define CLK_WPE_VPP0_CACH3_TOP 14
+#define CLK_WPE_VPP0_CACH3_DMA 15
+#define CLK_WPE_VPP0_PSP 16
+#define CLK_WPE_VPP0_PSP2 17
+#define CLK_WPE_VPP0_SYNC 18
+#define CLK_WPE_VPP0_C24 19
+#define CLK_WPE_VPP0_MDP_CROP 20
+#define CLK_WPE_VPP0_ISP_CROP 21
+#define CLK_WPE_VPP0_TOP 22
+#define CLK_WPE_VPP0_NR_CLK 23
+
+/* VPPSYS1 */
+#define CLK_VPP1_SVPP1_MDP_OVL 0
+#define CLK_VPP1_SVPP1_MDP_TCC 1
+#define CLK_VPP1_SVPP1_MDP_WROT 2
+#define CLK_VPP1_SVPP1_VPP_PAD 3
+#define CLK_VPP1_SVPP2_MDP_WROT 4
+#define CLK_VPP1_SVPP2_VPP_PAD 5
+#define CLK_VPP1_SVPP3_MDP_WROT 6
+#define CLK_VPP1_SVPP3_VPP_PAD 7
+#define CLK_VPP1_SVPP1_MDP_RDMA 8
+#define CLK_VPP1_SVPP1_MDP_FG 9
+#define CLK_VPP1_SVPP2_MDP_RDMA 10
+#define CLK_VPP1_SVPP2_MDP_FG 11
+#define CLK_VPP1_SVPP3_MDP_RDMA 12
+#define CLK_VPP1_SVPP3_MDP_FG 13
+#define CLK_VPP1_VPP_SPLIT 14
+#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15
+#define CLK_VPP1_SVPP1_MDP_RSZ 16
+#define CLK_VPP1_SVPP1_MDP_TDSHP 17
+#define CLK_VPP1_SVPP1_MDP_COLOR 18
+#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 19
+#define CLK_VPP1_SVPP2_MDP_RSZ 20
+#define CLK_VPP1_SVPP2_VPP_MERGE 21
+#define CLK_VPP1_SVPP2_MDP_TDSHP 22
+#define CLK_VPP1_SVPP2_MDP_COLOR 23
+#define CLK_VPP1_SVPP3_MDP_RSZ 24
+#define CLK_VPP1_SVPP3_VPP_MERGE 25
+#define CLK_VPP1_SVPP3_MDP_TDSHP 26
+#define CLK_VPP1_SVPP3_MDP_COLOR 27
+#define CLK_VPP1_GALS5 28
+#define CLK_VPP1_GALS6 29
+#define CLK_VPP1_LARB5 30
+#define CLK_VPP1_LARB6 31
+#define CLK_VPP1_SVPP1_MDP_HDR 32
+#define CLK_VPP1_SVPP1_MDP_AAL 33
+#define CLK_VPP1_SVPP2_MDP_HDR 34
+#define CLK_VPP1_SVPP2_MDP_AAL 35
+#define CLK_VPP1_SVPP3_MDP_HDR 36
+#define CLK_VPP1_SVPP3_MDP_AAL 37
+#define CLK_VPP1_DISP_MUTEX 38
+#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 39
+#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 40
+#define CLK_VPP1_VPP0_DL_ASYNC 41
+#define CLK_VPP1_VPP0_DL1_RELAY 42
+#define CLK_VPP1_LARB5_FAKE_ENG 43
+#define CLK_VPP1_LARB6_FAKE_ENG 44
+#define CLK_VPP1_HDMI_META 45
+#define CLK_VPP1_VPP_SPLIT_HDMI 46
+#define CLK_VPP1_DGI_IN 47
+#define CLK_VPP1_DGI_OUT 48
+#define CLK_VPP1_VPP_SPLIT_DGI 49
+#define CLK_VPP1_DL_CON_OCC 50
+#define CLK_VPP1_VPP_SPLIT_26M 51
+#define CLK_VPP1_NR_CLK 52
+
+/* IMGSYS */
+#define CLK_IMGSYS_MAIN_LARB9 0
+#define CLK_IMGSYS_MAIN_TRAW0 1
+#define CLK_IMGSYS_MAIN_TRAW1 2
+#define CLK_IMGSYS_MAIN_VCORE_GALS 3
+#define CLK_IMGSYS_MAIN_DIP0 4
+#define CLK_IMGSYS_MAIN_WPE0 5
+#define CLK_IMGSYS_MAIN_IPE 6
+#define CLK_IMGSYS_MAIN_WPE1 7
+#define CLK_IMGSYS_MAIN_WPE2 8
+#define CLK_IMGSYS_MAIN_GALS 9
+#define CLK_IMGSYS_MAIN_NR_CLK 10
+
+/* IMGSYS1_DIP_TOP */
+#define CLK_IMGSYS1_DIP_TOP_LARB10 0
+#define CLK_IMGSYS1_DIP_TOP_DIP_TOP 1
+#define CLK_IMGSYS1_DIP_TOP_NR_CLK 2
+
+/* IMGSYS1_DIP_NR */
+#define CLK_IMGSYS1_DIP_NR_LARB15 0
+#define CLK_IMGSYS1_DIP_NR_DIP_NR 1
+#define CLK_IMGSYS1_DIP_NR_NR_CLK 2
+
+/* IMGSYS_WPE1 */
+#define CLK_IMGSYS_WPE1_LARB11 0
+#define CLK_IMGSYS_WPE1 1
+#define CLK_IMGSYS_WPE1_NR_CLK 2
+
+/* IPESYS */
+#define CLK_IPE_DPE 0
+#define CLK_IPE_FDVT 1
+#define CLK_IPE_ME 2
+#define CLK_IPESYS_TOP 3
+#define CLK_IPE_SMI_LARB12 4
+#define CLK_IPE_NR_CLK 5
+
+/* IMGSYS_WPE2 */
+#define CLK_IMGSYS_WPE2_LARB11 0
+#define CLK_IMGSYS_WPE2 1
+#define CLK_IMGSYS_WPE2_NR_CLK 2
+
+/* IMGSYS_WPE3 */
+#define CLK_IMGSYS_WPE3_LARB11 0
+#define CLK_IMGSYS_WPE3 1
+#define CLK_IMGSYS_WPE3_NR_CLK 2
+
+/* CAMSYS */
+#define CLK_CAM_MAIN_LARB13 0
+#define CLK_CAM_MAIN_LARB14 1
+#define CLK_CAM_MAIN_CAM 2
+#define CLK_CAM_MAIN_CAM_SUBA 3
+#define CLK_CAM_MAIN_CAM_SUBB 4
+#define CLK_CAM_MAIN_CAMTG 5
+#define CLK_CAM_MAIN_SENINF 6
+#define CLK_CAM_MAIN_GCAMSVA 7
+#define CLK_CAM_MAIN_GCAMSVB 8
+#define CLK_CAM_MAIN_GCAMSVC 9
+#define CLK_CAM_MAIN_GCAMSVD 10
+#define CLK_CAM_MAIN_GCAMSVE 11
+#define CLK_CAM_MAIN_GCAMSVF 12
+#define CLK_CAM_MAIN_GCAMSVG 13
+#define CLK_CAM_MAIN_GCAMSVH 14
+#define CLK_CAM_MAIN_GCAMSVI 15
+#define CLK_CAM_MAIN_GCAMSVJ 16
+#define CLK_CAM_MAIN_CAMSV_TOP 17
+#define CLK_CAM_MAIN_CAMSV_CQ_A 18
+#define CLK_CAM_MAIN_CAMSV_CQ_B 19
+#define CLK_CAM_MAIN_CAMSV_CQ_C 20
+#define CLK_CAM_MAIN_FAKE_ENG 21
+#define CLK_CAM_MAIN_CAM2MM0_GALS 22
+#define CLK_CAM_MAIN_CAM2MM1_GALS 23
+#define CLK_CAM_MAIN_CAM2SYS_GALS 24
+#define CLK_CAM_MAIN_NR_CLK 25
+
+/* CAMSYS_RAWA */
+#define CLK_CAM_RAWA_LARBX 0
+#define CLK_CAM_RAWA_CAM 1
+#define CLK_CAM_RAWA_CAMTG 2
+#define CLK_CAM_RAWA_NR_CLK 3
+
+/* CAMSYS_YUVA */
+#define CLK_CAM_YUVA_LARBX 0
+#define CLK_CAM_YUVA_CAM 1
+#define CLK_CAM_YUVA_CAMTG 2
+#define CLK_CAM_YUVA_NR_CLK 3
+
+/* CAMSYS_RAWB */
+#define CLK_CAM_RAWB_LARBX 0
+#define CLK_CAM_RAWB_CAM 1
+#define CLK_CAM_RAWB_CAMTG 2
+#define CLK_CAM_RAWB_NR_CLK 3
+
+/* CAMSYS_YUVB */
+#define CLK_CAM_YUVB_LARBX 0
+#define CLK_CAM_YUVB_CAM 1
+#define CLK_CAM_YUVB_CAMTG 2
+#define CLK_CAM_YUVB_NR_CLK 3
+
+/* CCUSYS */
+#define CLK_CCU_LARB27 0
+#define CLK_CCU_AHB 1
+#define CLK_CCU_CCU0 2
+#define CLK_CCU_NR_CLK 3
+
+/* VDECSYS_SOC */
+#define CLK_VDE1_SOC_LARB1 0
+#define CLK_VDE1_SOC_LAT 1
+#define CLK_VDE1_SOC_LAT_ACTIVE 2
+#define CLK_VDE1_SOC_LAT_ENG 3
+#define CLK_VDE1_SOC_VDEC 4
+#define CLK_VDE1_SOC_VDEC_ACTIVE 5
+#define CLK_VDE1_SOC_VDEC_ENG 6
+#define CLK_VDE1_NR_CLK 7
+
+/* VDECSYS */
+#define CLK_VDE2_LARB1 0
+#define CLK_VDE2_LAT 1
+#define CLK_VDE2_VDEC 2
+#define CLK_VDE2_VDEC_ACTIVE 3
+#define CLK_VDE2_VDEC_ENG 4
+#define CLK_VDE2_NR_CLK 5
+
+/* VENCSYS */
+#define CLK_VEN1_CKE0_LARB 0
+#define CLK_VEN1_CKE1_VENC 1
+#define CLK_VEN1_CKE2_JPGENC 2
+#define CLK_VEN1_CKE3_JPGDEC 3
+#define CLK_VEN1_CKE4_JPGDEC_C1 4
+#define CLK_VEN1_CKE5_GALS 5
+#define CLK_VEN1_CKE6_GALS_SRAM 6
+#define CLK_VEN1_NR_CLK 7
+
+/* VDOSYS0 */
+#define CLK_VDO0_DISP_OVL0 0
+#define CLK_VDO0_FAKE_ENG0 1
+#define CLK_VDO0_DISP_CCORR0 2
+#define CLK_VDO0_DISP_MUTEX0 3
+#define CLK_VDO0_DISP_GAMMA0 4
+#define CLK_VDO0_DISP_DITHER0 5
+#define CLK_VDO0_DISP_WDMA0 6
+#define CLK_VDO0_DISP_RDMA0 7
+#define CLK_VDO0_DSI0 8
+#define CLK_VDO0_DSI1 9
+#define CLK_VDO0_DSC_WRAP0 10
+#define CLK_VDO0_VPP_MERGE0 11
+#define CLK_VDO0_DP_INTF0 12
+#define CLK_VDO0_DISP_AAL0 13
+#define CLK_VDO0_INLINEROT0 14
+#define CLK_VDO0_APB_BUS 15
+#define CLK_VDO0_DISP_COLOR0 16
+#define CLK_VDO0_MDP_WROT0 17
+#define CLK_VDO0_DISP_RSZ0 18
+#define CLK_VDO0_DISP_POSTMASK0 19
+#define CLK_VDO0_FAKE_ENG1 20
+#define CLK_VDO0_DL_ASYNC2 21
+#define CLK_VDO0_DL_RELAY3 22
+#define CLK_VDO0_DL_RELAY4 23
+#define CLK_VDO0_SMI_GALS 24
+#define CLK_VDO0_SMI_COMMON 25
+#define CLK_VDO0_SMI_EMI 26
+#define CLK_VDO0_SMI_IOMMU 27
+#define CLK_VDO0_SMI_LARB 28
+#define CLK_VDO0_SMI_RSI 29
+#define CLK_VDO0_DSI0_DSI 30
+#define CLK_VDO0_DSI1_DSI 31
+#define CLK_VDO0_DP_INTF0_DP_INTF 32
+#define CLK_VDO0_NR_CLK 33
+
+/* VDOSYS1 */
+#define CLK_VDO1_SMI_LARB2 0
+#define CLK_VDO1_SMI_LARB3 1
+#define CLK_VDO1_GALS 2
+#define CLK_VDO1_FAKE_ENG0 3
+#define CLK_VDO1_FAKE_ENG1 4
+#define CLK_VDO1_MDP_RDMA0 5
+#define CLK_VDO1_MDP_RDMA1 6
+#define CLK_VDO1_MDP_RDMA2 7
+#define CLK_VDO1_MDP_RDMA3 8
+#define CLK_VDO1_VPP_MERGE0 9
+#define CLK_VDO1_VPP_MERGE1 10
+#define CLK_VDO1_VPP_MERGE2 11
+#define CLK_VDO1_VPP_MERGE3 12
+#define CLK_VDO1_VPP_MERGE4 13
+#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14
+#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15
+#define CLK_VDO1_DISP_MUTEX 16
+#define CLK_VDO1_MDP_RDMA4 17
+#define CLK_VDO1_MDP_RDMA5 18
+#define CLK_VDO1_MDP_RDMA6 19
+#define CLK_VDO1_MDP_RDMA7 20
+#define CLK_VDO1_DP_INTF0_MMCK 21
+#define CLK_VDO1_DPI0_MM 22
+#define CLK_VDO1_DPI1_MM 23
+#define CLK_VDO1_MERGE0_DL_ASYNC 24
+#define CLK_VDO1_MERGE1_DL_ASYNC 25
+#define CLK_VDO1_MERGE2_DL_ASYNC 26
+#define CLK_VDO1_MERGE3_DL_ASYNC 27
+#define CLK_VDO1_MERGE4_DL_ASYNC 28
+#define CLK_VDO1_DSC_VDO1_DL_ASYNC 29
+#define CLK_VDO1_MERGE_VDO1_DL_ASYNC 30
+#define CLK_VDO1_PADDING0 31
+#define CLK_VDO1_PADDING1 32
+#define CLK_VDO1_PADDING2 33
+#define CLK_VDO1_PADDING3 34
+#define CLK_VDO1_PADDING4 35
+#define CLK_VDO1_PADDING5 36
+#define CLK_VDO1_PADDING6 37
+#define CLK_VDO1_PADDING7 38
+#define CLK_VDO1_DISP_RSZ0 39
+#define CLK_VDO1_DISP_RSZ1 40
+#define CLK_VDO1_DISP_RSZ2 41
+#define CLK_VDO1_DISP_RSZ3 42
+#define CLK_VDO1_HDR_VDO_FE0 43
+#define CLK_VDO1_HDR_GFX_FE0 44
+#define CLK_VDO1_HDR_VDO_BE 45
+#define CLK_VDO1_HDR_VDO_FE1 46
+#define CLK_VDO1_HDR_GFX_FE1 47
+#define CLK_VDO1_DISP_MIXER 48
+#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 49
+#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 50
+#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 51
+#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 52
+#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 53
+#define CLK_VDO1_DPI0 54
+#define CLK_VDO1_DISP_MONITOR_DPI0 55
+#define CLK_VDO1_DPI1 56
+#define CLK_VDO1_DISP_MONITOR_DPI1 57
+#define CLK_VDO1_DPINTF 58
+#define CLK_VDO1_DISP_MONITOR_DPINTF 59
+#define CLK_VDO1_26M_SLOW 60
+#define CLK_VDO1_NR_CLK 61
+
+#endif /* _DT_BINDINGS_CLK_MT8188_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock
2023-01-19 12:48 ` [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock Garmin.Chang
@ 2023-01-20 8:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 55+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-20 8:29 UTC (permalink / raw)
To: Garmin.Chang, Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On 19/01/2023 13:48, Garmin.Chang wrote:
> Add the new binding documentation for system clock
> and functional clock on MediaTek MT8188.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> .../bindings/clock/mediatek,mt8188-clock.yaml | 71 ++
> .../clock/mediatek,mt8188-sys-clock.yaml | 55 ++
> .../dt-bindings/clock/mediatek,mt8188-clk.h | 733 ++++++++++++++++++
> 3 files changed, 859 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
2023-01-19 12:48 ` [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:44 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen " Garmin.Chang
` (17 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 apmixedsys clock controller which provides Plls
generated from SoC 26m and ssusb clock gate control.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Kconfig | 11 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 154 +++++++++++++++++++
3 files changed, 166 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 22e8e79475ee..f02b679f71d0 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -565,6 +565,17 @@ config COMMON_CLK_MT8186
help
This driver supports MediaTek MT8186 clocks.
+config COMMON_CLK_MT8188
+ bool "Clock driver for MediaTek MT8188"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT8188 basic clocks and clocks
+ required for various peripheral found on MediaTek. Choose
+ M or Y here if you want to use clocks such as peri_ao,
+ infra_ao, etc.
+
config COMMON_CLK_MT8192
bool "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e24080fd6e7f..13ab8deb362c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
+obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
new file mode 100644
index 000000000000..8d73ae3a0da8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_APMIXED(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate apmixed_clks[] = {
+ GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
+};
+
+#define MT8188_PLL_FMAX (3800UL * MHZ)
+#define MT8188_PLL_FMIN (1500UL * MHZ)
+#define MT8188_INTEGER_BITS 8
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
+ _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
+ _pcw_reg, _pcw_shift, _pcw_chg_reg, \
+ _en_reg, _pll_en_bit) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8188_PLL_FMAX, \
+ .fmin = MT8188_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8188_INTEGER_BITS, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ .en_reg = _en_reg, \
+ .pll_en_bit = _pll_en_bit, \
+ }
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
+ 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
+ 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
+ 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
+ 0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
+ HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
+ HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
+ 0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
+ HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
+ 0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
+ 0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
+ 0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
+ 0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
+ 0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
+ 0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
+ PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
+ 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
+};
+
+static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
+ { .compatible = "mediatek,mt8188-apmixedsys", },
+ {}
+};
+
+static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ if (r)
+ goto free_apmixed_data;
+
+ r = mtk_clk_register_gates_with_dev(node, apmixed_clks,
+ ARRAY_SIZE(apmixed_clks), clk_data, NULL);
+ if (r)
+ goto unregister_plls;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
+unregister_plls:
+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+free_apmixed_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static int clk_mt8188_apmixed_remove(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_apmixed_drv = {
+ .probe = clk_mt8188_apmixed_probe,
+ .remove = clk_mt8188_apmixed_remove,
+ .driver = {
+ .name = "clk-mt8188-apmixed",
+ .of_match_table = of_match_clk_mt8188_apmixed,
+ },
+};
+builtin_platform_driver(clk_mt8188_apmixed_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support
2023-01-19 12:48 ` [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support Garmin.Chang
@ 2023-02-03 7:44 ` Chen-Yu Tsai
2023-03-09 5:41 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:44 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 apmixedsys clock controller which provides Plls
> generated from SoC 26m and ssusb clock gate control.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 11 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 154 +++++++++++++++++++
> 3 files changed, 166 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 22e8e79475ee..f02b679f71d0 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -565,6 +565,17 @@ config COMMON_CLK_MT8186
> help
> This driver supports MediaTek MT8186 clocks.
>
> +config COMMON_CLK_MT8188
> + bool "Clock driver for MediaTek MT8188"
> + depends on ARM64 || COMPILE_TEST
> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK
> + help
> + This driver supports MediaTek MT8188 basic clocks and clocks
> + required for various peripheral found on MediaTek. Choose
> + M or Y here if you want to use clocks such as peri_ao,
> + infra_ao, etc.
> +
> config COMMON_CLK_MT8192
> bool "Clock driver for MediaTek MT8192"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index e24080fd6e7f..13ab8deb362c 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -83,6 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
> clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
> clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
> +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> new file mode 100644
> index 000000000000..8d73ae3a0da8
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +#include "clk-pll.h"
> +
> +static const struct mtk_gate_regs apmixed_cg_regs = {
> + .set_ofs = 0x8,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x8,
> +};
> +
> +#define GATE_APMIXED(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate apmixed_clks[] = {
> + GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
> +};
> +
> +#define MT8188_PLL_FMAX (3800UL * MHZ)
> +#define MT8188_PLL_FMIN (1500UL * MHZ)
> +#define MT8188_INTEGER_BITS 8
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
> + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
> + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
> + _pcw_reg, _pcw_shift, _pcw_chg_reg, \
> + _en_reg, _pll_en_bit) { \
> + .id = _id, \
> + .name = _name, \
> + .reg = _reg, \
> + .pwr_reg = _pwr_reg, \
> + .en_mask = _en_mask, \
> + .flags = _flags, \
> + .rst_bar_mask = _rst_bar_mask, \
> + .fmax = MT8188_PLL_FMAX, \
> + .fmin = MT8188_PLL_FMIN, \
> + .pcwbits = _pcwbits, \
> + .pcwibits = MT8188_INTEGER_BITS, \
> + .pd_reg = _pd_reg, \
> + .pd_shift = _pd_shift, \
> + .tuner_reg = _tuner_reg, \
> + .tuner_en_reg = _tuner_en_reg, \
> + .tuner_en_bit = _tuner_en_bit, \
> + .pcw_reg = _pcw_reg, \
> + .pcw_shift = _pcw_shift, \
> + .pcw_chg_reg = _pcw_chg_reg, \
> + .en_reg = _en_reg, \
> + .pll_en_bit = _pll_en_bit, \
> + }
> +
> +static const struct mtk_pll_data plls[] = {
> + PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
> + 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
> + 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
> + 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
> + 0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
> + HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
> + HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
> + 0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
> + HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
> + 0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
> + 0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
> + 0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
> + 0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
> + 0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
> + 0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
> + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
> + 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
> + { .compatible = "mediatek,mt8188-apmixedsys", },
> + {}
> +};
> +
> +static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> + if (r)
> + goto free_apmixed_data;
> +
> + r = mtk_clk_register_gates_with_dev(node, apmixed_clks,
> + ARRAY_SIZE(apmixed_clks), clk_data, NULL);
This API is gone. Please replace it with mtk_clk_register_clks. And please
pass in the |struct device| pointer.
ChenYu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support
2023-02-03 7:44 ` Chen-Yu Tsai
@ 2023-03-09 5:41 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:41 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:44 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 apmixedsys clock controller which provides Plls
> > generated from SoC 26m and ssusb clock gate control.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Kconfig | 11 ++
> > drivers/clk/mediatek/Makefile | 1 +
> > drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 154
> > +++++++++++++++++++
> > 3 files changed, 166 insertions(+)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> >
> > diff --git a/drivers/clk/mediatek/Kconfig
> > b/drivers/clk/mediatek/Kconfig
> > index 22e8e79475ee..f02b679f71d0 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -565,6 +565,17 @@ config COMMON_CLK_MT8186
> > help
> > This driver supports MediaTek MT8186 clocks.
> >
> > +config COMMON_CLK_MT8188
> > + bool "Clock driver for MediaTek MT8188"
> > + depends on ARM64 || COMPILE_TEST
> > + select COMMON_CLK_MEDIATEK
> > + default ARCH_MEDIATEK
> > + help
> > + This driver supports MediaTek MT8188 basic clocks and
> > clocks
> > + required for various peripheral found on MediaTek. Choose
> > + M or Y here if you want to use clocks such as peri_ao,
> > + infra_ao, etc.
> > +
> > config COMMON_CLK_MT8192
> > bool "Clock driver for MediaTek MT8192"
> > depends on ARM64 || COMPILE_TEST
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index e24080fd6e7f..13ab8deb362c 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -83,6 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > clk-mt8186-mfg.o clk-mt8186-mm.o
> > clk-mt8186-wpe.o \
> > clk-mt8186-img.o clk-mt8186-
> > vdec.o clk-mt8186-venc.o \
> > clk-mt8186-cam.o clk-mt8186-
> > mdp.o clk-mt8186-ipe.o
> > +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > new file mode 100644
> > index 000000000000..8d73ae3a0da8
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > @@ -0,0 +1,154 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +#include "clk-pll.h"
> > +
> > +static const struct mtk_gate_regs apmixed_cg_regs = {
> > + .set_ofs = 0x8,
> > + .clr_ofs = 0x8,
> > + .sta_ofs = 0x8,
> > +};
> > +
> > +#define GATE_APMIXED(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr_inv)
> > +
> > +static const struct mtk_gate apmixed_clks[] = {
> > + GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN,
> > "pll_ssusb26m_en", "clk26m", 1),
> > +};
> > +
> > +#define MT8188_PLL_FMAX (3800UL * MHZ)
> > +#define MT8188_PLL_FMIN (1500UL * MHZ)
> > +#define MT8188_INTEGER_BITS 8
> > +
> > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask,
> > _flags, \
> > + _rst_bar_mask, _pcwbits, _pd_reg,
> > _pd_shift, \
> > + _tuner_reg, _tuner_en_reg,
> > _tuner_en_bit, \
> > + _pcw_reg, _pcw_shift,
> > _pcw_chg_reg, \
> > + _en_reg, _pll_en_bit)
> > { \
> > + .id =
> > _id, \
> > + .name =
> > _name, \
> > + .reg =
> > _reg, \
> > + .pwr_reg =
> > _pwr_reg, \
> > + .en_mask =
> > _en_mask, \
> > + .flags =
> > _flags, \
> > + .rst_bar_mask =
> > _rst_bar_mask, \
> > + .fmax =
> > MT8188_PLL_FMAX, \
> > + .fmin =
> > MT8188_PLL_FMIN, \
> > + .pcwbits =
> > _pcwbits, \
> > + .pcwibits =
> > MT8188_INTEGER_BITS, \
> > + .pd_reg =
> > _pd_reg, \
> > + .pd_shift =
> > _pd_shift, \
> > + .tuner_reg =
> > _tuner_reg, \
> > + .tuner_en_reg =
> > _tuner_en_reg, \
> > + .tuner_en_bit =
> > _tuner_en_bit, \
> > + .pcw_reg =
> > _pcw_reg, \
> > + .pcw_shift =
> > _pcw_shift, \
> > + .pcw_chg_reg =
> > _pcw_chg_reg, \
> > + .en_reg =
> > _en_reg, \
> > + .pll_en_bit =
> > _pll_en_bit, \
> > + }
> > +
> > +static const struct mtk_pll_data plls[] = {
> > + PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
> > + 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
> > + 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
> > + 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
> > + 0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
> > + HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548,
> > 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468,
> > 0xff000000,
> > + HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460,
> > 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
> > + 0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510,
> > 0xff000000,
> > + HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508,
> > 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
> > + 0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
> > + PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
> > + 0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0,
> > 0, 9),
> > + PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
> > + 0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0,
> > 0, 9),
> > + PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
> > + 0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0,
> > 0, 9),
> > + PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
> > + 0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0,
> > 0, 9),
> > + PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
> > + 0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0,
> > 0, 9),
> > + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
> > + 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
> > + { .compatible = "mediatek,mt8188-apmixedsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *clk_data;
> > + struct device_node *node = pdev->dev.of_node;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
> > clk_data);
> > + if (r)
> > + goto free_apmixed_data;
> > +
> > + r = mtk_clk_register_gates_with_dev(node, apmixed_clks,
> > + ARRAY_SIZE(apmixed_clks), clk_data, NULL);
>
> This API is gone. Please replace it with mtk_clk_register_clks. And
> please
> pass in the |struct device| pointer.
>
> ChenYu
Thank you for your suggestions.
OK, I will use mtk_clk_register_gates in v6.
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
2023-01-19 12:48 ` [PATCH v5 01/19] dt-bindings: clock: mediatek: Add new MT8188 clock Garmin.Chang
2023-01-19 12:48 ` [PATCH v5 02/19] clk: mediatek: Add MT8188 apmixedsys clock support Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:43 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral " Garmin.Chang
` (16 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 topckgen clock controller which provides muxes, dividers
to handle variety clock selection in other IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-topckgen.c | 1352 ++++++++++++++++++++
2 files changed, 1353 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-topckgen.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 13ab8deb362c..89b1b331cad0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -83,7 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
-obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
+obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
new file mode 100644
index 000000000000..dd0014b461ff
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
@@ -0,0 +1,1352 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+static DEFINE_SPINLOCK(mt8188_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
+ FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000),
+ FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
+ FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000),
+ FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
+ FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll_ck", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll_ck", 1, 6),
+ FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll_ck", 1, 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll_ck", 1, 9),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll_ck", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll_ck", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll_ck", 1, 13),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
+ FACTOR(CLK_TOP_IMGPLL, "imgpll_ck", "imgpll", 1, 1),
+ FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+ FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
+ FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
+ FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
+ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_ck", 1, 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll_ck", 1, 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_ck", 1, 6),
+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll_ck", 1, 7),
+ FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll_ck", 1, 9),
+ FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
+ FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
+ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll_ck", 1, 16),
+ FACTOR(CLK_TOP_ETHPLL, "ethpll_ck", "ethpll", 1, 1),
+ FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll_ck", 1, 2),
+ FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll_ck", 1, 4),
+ FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll_ck", 1, 8),
+ FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll_ck", 1, 10),
+ FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
+ FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll_ck", 1, 2),
+ FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll_ck", 1, 4),
+ FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll_ck", 1, 8),
+ FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2),
+ FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4),
+ FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8),
+ FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7),
+ FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10),
+ FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "ulposc1_d4"
+};
+
+static const char * const spm_parents[] = {
+ "clk26m",
+ "ulposc1_d10",
+ "mainpll_d7_d4",
+ "clk32k"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "univpll_d4",
+ "mainpll_d6",
+ "univpll_d6",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d3",
+ "mainpll_d3"
+};
+
+static const char * const bus_aximem_parents[] = {
+ "clk26m",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6"
+};
+
+static const char * const vpp_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "univpll_d4_d2",
+ "mmpll_d4_d2",
+ "mmpll_d7",
+ "univpll_d6",
+ "mainpll_d4",
+ "mmpll_d5",
+ "tvdpll1",
+ "tvdpll2",
+ "univpll_d4",
+ "mmpll_d4"
+};
+
+static const char * const ethdr_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "univpll_d4_d2",
+ "mmpll_d4_d2",
+ "mmpll_d7",
+ "univpll_d6",
+ "mainpll_d4",
+ "mmpll_d5_d4",
+ "tvdpll1",
+ "tvdpll2",
+ "univpll_d4",
+ "mmpll_d4"
+};
+
+static const char * const ipe_parents[] = {
+ "clk26m",
+ "imgpll_ck",
+ "mainpll_d4",
+ "mmpll_d6",
+ "univpll_d6",
+ "mainpll_d6",
+ "mmpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "mainpll_d7"
+};
+
+static const char * const cam_parents[] = {
+ "clk26m",
+ "tvdpll1",
+ "mainpll_d4",
+ "mmpll_d4",
+ "univpll_d4",
+ "univpll_d5",
+ "univpll_d6",
+ "mmpll_d7",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "imgpll_ck"
+};
+
+static const char * const ccu_parents[] = {
+ "clk26m",
+ "univpll_d6",
+ "mainpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d5",
+ "mainpll_d6",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d4_d2",
+ "univpll_d7"
+};
+
+static const char * const ccu_ahb_parents[] = {
+ "clk26m",
+ "univpll_d6",
+ "mainpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d5",
+ "mainpll_d6",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d4_d2",
+ "univpll_d7"
+};
+
+static const char * const img_parents[] = {
+ "clk26m",
+ "imgpll_ck",
+ "univpll_d4",
+ "mainpll_d4",
+ "univpll_d5",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d6",
+ "mainpll_d6",
+ "mmpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d5_d2"
+};
+
+static const char * const camtm_parents[] = {
+ "clk26m",
+ "univpll_d4_d4",
+ "univpll_d6_d2",
+ "univpll_d6_d4"
+};
+
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp1_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "mmpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp2_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "mmpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp3_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "mmpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp4_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp5_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp6_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp7_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const mfg_core_tmp_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2",
+ "univpll_d6",
+ "univpll_d7"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d6_d8",
+ "univpll_192m_d4",
+ "univpll_192m_d10",
+ "clk13m",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const camtg2_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d6_d8",
+ "univpll_192m_d4",
+ "univpll_192m_d10",
+ "clk13m",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const camtg3_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d6_d8",
+ "univpll_192m_d4",
+ "univpll_192m_d10",
+ "clk13m",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll_d6_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d4_d4",
+ "univpll_d5_d4"
+};
+
+static const char * const msdc5hclk_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d6_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll_d4_d4",
+ "mainpll_d6_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7_d2",
+ "msdcpll_d2"
+};
+
+static const char * const msdc30_2_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7_d2",
+ "msdcpll_d2"
+};
+
+static const char * const intdir_parents[] = {
+ "clk26m",
+ "univpll_d6",
+ "mainpll_d4",
+ "univpll_d4"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d4"
+};
+
+static const char * const audio_h_parents[] = {
+ "clk26m",
+ "univpll_d7",
+ "apll1",
+ "apll2"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+ "clk26m",
+ "ulposc1_d10",
+ "ulposc1_d7",
+ "ulposc1_d8",
+ "ulposc1_d16",
+ "mainpll_d4_d8",
+ "univpll_d5_d8",
+ "tvdpll1_d16"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const sspm_parents[] = {
+ "clk26m",
+ "mainpll_d7_d2",
+ "mainpll_d6_d2",
+ "mainpll_d5_d2",
+ "mainpll_d9",
+ "mainpll_d4_d2"
+};
+
+static const char * const dp_parents[] = {
+ "clk26m",
+ "tvdpll1_d2",
+ "tvdpll2_d2",
+ "tvdpll1_d4",
+ "tvdpll2_d4",
+ "tvdpll1_d8",
+ "tvdpll2_d8",
+ "tvdpll1_d16",
+ "tvdpll2_d16"
+};
+
+static const char * const edp_parents[] = {
+ "clk26m",
+ "tvdpll1_d2",
+ "tvdpll2_d2",
+ "tvdpll1_d4",
+ "tvdpll2_d4",
+ "tvdpll1_d8",
+ "tvdpll2_d8",
+ "tvdpll1_d16",
+ "tvdpll2_d16"
+};
+
+static const char * const dpi_parents[] = {
+ "clk26m",
+ "tvdpll1_d2",
+ "tvdpll2_d2",
+ "tvdpll1_d4",
+ "tvdpll2_d4",
+ "tvdpll1_d8",
+ "tvdpll2_d8",
+ "tvdpll1_d16",
+ "tvdpll2_d16"
+};
+
+static const char * const disp_pwm0_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "ulposc1_d2",
+ "ulposc1_d4",
+ "ulposc1_d16",
+ "ethpll_d4"
+};
+
+static const char * const disp_pwm1_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "ulposc1_d2",
+ "ulposc1_d4",
+ "ulposc1_d16"
+};
+
+static const char * const usb_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const usb_2p_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_2p_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const usb_3p_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const ssusb_xhci_3p_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "mainpll_d4_d8",
+ "univpll_d5_d4"
+};
+
+static const char * const seninf_parents[] = {
+ "clk26m",
+ "univpll_d4_d4",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d7",
+ "univpll_d6",
+ "mmpll_d6",
+ "univpll_d5"
+};
+
+static const char * const seninf1_parents[] = {
+ "clk26m",
+ "univpll_d4_d4",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d7",
+ "univpll_d6",
+ "mmpll_d6",
+ "univpll_d5"
+};
+
+static const char * const gcpu_parents[] = {
+ "clk26m",
+ "mainpll_d6",
+ "univpll_d4_d2",
+ "mmpll_d5_d2",
+ "univpll_d5_d2"
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "mmpll_d4_d2",
+ "mainpll_d6",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d6",
+ "mmpll_d6",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "mmpll_d9",
+ "univpll_d4_d4",
+ "mainpll_d4",
+ "univpll_d4",
+ "univpll_d5",
+ "univpll_d5_d2",
+ "mainpll_d5"
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "univpll_d4_d2",
+ "mmpll_d4_d2",
+ "univpll_d6",
+ "mainpll_d5",
+ "univpll_d5",
+ "mmpll_d6",
+ "mainpll_d4",
+ "tvdpll2",
+ "univpll_d4",
+ "imgpll_ck",
+ "univpll_d6_d2",
+ "mmpll_d9"
+};
+
+static const char * const pwm_parents[] = {
+ "clk32k",
+ "clk26m",
+ "univpll_d4_d8",
+ "univpll_d6_d4"
+};
+
+static const char * const mcupm_parents[] = {
+ "clk26m",
+ "mainpll_d6_d2",
+ "mainpll_d7_d4"
+};
+
+static const char * const spmi_p_mst_parents[] = {
+ "clk26m",
+ "clk13m",
+ "ulposc1_d8",
+ "ulposc1_d10",
+ "ulposc1_d16",
+ "ulposc1_d7",
+ "clk32k",
+ "mainpll_d7_d8",
+ "mainpll_d6_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const spmi_m_mst_parents[] = {
+ "clk26m",
+ "clk13m",
+ "ulposc1_d8",
+ "ulposc1_d10",
+ "ulposc1_d16",
+ "ulposc1_d7",
+ "clk32k",
+ "mainpll_d7_d8",
+ "mainpll_d6_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const dvfsrc_parents[] = {
+ "clk26m",
+ "ulposc1_d10",
+ "univpll_d6_d8",
+ "msdcpll_d16"
+};
+
+static const char * const tl_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "mainpll_d4_d4"
+};
+
+static const char * const aes_msdcfde_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "mainpll_d4_d4",
+ "univpll_d4_d2",
+ "univpll_d6"
+};
+
+static const char * const dsi_occ_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d5_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const wpe_vpp_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "mmpll_d4_d2",
+ "mainpll_d6",
+ "mmpll_d7",
+ "univpll_d6",
+ "mainpll_d5",
+ "univpll_d5",
+ "mainpll_d4",
+ "tvdpll1",
+ "univpll_d4"
+};
+
+static const char * const hdcp_parents[] = {
+ "clk26m",
+ "univpll_d4_d8",
+ "mainpll_d5_d8",
+ "univpll_d6_d4"
+};
+
+static const char * const hdcp_24m_parents[] = {
+ "clk26m",
+ "univpll_192m_d4",
+ "univpll_192m_d8",
+ "univpll_d6_d8"
+};
+
+static const char * const hdmi_apb_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "msdcpll_d2"
+};
+
+static const char * const snps_eth_250m_parents[] = {
+ "clk26m",
+ "ethpll_d2"
+};
+
+static const char * const snps_eth_62p4m_ptp_parents[] = {
+ "apll2_d3",
+ "apll1_d3",
+ "clk26m",
+ "ethpll_d8"
+};
+
+static const char * const snps_eth_50m_rmii_parents[] = {
+ "clk26m",
+ "ethpll_d10"
+};
+
+static const char * const adsp_parents[] = {
+ "clk26m",
+ "clk13m",
+ "mainpll_d6",
+ "mainpll_d5_d2",
+ "univpll_d4_d4",
+ "univpll_d4",
+ "ulposc1_d2",
+ "ulposc1_ck1",
+ "adsppll_ck",
+ "adsppll_d2",
+ "adsppll_d4",
+ "adsppll_d8"
+};
+
+static const char * const audio_local_bus_parents[] = {
+ "clk26m",
+ "clk13m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "mainpll_d5_d2",
+ "mainpll_d4_d2",
+ "mainpll_d7",
+ "mainpll_d4",
+ "univpll_d6",
+ "ulposc1_ck1",
+ "ulposc1_d4",
+ "ulposc1_d2"
+};
+
+static const char * const asm_h_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "univpll_d6_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const asm_l_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "univpll_d6_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const apll1_parents[] = {
+ "clk26m",
+ "apll1_d4"
+};
+
+static const char * const apll2_parents[] = {
+ "clk26m",
+ "apll2_d4"
+};
+
+static const char * const apll3_parents[] = {
+ "clk26m",
+ "apll3_d4"
+};
+
+static const char * const apll4_parents[] = {
+ "clk26m",
+ "apll4_d4"
+};
+
+static const char * const apll5_parents[] = {
+ "clk26m",
+ "apll5_d4"
+};
+
+static const char * const i2so1_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const i2so2_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const i2si1_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const i2si2_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const dptx_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const aud_iec_parents[] = {
+ "clk26m",
+ "apll1",
+ "apll2",
+ "apll3",
+ "apll4",
+ "apll5"
+};
+
+static const char * const a1sys_hp_parents[] = {
+ "clk26m",
+ "apll1_d4"
+};
+
+static const char * const a2sys_parents[] = {
+ "clk26m",
+ "apll2_d4"
+};
+
+static const char * const a3sys_parents[] = {
+ "clk26m",
+ "apll3_d4",
+ "apll4_d4",
+ "apll5_d4"
+};
+
+static const char * const a4sys_parents[] = {
+ "clk26m",
+ "apll3_d4",
+ "apll4_d4",
+ "apll5_d4"
+};
+
+static const char * const ecc_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d5_d2",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "univpll_d6"
+};
+
+static const char * const spinor_parents[] = {
+ "clk26m",
+ "clk13m",
+ "mainpll_d7_d8",
+ "univpll_d6_d8"
+};
+
+static const char * const ulposc_parents[] = {
+ "ulposc_ck1",
+ "ethpll_d2",
+ "mainpll_d4_d2",
+ "ethpll_d10"
+};
+
+static const char * const srck_parents[] = {
+ "ulposc1_d10",
+ "clk26m"
+};
+
+static const char * const mfg_fast_ref_parents[] = {
+ "top_mfg_core_tmp",
+ "mfgpll_ck"
+};
+
+static const struct mtk_mux top_mtk_muxes[] = {
+ /*
+ * CLK_CFG_0
+ * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
+ * spm_sel and scp_sel are main clocks in always-on co-processor.
+ */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
+ 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
+ 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
+ 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
+ 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, CLK_IS_CRITICAL),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
+ vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
+ ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
+ ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
+ cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
+ ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
+ ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
+ img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
+ camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
+ dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
+ dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
+ dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
+ dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
+ dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
+ dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
+ dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
+ dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
+ mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
+ camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
+ camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
+ camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23),
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
+ uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
+ spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
+ msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
+ msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
+ msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
+ msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
+ intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
+ aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
+ audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
+ pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
+ atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
+ sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
+ dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
+ edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
+ dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
+ disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
+ disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
+ usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
+ ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
+ usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11),
+ /* CLK_CFG_11 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
+ ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
+ usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
+ ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
+ i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15),
+ /* CLK_CFG_12 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
+ seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
+ seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
+ gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
+ venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19),
+ /*
+ * CLK_CFG_13
+ * top_mcupm is main clock in co-processor, should not be handled by Linux.
+ */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
+ vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
+ pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
+ 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
+ spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
+ /*
+ * CLK_CFG_14
+ * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux.
+ */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
+ spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
+ 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
+ tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
+ aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27),
+ /* CLK_CFG_15 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
+ dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
+ wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
+ hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
+ hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31),
+ /* CLK_CFG_16 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
+ hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
+ snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
+ snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
+ snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
+ /* CLK_CFG_17 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
+ adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
+ audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
+ asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
+ asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7),
+ /* CLK_CFG_18 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
+ apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
+ apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
+ apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
+ apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11),
+ /* CLK_CFG_19 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
+ apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
+ i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
+ i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
+ i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15),
+ /* CLK_CFG_20 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
+ i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
+ dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
+ aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
+ a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19),
+ /* CLK_CFG_21 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
+ a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
+ a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
+ a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
+ ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
+ /*
+ * CLK_CFG_22
+ * top_ulposc/top_srck are clock source of always on co-processor,
+ * should not be closed by Linux.
+ */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
+ spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
+ 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
+ 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_composite top_adj_divs[] = {
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),
+};
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x238,
+ .clr_ofs = 0x238,
+ .sta_ofs = 0x238,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x250,
+ .clr_ofs = 0x250,
+ .sta_ofs = 0x250,
+};
+
+#define GATE_TOP0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_TOP1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0),
+ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1),
+ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2),
+ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3),
+ GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
+ GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5),
+ GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6),
+ GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7),
+ GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8),
+ GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9),
+ GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15),
+ GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
+};
+
+static const struct of_device_id of_match_clk_mt8188_topck[] = {
+ { .compatible = "mediatek,mt8188-topckgen", },
+ {}
+};
+
+/* Register mux notifier for MFG mux */
+static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
+{
+ struct mtk_mux_nb *mfg_mux_nb;
+
+ mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
+ if (!mfg_mux_nb)
+ return -ENOMEM;
+
+ mfg_mux_nb->ops = &clk_mux_ops;
+ mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
+
+ return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
+}
+
+static int clk_mt8188_topck_probe(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *top_clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw *hw;
+ int r;
+ void __iomem *base;
+
+ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ if (!top_clk_data)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ r = PTR_ERR(base);
+ goto free_top_data;
+ }
+
+ r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ top_clk_data);
+ if (r)
+ goto free_top_data;
+
+ r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+ if (r)
+ goto unregister_fixed_clks;
+
+ r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
+ &mt8188_clk_lock, top_clk_data);
+ if (r)
+ goto unregister_factors;
+
+ hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents,
+ ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT,
+ (base + 0x250), 8, 1, 0, &mt8188_clk_lock);
+ if (IS_ERR(hw)) {
+ r = PTR_ERR(hw);
+ goto unregister_muxes;
+ }
+ top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
+
+ r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev,
+ top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
+ if (r)
+ goto unregister_muxes;
+
+ r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt8188_clk_lock, top_clk_data);
+ if (r)
+ goto unregister_muxes;
+
+ r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
+ if (r)
+ goto unregister_composite_divs;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, top_clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
+unregister_composite_divs:
+ mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
+unregister_muxes:
+ mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
+unregister_factors:
+ mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+unregister_fixed_clks:
+ mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
+free_top_data:
+ mtk_free_clk_data(top_clk_data);
+ return r;
+}
+
+static int clk_mt8188_topck_remove(struct platform_device *pdev)
+{
+ struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
+ mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
+ mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
+ mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+ mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
+ mtk_free_clk_data(top_clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_topck_drv = {
+ .probe = clk_mt8188_topck_probe,
+ .remove = clk_mt8188_topck_remove,
+ .driver = {
+ .name = "clk-mt8188-topck",
+ .of_match_table = of_match_clk_mt8188_topck,
+ },
+};
+builtin_platform_driver(clk_mt8188_topck_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen clock support
2023-01-19 12:48 ` [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen " Garmin.Chang
@ 2023-02-03 6:43 ` Chen-Yu Tsai
2023-03-09 5:35 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:43 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:53 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 topckgen clock controller which provides muxes, dividers
> to handle variety clock selection in other IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-topckgen.c | 1352 ++++++++++++++++++++
> 2 files changed, 1353 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-topckgen.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 13ab8deb362c..89b1b331cad0 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -83,7 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
> clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
> clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
> -obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> new file mode 100644
> index 000000000000..dd0014b461ff
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> @@ -0,0 +1,1352 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +static DEFINE_SPINLOCK(mt8188_clk_lock);
> +
> +static const struct mtk_fixed_clk top_fixed_clks[] = {
> + FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
> + FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000),
> + FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
> + FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000),
> + FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
> + FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
> +};
> +
> +static const struct mtk_fixed_factor top_divs[] = {
> + FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
> + FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
Please don't add 1:1 placeholder clocks. They only bloat the clock tree
and do nothing else.
> + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1, 3),
> + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1, 4),
> + FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
> + FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
> + FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
> + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll_ck", 1, 5),
> + FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
> + FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
> + FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
> + FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll_ck", 1, 6),
> + FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
> + FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
> + FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
> + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll_ck", 1, 7),
> + FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
> + FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
> + FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
> + FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll_ck", 1, 9),
> + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
Same here.
> + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3),
> + FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll_ck", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
> + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
> + FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll_ck", 1, 6),
> + FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
> + FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
> + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7),
> + FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll_ck", 1, 13),
> + FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
> + FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
> + FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10),
> + FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
> + FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
> + FACTOR(CLK_TOP_IMGPLL, "imgpll_ck", "imgpll", 1, 1),
Again.
> + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
> + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
> + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
> + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
> + FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
> + FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
> + FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
> + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
Again.
> + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_ck", 1, 4),
> + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
> + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll_ck", 1, 5),
> + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
> + FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
> + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_ck", 1, 6),
> + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
> + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll_ck", 1, 7),
> + FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll_ck", 1, 9),
> + FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
> + FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
> + FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
> + FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
> + FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
> + FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
> + FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
> + FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
> + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
Here too.
> + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
> + FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll_ck", 1, 16),
> + FACTOR(CLK_TOP_ETHPLL, "ethpll_ck", "ethpll", 1, 1),
And this one.
> + FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll_ck", 1, 2),
> + FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll_ck", 1, 4),
> + FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll_ck", 1, 8),
> + FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll_ck", 1, 10),
> + FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
And this one.
> + FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll_ck", 1, 2),
> + FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll_ck", 1, 4),
> + FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll_ck", 1, 8),
> + FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2),
> + FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4),
> + FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8),
> + FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7),
> + FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10),
> + FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16),
> +};
> +
> +static const char * const axi_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d7_d2",
> + "mainpll_d4_d2",
> + "mainpll_d5_d2",
> + "mainpll_d6_d2",
> + "ulposc1_d4"
> +};
> +
> +static const char * const spm_parents[] = {
> + "clk26m",
> + "ulposc1_d10",
> + "mainpll_d7_d4",
> + "clk32k"
> +};
> +
> +static const char * const scp_parents[] = {
> + "clk26m",
> + "univpll_d4",
> + "mainpll_d6",
> + "univpll_d6",
> + "univpll_d4_d2",
> + "mainpll_d4_d2",
> + "univpll_d3",
> + "mainpll_d3"
> +};
> +
> +static const char * const bus_aximem_parents[] = {
> + "clk26m",
> + "mainpll_d7_d2",
> + "mainpll_d4_d2",
> + "mainpll_d5_d2",
> + "mainpll_d6"
> +};
> +
> +static const char * const vpp_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d5_d2",
> + "mmpll_d6_d2",
> + "univpll_d5_d2",
> + "univpll_d4_d2",
> + "mmpll_d4_d2",
> + "mmpll_d7",
> + "univpll_d6",
> + "mainpll_d4",
> + "mmpll_d5",
> + "tvdpll1",
> + "tvdpll2",
> + "univpll_d4",
> + "mmpll_d4"
> +};
> +
> +static const char * const ethdr_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d5_d2",
> + "mmpll_d6_d2",
> + "univpll_d5_d2",
> + "univpll_d4_d2",
> + "mmpll_d4_d2",
> + "mmpll_d7",
> + "univpll_d6",
> + "mainpll_d4",
> + "mmpll_d5_d4",
> + "tvdpll1",
> + "tvdpll2",
> + "univpll_d4",
> + "mmpll_d4"
> +};
> +
> +static const char * const ipe_parents[] = {
> + "clk26m",
> + "imgpll_ck",
> + "mainpll_d4",
> + "mmpll_d6",
> + "univpll_d6",
> + "mainpll_d6",
> + "mmpll_d4_d2",
> + "univpll_d4_d2",
> + "mainpll_d4_d2",
> + "mmpll_d6_d2",
> + "univpll_d5_d2",
> + "mainpll_d7"
> +};
> +
> +static const char * const cam_parents[] = {
> + "clk26m",
> + "tvdpll1",
> + "mainpll_d4",
> + "mmpll_d4",
> + "univpll_d4",
> + "univpll_d5",
> + "univpll_d6",
> + "mmpll_d7",
> + "univpll_d4_d2",
> + "mainpll_d4_d2",
> + "imgpll_ck"
> +};
> +
> +static const char * const ccu_parents[] = {
> + "clk26m",
> + "univpll_d6",
> + "mainpll_d4_d2",
> + "mainpll_d4",
> + "univpll_d5",
> + "mainpll_d6",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d4_d2",
> + "univpll_d7"
> +};
> +
> +static const char * const ccu_ahb_parents[] = {
> + "clk26m",
> + "univpll_d6",
> + "mainpll_d4_d2",
> + "mainpll_d4",
> + "univpll_d5",
> + "mainpll_d6",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d4_d2",
> + "univpll_d7"
> +};
This looks like it is the same as ccu_parents. Please reuse it. Add
a comment saying "ccu_parents is also used for ccu_ahb clock" if it helps.
> +
> +static const char * const img_parents[] = {
> + "clk26m",
> + "imgpll_ck",
> + "univpll_d4",
> + "mainpll_d4",
> + "univpll_d5",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d6",
> + "mainpll_d6",
> + "mmpll_d4_d2",
> + "univpll_d4_d2",
> + "mainpll_d4_d2",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const camtm_parents[] = {
> + "clk26m",
> + "univpll_d4_d4",
> + "univpll_d6_d2",
> + "univpll_d6_d4"
> +};
> +
> +static const char * const dsp_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d4_d2",
> + "univpll_d5",
> + "univpll_d4",
> + "mmpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp1_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d4_d2",
> + "univpll_d5",
> + "mmpll_d5",
> + "univpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp2_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d4_d2",
> + "univpll_d5",
> + "mmpll_d5",
> + "univpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp3_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d4_d2",
> + "univpll_d5",
> + "mmpll_d5",
> + "univpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp4_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d4_d2",
> + "mainpll_d4",
> + "univpll_d4",
> + "mmpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp5_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d4_d2",
> + "mainpll_d4",
> + "univpll_d4",
> + "mmpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp6_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d4_d2",
> + "mainpll_d4",
> + "univpll_d4",
> + "mmpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const dsp7_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d4_d2",
> + "univpll_d5",
> + "univpll_d4",
> + "mmpll_d4",
> + "mainpll_d3",
> + "univpll_d3"
> +};
These dsp*_parents all look very similar. From what I can tell there
are two variants. Please merge them. You could name them dspX_Y_Z_parents
or something. Maybe add a comment just above them stating that the
dsp* clocks have two variants.
> +
> +static const char * const mfg_core_tmp_parents[] = {
> + "clk26m",
> + "mainpll_d5_d2",
> + "univpll_d6",
> + "univpll_d7"
> +};
> +
> +static const char * const camtg_parents[] = {
> + "clk26m",
> + "univpll_192m_d8",
> + "univpll_d6_d8",
> + "univpll_192m_d4",
> + "univpll_192m_d10",
> + "clk13m",
> + "univpll_192m_d16",
> + "univpll_192m_d32"
> +};
> +
> +static const char * const camtg2_parents[] = {
> + "clk26m",
> + "univpll_192m_d8",
> + "univpll_d6_d8",
> + "univpll_192m_d4",
> + "univpll_192m_d10",
> + "clk13m",
> + "univpll_192m_d16",
> + "univpll_192m_d32"
> +};
> +
> +static const char * const camtg3_parents[] = {
> + "clk26m",
> + "univpll_192m_d8",
> + "univpll_d6_d8",
> + "univpll_192m_d4",
> + "univpll_192m_d10",
> + "clk13m",
> + "univpll_192m_d16",
> + "univpll_192m_d32"
> +};
Please merge the three into one.
> +static const char * const uart_parents[] = {
> + "clk26m",
> + "univpll_d6_d8"
> +};
> +
> +static const char * const spi_parents[] = {
> + "clk26m",
> + "mainpll_d5_d4",
> + "mainpll_d6_d4",
> + "univpll_d6_d4",
> + "univpll_d6_d2",
> + "mainpll_d6_d2",
> + "mainpll_d4_d4",
> + "univpll_d5_d4"
> +};
> +
> +static const char * const msdc5hclk_parents[] = {
> + "clk26m",
> + "mainpll_d4_d2",
> + "mainpll_d6_d2"
> +};
> +
> +static const char * const msdc50_0_parents[] = {
> + "clk26m",
> + "msdcpll_ck",
> + "msdcpll_d2",
> + "univpll_d4_d4",
> + "mainpll_d6_d2",
> + "univpll_d4_d2"
> +};
> +
> +static const char * const msdc30_1_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d6_d2",
> + "mainpll_d7_d2",
> + "msdcpll_d2"
> +};
> +
> +static const char * const msdc30_2_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "mainpll_d6_d2",
> + "mainpll_d7_d2",
> + "msdcpll_d2"
> +};
Merge the two.
> +static const char * const intdir_parents[] = {
> + "clk26m",
> + "univpll_d6",
> + "mainpll_d4",
> + "univpll_d4"
> +};
> +
> +static const char * const aud_intbus_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d7_d4"
> +};
> +
> +static const char * const audio_h_parents[] = {
> + "clk26m",
> + "univpll_d7",
> + "apll1",
> + "apll2"
> +};
> +
> +static const char * const pwrap_ulposc_parents[] = {
> + "clk26m",
> + "ulposc1_d10",
> + "ulposc1_d7",
> + "ulposc1_d8",
> + "ulposc1_d16",
> + "mainpll_d4_d8",
> + "univpll_d5_d8",
> + "tvdpll1_d16"
> +};
> +
> +static const char * const atb_parents[] = {
> + "clk26m",
> + "mainpll_d4_d2",
> + "mainpll_d5_d2"
> +};
> +
> +static const char * const sspm_parents[] = {
> + "clk26m",
> + "mainpll_d7_d2",
> + "mainpll_d6_d2",
> + "mainpll_d5_d2",
> + "mainpll_d9",
> + "mainpll_d4_d2"
> +};
> +
> +static const char * const dp_parents[] = {
> + "clk26m",
> + "tvdpll1_d2",
> + "tvdpll2_d2",
> + "tvdpll1_d4",
> + "tvdpll2_d4",
> + "tvdpll1_d8",
> + "tvdpll2_d8",
> + "tvdpll1_d16",
> + "tvdpll2_d16"
> +};
> +
> +static const char * const edp_parents[] = {
> + "clk26m",
> + "tvdpll1_d2",
> + "tvdpll2_d2",
> + "tvdpll1_d4",
> + "tvdpll2_d4",
> + "tvdpll1_d8",
> + "tvdpll2_d8",
> + "tvdpll1_d16",
> + "tvdpll2_d16"
> +};
> +
> +static const char * const dpi_parents[] = {
> + "clk26m",
> + "tvdpll1_d2",
> + "tvdpll2_d2",
> + "tvdpll1_d4",
> + "tvdpll2_d4",
> + "tvdpll1_d8",
> + "tvdpll2_d8",
> + "tvdpll1_d16",
> + "tvdpll2_d16"
> +};
Merge the three.
> +static const char * const disp_pwm0_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "ulposc1_d2",
> + "ulposc1_d4",
> + "ulposc1_d16",
> + "ethpll_d4"
> +};
> +
> +static const char * const disp_pwm1_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "ulposc1_d2",
> + "ulposc1_d4",
> + "ulposc1_d16"
> +};
You could merge the two, and add a comment saying that pwm1 doesn't have
the last clock. Later below in the clock definition, for pwm1 just have
ARRAY_SIZE() - 1 for num_parents.
This one is up to you though. It's trading amount of code for complexity.
> +static const char * const usb_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const usb_2p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_2p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const usb_3p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const ssusb_xhci_3p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d6_d4",
> + "univpll_d5_d2"
> +};
These are all the same. Please merge them. Maybe call them usb_parents?
> +static const char * const i2c_parents[] = {
> + "clk26m",
> + "mainpll_d4_d8",
> + "univpll_d5_d4"
> +};
> +
> +static const char * const seninf_parents[] = {
> + "clk26m",
> + "univpll_d4_d4",
> + "univpll_d6_d2",
> + "mainpll_d4_d2",
> + "univpll_d7",
> + "univpll_d6",
> + "mmpll_d6",
> + "univpll_d5"
> +};
> +
> +static const char * const seninf1_parents[] = {
> + "clk26m",
> + "univpll_d4_d4",
> + "univpll_d6_d2",
> + "mainpll_d4_d2",
> + "univpll_d7",
> + "univpll_d6",
> + "mmpll_d6",
> + "univpll_d5"
> +};
These two are the same. Please merge.
> +static const char * const gcpu_parents[] = {
> + "clk26m",
> + "mainpll_d6",
> + "univpll_d4_d2",
> + "mmpll_d5_d2",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const venc_parents[] = {
> + "clk26m",
> + "mmpll_d4_d2",
> + "mainpll_d6",
> + "univpll_d4_d2",
> + "mainpll_d4_d2",
> + "univpll_d6",
> + "mmpll_d6",
> + "mainpll_d5_d2",
> + "mainpll_d6_d2",
> + "mmpll_d9",
> + "univpll_d4_d4",
> + "mainpll_d4",
> + "univpll_d4",
> + "univpll_d5",
> + "univpll_d5_d2",
> + "mainpll_d5"
> +};
> +
> +static const char * const vdec_parents[] = {
> + "clk26m",
> + "mainpll_d5_d2",
> + "mmpll_d6_d2",
> + "univpll_d5_d2",
> + "univpll_d4_d2",
> + "mmpll_d4_d2",
> + "univpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mmpll_d6",
> + "mainpll_d4",
> + "tvdpll2",
> + "univpll_d4",
> + "imgpll_ck",
> + "univpll_d6_d2",
> + "mmpll_d9"
> +};
> +
> +static const char * const pwm_parents[] = {
> + "clk32k",
> + "clk26m",
> + "univpll_d4_d8",
> + "univpll_d6_d4"
> +};
> +
> +static const char * const mcupm_parents[] = {
> + "clk26m",
> + "mainpll_d6_d2",
> + "mainpll_d7_d4"
> +};
> +
> +static const char * const spmi_p_mst_parents[] = {
> + "clk26m",
> + "clk13m",
> + "ulposc1_d8",
> + "ulposc1_d10",
> + "ulposc1_d16",
> + "ulposc1_d7",
> + "clk32k",
> + "mainpll_d7_d8",
> + "mainpll_d6_d8",
> + "mainpll_d5_d8"
> +};
> +
> +static const char * const spmi_m_mst_parents[] = {
> + "clk26m",
> + "clk13m",
> + "ulposc1_d8",
> + "ulposc1_d10",
> + "ulposc1_d16",
> + "ulposc1_d7",
> + "clk32k",
> + "mainpll_d7_d8",
> + "mainpll_d6_d8",
> + "mainpll_d5_d8"
> +};
Merge these two.
> +static const char * const dvfsrc_parents[] = {
> + "clk26m",
> + "ulposc1_d10",
> + "univpll_d6_d8",
> + "msdcpll_d16"
> +};
> +
> +static const char * const tl_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "mainpll_d4_d4"
> +};
> +
> +static const char * const aes_msdcfde_parents[] = {
> + "clk26m",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "mainpll_d4_d4",
> + "univpll_d4_d2",
> + "univpll_d6"
> +};
> +
> +static const char * const dsi_occ_parents[] = {
> + "clk26m",
> + "univpll_d6_d2",
> + "univpll_d5_d2",
> + "univpll_d4_d2"
> +};
> +
> +static const char * const wpe_vpp_parents[] = {
> + "clk26m",
> + "mainpll_d5_d2",
> + "mmpll_d6_d2",
> + "univpll_d5_d2",
> + "mainpll_d4_d2",
> + "univpll_d4_d2",
> + "mmpll_d4_d2",
> + "mainpll_d6",
> + "mmpll_d7",
> + "univpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mainpll_d4",
> + "tvdpll1",
> + "univpll_d4"
> +};
> +
> +static const char * const hdcp_parents[] = {
> + "clk26m",
> + "univpll_d4_d8",
> + "mainpll_d5_d8",
> + "univpll_d6_d4"
> +};
> +
> +static const char * const hdcp_24m_parents[] = {
> + "clk26m",
> + "univpll_192m_d4",
> + "univpll_192m_d8",
> + "univpll_d6_d8"
> +};
> +
> +static const char * const hdmi_apb_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "msdcpll_d2"
> +};
> +
> +static const char * const snps_eth_250m_parents[] = {
> + "clk26m",
> + "ethpll_d2"
> +};
> +
> +static const char * const snps_eth_62p4m_ptp_parents[] = {
> + "apll2_d3",
> + "apll1_d3",
> + "clk26m",
> + "ethpll_d8"
> +};
> +
> +static const char * const snps_eth_50m_rmii_parents[] = {
> + "clk26m",
> + "ethpll_d10"
> +};
> +
> +static const char * const adsp_parents[] = {
> + "clk26m",
> + "clk13m",
> + "mainpll_d6",
> + "mainpll_d5_d2",
> + "univpll_d4_d4",
> + "univpll_d4",
> + "ulposc1_d2",
> + "ulposc1_ck1",
> + "adsppll_ck",
> + "adsppll_d2",
> + "adsppll_d4",
> + "adsppll_d8"
> +};
> +
> +static const char * const audio_local_bus_parents[] = {
> + "clk26m",
> + "clk13m",
> + "mainpll_d4_d4",
> + "mainpll_d7_d2",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d7",
> + "mainpll_d4",
> + "univpll_d6",
> + "ulposc1_ck1",
> + "ulposc1_d4",
> + "ulposc1_d2"
> +};
> +
> +static const char * const asm_h_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "univpll_d6_d2",
> + "mainpll_d5_d2"
> +};
> +
> +static const char * const asm_l_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "univpll_d6_d2",
> + "mainpll_d5_d2"
> +};
> +
> +static const char * const apll1_parents[] = {
> + "clk26m",
> + "apll1_d4"
> +};
> +
> +static const char * const apll2_parents[] = {
> + "clk26m",
> + "apll2_d4"
> +};
> +
> +static const char * const apll3_parents[] = {
> + "clk26m",
> + "apll3_d4"
> +};
> +
> +static const char * const apll4_parents[] = {
> + "clk26m",
> + "apll4_d4"
> +};
> +
> +static const char * const apll5_parents[] = {
> + "clk26m",
> + "apll5_d4"
> +};
> +
> +static const char * const i2so1_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
> +
> +static const char * const i2so2_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
> +
> +static const char * const i2si1_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
> +
> +static const char * const i2si2_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
> +
> +static const char * const dptx_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
> +
> +static const char * const aud_iec_parents[] = {
> + "clk26m",
> + "apll1",
> + "apll2",
> + "apll3",
> + "apll4",
> + "apll5"
> +};
Please merge all these. Maybe call them something like aud_if?
> +static const char * const a1sys_hp_parents[] = {
> + "clk26m",
> + "apll1_d4"
> +};
> +
> +static const char * const a2sys_parents[] = {
> + "clk26m",
> + "apll2_d4"
> +};
> +
> +static const char * const a3sys_parents[] = {
> + "clk26m",
> + "apll3_d4",
> + "apll4_d4",
> + "apll5_d4"
> +};
> +
> +static const char * const a4sys_parents[] = {
> + "clk26m",
> + "apll3_d4",
> + "apll4_d4",
> + "apll5_d4"
> +};
Please merge the two.
> +static const char * const ecc_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "univpll_d6"
> +};
> +
> +static const char * const spinor_parents[] = {
> + "clk26m",
> + "clk13m",
> + "mainpll_d7_d8",
> + "univpll_d6_d8"
> +};
> +
> +static const char * const ulposc_parents[] = {
> + "ulposc_ck1",
> + "ethpll_d2",
> + "mainpll_d4_d2",
> + "ethpll_d10"
> +};
> +
> +static const char * const srck_parents[] = {
> + "ulposc1_d10",
> + "clk26m"
> +};
> +
> +static const char * const mfg_fast_ref_parents[] = {
> + "top_mfg_core_tmp",
> + "mfgpll_ck"
> +};
> +
> +static const struct mtk_mux top_mtk_muxes[] = {
> + /*
> + * CLK_CFG_0
> + * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
> + * spm_sel and scp_sel are main clocks in always-on co-processor.
> + */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
> + 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
> + 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
> + 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
> + 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, CLK_IS_CRITICAL),
> + /* CLK_CFG_1 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
> + vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
> + ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
> + ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
> + cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
> + /* CLK_CFG_2 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
> + ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
> + ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
> + img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
> + camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11),
> + /* CLK_CFG_3 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
> + dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
> + dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
> + dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
> + dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15),
> + /* CLK_CFG_4 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
> + dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
> + dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
> + dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
> + dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
> + /* CLK_CFG_5 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
> + mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
> + camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
> + camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
> + camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23),
> + /* CLK_CFG_6 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
> + uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
> + spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
> + msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
> + msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27),
> + /* CLK_CFG_7 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
> + msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
> + msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
> + intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
> + aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31),
> + /* CLK_CFG_8 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
> + audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
> + pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
> + atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
> + sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
> + /* CLK_CFG_9 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
> + dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
> + edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
> + dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
> + disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
> + /* CLK_CFG_10 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
> + disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
> + usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
> + ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
> + usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11),
> + /* CLK_CFG_11 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
> + ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
> + usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
> + ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
> + i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15),
> + /* CLK_CFG_12 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
> + seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
> + seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
> + gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
> + venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19),
> + /*
> + * CLK_CFG_13
> + * top_mcupm is main clock in co-processor, should not be handled by Linux.
> + */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
> + vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
> + pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
> + 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
> + spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
> + /*
> + * CLK_CFG_14
> + * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux.
> + */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
> + spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
> + 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
> + tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
> + aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27),
> + /* CLK_CFG_15 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
> + dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
> + wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
> + hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
> + hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31),
> + /* CLK_CFG_16 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
> + hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
> + snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
> + snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
> + snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
> + /* CLK_CFG_17 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
> + adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
> + audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
> + asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
> + asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7),
> + /* CLK_CFG_18 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
> + apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
> + apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
> + apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
> + apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11),
> + /* CLK_CFG_19 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
> + apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
> + i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
> + i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
> + i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15),
> + /* CLK_CFG_20 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
> + i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
> + dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
> + aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
> + a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19),
> + /* CLK_CFG_21 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
> + a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
> + a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
> + a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
> + ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
> + /*
> + * CLK_CFG_22
> + * top_ulposc/top_srck are clock source of always on co-processor,
> + * should not be closed by Linux.
> + */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
> + spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
> + 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
> + 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, CLK_IS_CRITICAL),
> +};
> +
> +static const struct mtk_composite top_adj_divs[] = {
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
> + DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),
> +};
> +static const struct mtk_gate_regs top0_cg_regs = {
> + .set_ofs = 0x238,
> + .clr_ofs = 0x238,
> + .sta_ofs = 0x238,
> +};
> +
> +static const struct mtk_gate_regs top1_cg_regs = {
> + .set_ofs = 0x250,
> + .clr_ofs = 0x250,
> + .sta_ofs = 0x250,
> +};
> +
> +#define GATE_TOP0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_TOP1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate top_clks[] = {
> + /* TOP0 */
> + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0),
> + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1),
> + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2),
> + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3),
> + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
> + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5),
> + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6),
> + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7),
> + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8),
> + GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9),
> + GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15),
> + GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18),
> + /* TOP1 */
> + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
> + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
> + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2),
> + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
> + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4),
> + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
> + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6),
> + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_topck[] = {
> + { .compatible = "mediatek,mt8188-topckgen", },
> + {}
> +};
> +
> +/* Register mux notifier for MFG mux */
> +static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
> +{
> + struct mtk_mux_nb *mfg_mux_nb;
> +
> + mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
> + if (!mfg_mux_nb)
> + return -ENOMEM;
> +
> + mfg_mux_nb->ops = &clk_mux_ops;
> + mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
> +
> + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
> +}
> +
> +static int clk_mt8188_topck_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *top_clk_data;
> + struct device_node *node = pdev->dev.of_node;
> + struct clk_hw *hw;
> + int r;
> + void __iomem *base;
> +
> + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> + if (!top_clk_data)
> + return -ENOMEM;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base)) {
> + r = PTR_ERR(base);
> + goto free_top_data;
> + }
> +
> + r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> + top_clk_data);
> + if (r)
> + goto free_top_data;
> +
> + r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> + if (r)
> + goto unregister_fixed_clks;
> +
> + r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
> + &mt8188_clk_lock, top_clk_data);
> + if (r)
> + goto unregister_factors;
> +
> + hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents,
> + ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT,
> + (base + 0x250), 8, 1, 0, &mt8188_clk_lock);
> + if (IS_ERR(hw)) {
> + r = PTR_ERR(hw);
> + goto unregister_muxes;
> + }
> + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
> +
> + r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev,
> + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
> + if (r)
> + goto unregister_muxes;
> +
> + r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
> + &mt8188_clk_lock, top_clk_data);
> + if (r)
> + goto unregister_muxes;
> +
> + r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> + if (r)
> + goto unregister_composite_divs;
> +
> + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
> + if (r)
> + goto unregister_gates;
> +
> + platform_set_drvdata(pdev, top_clk_data);
> +
> + return r;
> +
> +unregister_gates:
> + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> +unregister_composite_divs:
> + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
> +unregister_muxes:
> + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
> +unregister_factors:
> + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> +unregister_fixed_clks:
> + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
> +free_top_data:
> + mtk_free_clk_data(top_clk_data);
> + return r;
> +}
> +
> +static int clk_mt8188_topck_remove(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
> + struct device_node *node = pdev->dev.of_node;
> +
> + of_clk_del_provider(node);
> + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
> + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
> + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
> + mtk_free_clk_data(top_clk_data);
> +
> + return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_topck_drv = {
> + .probe = clk_mt8188_topck_probe,
> + .remove = clk_mt8188_topck_remove,
With the recently merged cleanup and refactor, you can use the expanded
simple probe library for this. Please see clk-mt8192.c in latest -next.
Thanks
ChenYu
> + .driver = {
> + .name = "clk-mt8188-topck",
> + .of_match_table = of_match_clk_mt8188_topck,
> + },
> +};
> +builtin_platform_driver(clk_mt8188_topck_drv);
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen clock support
2023-02-03 6:43 ` Chen-Yu Tsai
@ 2023-03-09 5:35 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:35 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 14:43 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:53 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 topckgen clock controller which provides muxes, dividers
> > to handle variety clock selection in other IP blocks.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-topckgen.c | 1352
> > ++++++++++++++++++++
> > 2 files changed, 1353 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-topckgen.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 13ab8deb362c..89b1b331cad0 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -83,7 +83,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > clk-mt8186-mfg.o clk-mt8186-mm.o
> > clk-mt8186-wpe.o \
> > clk-mt8186-img.o clk-mt8186-
> > vdec.o clk-mt8186-venc.o \
> > clk-mt8186-cam.o clk-mt8186-
> > mdp.o clk-mt8186-ipe.o
> > -obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> > +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > new file mode 100644
> > index 000000000000..dd0014b461ff
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > @@ -0,0 +1,1352 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +#include "clk-mux.h"
> > +
> > +static DEFINE_SPINLOCK(mt8188_clk_lock);
> > +
> > +static const struct mtk_fixed_clk top_fixed_clks[] = {
> > + FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
> > + FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck",
> > NULL, 49152000),
> > + FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
> > + FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL,
> > 533000000),
> > + FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL,
> > 250000000),
> > + FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
> > +};
> > +
> > +static const struct mtk_fixed_factor top_divs[] = {
> > + FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
> > + FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
>
> Please don't add 1:1 placeholder clocks. They only bloat the clock
> tree
> and do nothing else.
Thank you for your suggestions.
OK, I will remove all 1:1 placeholder clocks in v6.
>
> > + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1,
> > 3),
> > + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1,
> > 4),
> > + FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2",
> > "mainpll_d4", 1, 2),
> > + FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4",
> > "mainpll_d4", 1, 4),
> > + FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8",
> > "mainpll_d4", 1, 8),
> > + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll_ck", 1,
> > 5),
> > + FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2",
> > "mainpll_d5", 1, 2),
> > + FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4",
> > "mainpll_d5", 1, 4),
> > + FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8",
> > "mainpll_d5", 1, 8),
> > + FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll_ck", 1,
> > 6),
> > + FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2",
> > "mainpll_d6", 1, 2),
> > + FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4",
> > "mainpll_d6", 1, 4),
> > + FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8",
> > "mainpll_d6", 1, 8),
> > + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll_ck", 1,
> > 7),
> > + FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2",
> > "mainpll_d7", 1, 2),
> > + FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4",
> > "mainpll_d7", 1, 4),
> > + FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8",
> > "mainpll_d7", 1, 8),
> > + FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll_ck", 1,
> > 9),
> > + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
>
> Same here.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
> > 2),
> > + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
> > 3),
> > + FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll_ck", 1,
> > 4),
> > + FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2",
> > "univpll_d4", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4",
> > "univpll_d4", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8",
> > "univpll_d4", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
> > 5),
> > + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2",
> > "univpll_d5", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4",
> > "univpll_d5", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8",
> > "univpll_d5", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll_ck", 1,
> > 6),
> > + FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2",
> > "univpll_d6", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4",
> > "univpll_d6", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8",
> > "univpll_d6", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
> > 7),
> > + FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll_ck",
> > 1, 13),
> > + FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4",
> > "univpll_192m", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8",
> > "univpll_192m", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10",
> > "univpll_192m", 1, 10),
> > + FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16",
> > "univpll_192m", 1, 16),
> > + FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32",
> > "univpll_192m", 1, 32),
> > + FACTOR(CLK_TOP_IMGPLL, "imgpll_ck", "imgpll", 1, 1),
>
> Again.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
> > + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
> > + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
> > + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
> > + FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
> > + FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
> > + FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
> > + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
>
> Again.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
> > 2),
> > + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll_ck", 1, 5),
> > + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
> > 2),
> > + FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
> > 4),
> > + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_ck", 1, 6),
> > + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1,
> > 2),
> > + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll_ck", 1, 7),
> > + FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll_ck", 1, 9),
> > + FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
> > + FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
> > + FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
> > + FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1,
> > 16),
> > + FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
> > + FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
> > + FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
> > + FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1,
> > 16),
> > + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
>
> Here too.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
> > 2),
> > + FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll_ck", 1,
> > 16),
> > + FACTOR(CLK_TOP_ETHPLL, "ethpll_ck", "ethpll", 1, 1),
>
> And this one.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll_ck", 1, 8),
> > + FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll_ck", 1,
> > 10),
> > + FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
>
> And this one.
OK, I will remove it in v6.
>
> > + FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll_ck", 1,
> > 2),
> > + FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll_ck", 1,
> > 4),
> > + FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll_ck", 1,
> > 8),
> > + FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1,
> > 2),
> > + FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1,
> > 4),
> > + FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1,
> > 8),
> > + FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1,
> > 7),
> > + FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1,
> > 10),
> > + FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1,
> > 16),
> > +};
> > +
> > +static const char * const axi_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d4",
> > + "mainpll_d7_d2",
> > + "mainpll_d4_d2",
> > + "mainpll_d5_d2",
> > + "mainpll_d6_d2",
> > + "ulposc1_d4"
> > +};
> > +
> > +static const char * const spm_parents[] = {
> > + "clk26m",
> > + "ulposc1_d10",
> > + "mainpll_d7_d4",
> > + "clk32k"
> > +};
> > +
> > +static const char * const scp_parents[] = {
> > + "clk26m",
> > + "univpll_d4",
> > + "mainpll_d6",
> > + "univpll_d6",
> > + "univpll_d4_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d3",
> > + "mainpll_d3"
> > +};
> > +
> > +static const char * const bus_aximem_parents[] = {
> > + "clk26m",
> > + "mainpll_d7_d2",
> > + "mainpll_d4_d2",
> > + "mainpll_d5_d2",
> > + "mainpll_d6"
> > +};
> > +
> > +static const char * const vpp_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d5_d2",
> > + "mmpll_d6_d2",
> > + "univpll_d5_d2",
> > + "univpll_d4_d2",
> > + "mmpll_d4_d2",
> > + "mmpll_d7",
> > + "univpll_d6",
> > + "mainpll_d4",
> > + "mmpll_d5",
> > + "tvdpll1",
> > + "tvdpll2",
> > + "univpll_d4",
> > + "mmpll_d4"
> > +};
> > +
> > +static const char * const ethdr_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d5_d2",
> > + "mmpll_d6_d2",
> > + "univpll_d5_d2",
> > + "univpll_d4_d2",
> > + "mmpll_d4_d2",
> > + "mmpll_d7",
> > + "univpll_d6",
> > + "mainpll_d4",
> > + "mmpll_d5_d4",
> > + "tvdpll1",
> > + "tvdpll2",
> > + "univpll_d4",
> > + "mmpll_d4"
> > +};
> > +
> > +static const char * const ipe_parents[] = {
> > + "clk26m",
> > + "imgpll_ck",
> > + "mainpll_d4",
> > + "mmpll_d6",
> > + "univpll_d6",
> > + "mainpll_d6",
> > + "mmpll_d4_d2",
> > + "univpll_d4_d2",
> > + "mainpll_d4_d2",
> > + "mmpll_d6_d2",
> > + "univpll_d5_d2",
> > + "mainpll_d7"
> > +};
> > +
> > +static const char * const cam_parents[] = {
> > + "clk26m",
> > + "tvdpll1",
> > + "mainpll_d4",
> > + "mmpll_d4",
> > + "univpll_d4",
> > + "univpll_d5",
> > + "univpll_d6",
> > + "mmpll_d7",
> > + "univpll_d4_d2",
> > + "mainpll_d4_d2",
> > + "imgpll_ck"
> > +};
> > +
> > +static const char * const ccu_parents[] = {
> > + "clk26m",
> > + "univpll_d6",
> > + "mainpll_d4_d2",
> > + "mainpll_d4",
> > + "univpll_d5",
> > + "mainpll_d6",
> > + "mmpll_d6",
> > + "mmpll_d7",
> > + "univpll_d4_d2",
> > + "univpll_d7"
> > +};
> > +
> > +static const char * const ccu_ahb_parents[] = {
> > + "clk26m",
> > + "univpll_d6",
> > + "mainpll_d4_d2",
> > + "mainpll_d4",
> > + "univpll_d5",
> > + "mainpll_d6",
> > + "mmpll_d6",
> > + "mmpll_d7",
> > + "univpll_d4_d2",
> > + "univpll_d7"
> > +};
>
> This looks like it is the same as ccu_parents. Please reuse it. Add
> a comment saying "ccu_parents is also used for ccu_ahb clock" if it
> helps.
>
> > +
> > +static const char * const img_parents[] = {
> > + "clk26m",
> > + "imgpll_ck",
> > + "univpll_d4",
> > + "mainpll_d4",
> > + "univpll_d5",
> > + "mmpll_d6",
> > + "mmpll_d7",
> > + "univpll_d6",
> > + "mainpll_d6",
> > + "mmpll_d4_d2",
> > + "univpll_d4_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const camtm_parents[] = {
> > + "clk26m",
> > + "univpll_d4_d4",
> > + "univpll_d6_d2",
> > + "univpll_d6_d4"
> > +};
> > +
> > +static const char * const dsp_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d4_d2",
> > + "univpll_d5",
> > + "univpll_d4",
> > + "mmpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp1_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d5",
> > + "mmpll_d5",
> > + "univpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp2_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d5",
> > + "mmpll_d5",
> > + "univpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp3_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d5",
> > + "mmpll_d5",
> > + "univpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp4_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d4_d2",
> > + "mainpll_d4",
> > + "univpll_d4",
> > + "mmpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp5_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d4_d2",
> > + "mainpll_d4",
> > + "univpll_d4",
> > + "mmpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp6_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d4_d2",
> > + "mainpll_d4",
> > + "univpll_d4",
> > + "mmpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
> > +
> > +static const char * const dsp7_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d4_d2",
> > + "univpll_d5",
> > + "univpll_d4",
> > + "mmpll_d4",
> > + "mainpll_d3",
> > + "univpll_d3"
> > +};
>
> These dsp*_parents all look very similar. From what I can tell there
> are two variants. Please merge them. You could name them
> dspX_Y_Z_parents
> or something. Maybe add a comment just above them stating that the
> dsp* clocks have two variants.
>
> > +
> > +static const char * const mfg_core_tmp_parents[] = {
> > + "clk26m",
> > + "mainpll_d5_d2",
> > + "univpll_d6",
> > + "univpll_d7"
> > +};
> > +
> > +static const char * const camtg_parents[] = {
> > + "clk26m",
> > + "univpll_192m_d8",
> > + "univpll_d6_d8",
> > + "univpll_192m_d4",
> > + "univpll_192m_d10",
> > + "clk13m",
> > + "univpll_192m_d16",
> > + "univpll_192m_d32"
> > +};
> > +
> > +static const char * const camtg2_parents[] = {
> > + "clk26m",
> > + "univpll_192m_d8",
> > + "univpll_d6_d8",
> > + "univpll_192m_d4",
> > + "univpll_192m_d10",
> > + "clk13m",
> > + "univpll_192m_d16",
> > + "univpll_192m_d32"
> > +};
> > +
> > +static const char * const camtg3_parents[] = {
> > + "clk26m",
> > + "univpll_192m_d8",
> > + "univpll_d6_d8",
> > + "univpll_192m_d4",
> > + "univpll_192m_d10",
> > + "clk13m",
> > + "univpll_192m_d16",
> > + "univpll_192m_d32"
> > +};
>
> Please merge the three into one.
>
> > +static const char * const uart_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d8"
> > +};
> > +
> > +static const char * const spi_parents[] = {
> > + "clk26m",
> > + "mainpll_d5_d4",
> > + "mainpll_d6_d4",
> > + "univpll_d6_d4",
> > + "univpll_d6_d2",
> > + "mainpll_d6_d2",
> > + "mainpll_d4_d4",
> > + "univpll_d5_d4"
> > +};
> > +
> > +static const char * const msdc5hclk_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d2",
> > + "mainpll_d6_d2"
> > +};
> > +
> > +static const char * const msdc50_0_parents[] = {
> > + "clk26m",
> > + "msdcpll_ck",
> > + "msdcpll_d2",
> > + "univpll_d4_d4",
> > + "mainpll_d6_d2",
> > + "univpll_d4_d2"
> > +};
> > +
> > +static const char * const msdc30_1_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d6_d2",
> > + "mainpll_d7_d2",
> > + "msdcpll_d2"
> > +};
> > +
> > +static const char * const msdc30_2_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "mainpll_d6_d2",
> > + "mainpll_d7_d2",
> > + "msdcpll_d2"
> > +};
>
> Merge the two.
>
> > +static const char * const intdir_parents[] = {
> > + "clk26m",
> > + "univpll_d6",
> > + "mainpll_d4",
> > + "univpll_d4"
> > +};
> > +
> > +static const char * const aud_intbus_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d4",
> > + "mainpll_d7_d4"
> > +};
> > +
> > +static const char * const audio_h_parents[] = {
> > + "clk26m",
> > + "univpll_d7",
> > + "apll1",
> > + "apll2"
> > +};
> > +
> > +static const char * const pwrap_ulposc_parents[] = {
> > + "clk26m",
> > + "ulposc1_d10",
> > + "ulposc1_d7",
> > + "ulposc1_d8",
> > + "ulposc1_d16",
> > + "mainpll_d4_d8",
> > + "univpll_d5_d8",
> > + "tvdpll1_d16"
> > +};
> > +
> > +static const char * const atb_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d2",
> > + "mainpll_d5_d2"
> > +};
> > +
> > +static const char * const sspm_parents[] = {
> > + "clk26m",
> > + "mainpll_d7_d2",
> > + "mainpll_d6_d2",
> > + "mainpll_d5_d2",
> > + "mainpll_d9",
> > + "mainpll_d4_d2"
> > +};
> > +
> > +static const char * const dp_parents[] = {
> > + "clk26m",
> > + "tvdpll1_d2",
> > + "tvdpll2_d2",
> > + "tvdpll1_d4",
> > + "tvdpll2_d4",
> > + "tvdpll1_d8",
> > + "tvdpll2_d8",
> > + "tvdpll1_d16",
> > + "tvdpll2_d16"
> > +};
> > +
> > +static const char * const edp_parents[] = {
> > + "clk26m",
> > + "tvdpll1_d2",
> > + "tvdpll2_d2",
> > + "tvdpll1_d4",
> > + "tvdpll2_d4",
> > + "tvdpll1_d8",
> > + "tvdpll2_d8",
> > + "tvdpll1_d16",
> > + "tvdpll2_d16"
> > +};
> > +
> > +static const char * const dpi_parents[] = {
> > + "clk26m",
> > + "tvdpll1_d2",
> > + "tvdpll2_d2",
> > + "tvdpll1_d4",
> > + "tvdpll2_d4",
> > + "tvdpll1_d8",
> > + "tvdpll2_d8",
> > + "tvdpll1_d16",
> > + "tvdpll2_d16"
> > +};
>
> Merge the three.
>
> > +static const char * const disp_pwm0_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d4",
> > + "ulposc1_d2",
> > + "ulposc1_d4",
> > + "ulposc1_d16",
> > + "ethpll_d4"
> > +};
> > +
> > +static const char * const disp_pwm1_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d4",
> > + "ulposc1_d2",
> > + "ulposc1_d4",
> > + "ulposc1_d16"
> > +};
>
> You could merge the two, and add a comment saying that pwm1 doesn't
> have
> the last clock. Later below in the clock definition, for pwm1 just
> have
> ARRAY_SIZE() - 1 for num_parents.
>
> This one is up to you though. It's trading amount of code for
> complexity.
>
> > +static const char * const usb_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const ssusb_xhci_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const usb_2p_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const ssusb_xhci_2p_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const usb_3p_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const ssusb_xhci_3p_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "univpll_d6_d4",
> > + "univpll_d5_d2"
> > +};
>
> These are all the same. Please merge them. Maybe call them
> usb_parents?
>
> > +static const char * const i2c_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d8",
> > + "univpll_d5_d4"
> > +};
> > +
> > +static const char * const seninf_parents[] = {
> > + "clk26m",
> > + "univpll_d4_d4",
> > + "univpll_d6_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d7",
> > + "univpll_d6",
> > + "mmpll_d6",
> > + "univpll_d5"
> > +};
> > +
> > +static const char * const seninf1_parents[] = {
> > + "clk26m",
> > + "univpll_d4_d4",
> > + "univpll_d6_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d7",
> > + "univpll_d6",
> > + "mmpll_d6",
> > + "univpll_d5"
> > +};
>
> These two are the same. Please merge.
>
> > +static const char * const gcpu_parents[] = {
> > + "clk26m",
> > + "mainpll_d6",
> > + "univpll_d4_d2",
> > + "mmpll_d5_d2",
> > + "univpll_d5_d2"
> > +};
> > +
> > +static const char * const venc_parents[] = {
> > + "clk26m",
> > + "mmpll_d4_d2",
> > + "mainpll_d6",
> > + "univpll_d4_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d6",
> > + "mmpll_d6",
> > + "mainpll_d5_d2",
> > + "mainpll_d6_d2",
> > + "mmpll_d9",
> > + "univpll_d4_d4",
> > + "mainpll_d4",
> > + "univpll_d4",
> > + "univpll_d5",
> > + "univpll_d5_d2",
> > + "mainpll_d5"
> > +};
> > +
> > +static const char * const vdec_parents[] = {
> > + "clk26m",
> > + "mainpll_d5_d2",
> > + "mmpll_d6_d2",
> > + "univpll_d5_d2",
> > + "univpll_d4_d2",
> > + "mmpll_d4_d2",
> > + "univpll_d6",
> > + "mainpll_d5",
> > + "univpll_d5",
> > + "mmpll_d6",
> > + "mainpll_d4",
> > + "tvdpll2",
> > + "univpll_d4",
> > + "imgpll_ck",
> > + "univpll_d6_d2",
> > + "mmpll_d9"
> > +};
> > +
> > +static const char * const pwm_parents[] = {
> > + "clk32k",
> > + "clk26m",
> > + "univpll_d4_d8",
> > + "univpll_d6_d4"
> > +};
> > +
> > +static const char * const mcupm_parents[] = {
> > + "clk26m",
> > + "mainpll_d6_d2",
> > + "mainpll_d7_d4"
> > +};
> > +
> > +static const char * const spmi_p_mst_parents[] = {
> > + "clk26m",
> > + "clk13m",
> > + "ulposc1_d8",
> > + "ulposc1_d10",
> > + "ulposc1_d16",
> > + "ulposc1_d7",
> > + "clk32k",
> > + "mainpll_d7_d8",
> > + "mainpll_d6_d8",
> > + "mainpll_d5_d8"
> > +};
> > +
> > +static const char * const spmi_m_mst_parents[] = {
> > + "clk26m",
> > + "clk13m",
> > + "ulposc1_d8",
> > + "ulposc1_d10",
> > + "ulposc1_d16",
> > + "ulposc1_d7",
> > + "clk32k",
> > + "mainpll_d7_d8",
> > + "mainpll_d6_d8",
> > + "mainpll_d5_d8"
> > +};
>
> Merge these two.
>
> > +static const char * const dvfsrc_parents[] = {
> > + "clk26m",
> > + "ulposc1_d10",
> > + "univpll_d6_d8",
> > + "msdcpll_d16"
> > +};
> > +
> > +static const char * const tl_parents[] = {
> > + "clk26m",
> > + "univpll_d5_d4",
> > + "mainpll_d4_d4"
> > +};
> > +
> > +static const char * const aes_msdcfde_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d2",
> > + "mainpll_d6",
> > + "mainpll_d4_d4",
> > + "univpll_d4_d2",
> > + "univpll_d6"
> > +};
> > +
> > +static const char * const dsi_occ_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d2",
> > + "univpll_d5_d2",
> > + "univpll_d4_d2"
> > +};
> > +
> > +static const char * const wpe_vpp_parents[] = {
> > + "clk26m",
> > + "mainpll_d5_d2",
> > + "mmpll_d6_d2",
> > + "univpll_d5_d2",
> > + "mainpll_d4_d2",
> > + "univpll_d4_d2",
> > + "mmpll_d4_d2",
> > + "mainpll_d6",
> > + "mmpll_d7",
> > + "univpll_d6",
> > + "mainpll_d5",
> > + "univpll_d5",
> > + "mainpll_d4",
> > + "tvdpll1",
> > + "univpll_d4"
> > +};
> > +
> > +static const char * const hdcp_parents[] = {
> > + "clk26m",
> > + "univpll_d4_d8",
> > + "mainpll_d5_d8",
> > + "univpll_d6_d4"
> > +};
> > +
> > +static const char * const hdcp_24m_parents[] = {
> > + "clk26m",
> > + "univpll_192m_d4",
> > + "univpll_192m_d8",
> > + "univpll_d6_d8"
> > +};
> > +
> > +static const char * const hdmi_apb_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d4",
> > + "msdcpll_d2"
> > +};
> > +
> > +static const char * const snps_eth_250m_parents[] = {
> > + "clk26m",
> > + "ethpll_d2"
> > +};
> > +
> > +static const char * const snps_eth_62p4m_ptp_parents[] = {
> > + "apll2_d3",
> > + "apll1_d3",
> > + "clk26m",
> > + "ethpll_d8"
> > +};
> > +
> > +static const char * const snps_eth_50m_rmii_parents[] = {
> > + "clk26m",
> > + "ethpll_d10"
> > +};
> > +
> > +static const char * const adsp_parents[] = {
> > + "clk26m",
> > + "clk13m",
> > + "mainpll_d6",
> > + "mainpll_d5_d2",
> > + "univpll_d4_d4",
> > + "univpll_d4",
> > + "ulposc1_d2",
> > + "ulposc1_ck1",
> > + "adsppll_ck",
> > + "adsppll_d2",
> > + "adsppll_d4",
> > + "adsppll_d8"
> > +};
> > +
> > +static const char * const audio_local_bus_parents[] = {
> > + "clk26m",
> > + "clk13m",
> > + "mainpll_d4_d4",
> > + "mainpll_d7_d2",
> > + "mainpll_d5_d2",
> > + "mainpll_d4_d2",
> > + "mainpll_d7",
> > + "mainpll_d4",
> > + "univpll_d6",
> > + "ulposc1_ck1",
> > + "ulposc1_d4",
> > + "ulposc1_d2"
> > +};
> > +
> > +static const char * const asm_h_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d4",
> > + "univpll_d6_d2",
> > + "mainpll_d5_d2"
> > +};
> > +
> > +static const char * const asm_l_parents[] = {
> > + "clk26m",
> > + "univpll_d6_d4",
> > + "univpll_d6_d2",
> > + "mainpll_d5_d2"
> > +};
> > +
> > +static const char * const apll1_parents[] = {
> > + "clk26m",
> > + "apll1_d4"
> > +};
> > +
> > +static const char * const apll2_parents[] = {
> > + "clk26m",
> > + "apll2_d4"
> > +};
> > +
> > +static const char * const apll3_parents[] = {
> > + "clk26m",
> > + "apll3_d4"
> > +};
> > +
> > +static const char * const apll4_parents[] = {
> > + "clk26m",
> > + "apll4_d4"
> > +};
> > +
> > +static const char * const apll5_parents[] = {
> > + "clk26m",
> > + "apll5_d4"
> > +};
> > +
> > +static const char * const i2so1_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
> > +
> > +static const char * const i2so2_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
> > +
> > +static const char * const i2si1_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
> > +
> > +static const char * const i2si2_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
> > +
> > +static const char * const dptx_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
> > +
> > +static const char * const aud_iec_parents[] = {
> > + "clk26m",
> > + "apll1",
> > + "apll2",
> > + "apll3",
> > + "apll4",
> > + "apll5"
> > +};
>
> Please merge all these. Maybe call them something like aud_if?
>
> > +static const char * const a1sys_hp_parents[] = {
> > + "clk26m",
> > + "apll1_d4"
> > +};
> > +
> > +static const char * const a2sys_parents[] = {
> > + "clk26m",
> > + "apll2_d4"
> > +};
> > +
> > +static const char * const a3sys_parents[] = {
> > + "clk26m",
> > + "apll3_d4",
> > + "apll4_d4",
> > + "apll5_d4"
> > +};
> > +
> > +static const char * const a4sys_parents[] = {
> > + "clk26m",
> > + "apll3_d4",
> > + "apll4_d4",
> > + "apll5_d4"
> > +};
>
> Please merge the two.
>
> > +static const char * const ecc_parents[] = {
> > + "clk26m",
> > + "mainpll_d4_d4",
> > + "mainpll_d5_d2",
> > + "mainpll_d4_d2",
> > + "mainpll_d6",
> > + "univpll_d6"
> > +};
> > +
> > +static const char * const spinor_parents[] = {
> > + "clk26m",
> > + "clk13m",
> > + "mainpll_d7_d8",
> > + "univpll_d6_d8"
> > +};
> > +
> > +static const char * const ulposc_parents[] = {
> > + "ulposc_ck1",
> > + "ethpll_d2",
> > + "mainpll_d4_d2",
> > + "ethpll_d10"
> > +};
> > +
> > +static const char * const srck_parents[] = {
> > + "ulposc1_d10",
> > + "clk26m"
> > +};
> > +
> > +static const char * const mfg_fast_ref_parents[] = {
> > + "top_mfg_core_tmp",
> > + "mfgpll_ck"
> > +};
> > +
> > +static const struct mtk_mux top_mtk_muxes[] = {
> > + /*
> > + * CLK_CFG_0
> > + * axi_sel and bus_aximem_sel are bus clocks, should not be
> > closed by Linux.
> > + * spm_sel and scp_sel are main clocks in always-on co-
> > processor.
> > + */
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
> > axi_parents,
> > + 0x020, 0x024, 0x028, 0, 4, 7,
> > 0x04, 0, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
> > spm_parents,
> > + 0x020, 0x024, 0x028, 8, 4, 15,
> > 0x04, 1, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
> > scp_parents,
> > + 0x020, 0x024, 0x028, 16, 4, 23,
> > 0x04, 2, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM,
> > "top_bus_aximem", bus_aximem_parents,
> > + 0x020, 0x024, 0x028, 24, 4, 31,
> > 0x04, 3, CLK_IS_CRITICAL),
> > + /* CLK_CFG_1 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
> > + vpp_parents, 0x02C, 0x030, 0x034, 0,
> > 4, 7, 0x04, 4),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
> > + ethdr_parents, 0x02C, 0x030, 0x034, 8,
> > 4, 15, 0x04, 5),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
> > + ipe_parents, 0x02C, 0x030, 0x034, 16,
> > 4, 23, 0x04, 6),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
> > + cam_parents, 0x02C, 0x030, 0x034, 24,
> > 4, 31, 0x04, 7),
> > + /* CLK_CFG_2 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
> > + ccu_parents, 0x038, 0x03C, 0x040, 0,
> > 4, 7, 0x04, 8),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
> > + ccu_ahb_parents, 0x038, 0x03C, 0x040,
> > 8, 4, 15, 0x04, 9),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
> > + img_parents, 0x038, 0x03C, 0x040, 16,
> > 4, 23, 0x04, 10),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
> > + camtm_parents, 0x038, 0x03C, 0x040,
> > 24, 4, 31, 0x04, 11),
> > + /* CLK_CFG_3 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
> > + dsp_parents, 0x044, 0x048, 0x04C, 0,
> > 4, 7, 0x04, 12),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
> > + dsp1_parents, 0x044, 0x048, 0x04C, 8,
> > 4, 15, 0x04, 13),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
> > + dsp2_parents, 0x044, 0x048, 0x04C, 16,
> > 4, 23, 0x04, 14),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
> > + dsp3_parents, 0x044, 0x048, 0x04C, 24,
> > 4, 31, 0x04, 15),
> > + /* CLK_CFG_4 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
> > + dsp4_parents, 0x050, 0x054, 0x058, 0,
> > 4, 7, 0x04, 16),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
> > + dsp5_parents, 0x050, 0x054, 0x058, 8,
> > 4, 15, 0x04, 17),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
> > + dsp6_parents, 0x050, 0x054, 0x058, 16,
> > 4, 23, 0x04, 18),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
> > + dsp7_parents, 0x050, 0x054, 0x058, 24,
> > 4, 31, 0x04, 19),
> > + /* CLK_CFG_5 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP,
> > "top_mfg_core_tmp",
> > + mfg_core_tmp_parents, 0x05C, 0x060,
> > 0x064, 0, 4, 7, 0x04, 20),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
> > + camtg_parents, 0x05C, 0x060, 0x064, 8,
> > 4, 15, 0x04, 21),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
> > + camtg2_parents, 0x05C, 0x060, 0x064,
> > 16, 4, 23, 0x04, 22),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
> > + camtg3_parents, 0x05C, 0x060, 0x064,
> > 24, 4, 31, 0x04, 23),
> > + /* CLK_CFG_6 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
> > + uart_parents, 0x068, 0x06C, 0x070, 0,
> > 4, 7, 0x04, 24),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
> > + spi_parents, 0x068, 0x06C, 0x070, 8,
> > 4, 15, 0x04, 25),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK,
> > "top_msdc5hclk",
> > + msdc5hclk_parents, 0x068, 0x06C,
> > 0x070, 16, 4, 23, 0x04, 26),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
> > + msdc50_0_parents, 0x068, 0x06C, 0x070,
> > 24, 4, 31, 0x04, 27),
> > + /* CLK_CFG_7 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
> > + msdc30_1_parents, 0x074, 0x078, 0x07C,
> > 0, 4, 7, 0x04, 28),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
> > + msdc30_2_parents, 0x074, 0x078, 0x07C,
> > 8, 4, 15, 0x04, 29),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
> > + intdir_parents, 0x074, 0x078, 0x07C,
> > 16, 4, 23, 0x04, 30),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
> > + aud_intbus_parents, 0x074, 0x078,
> > 0x07C, 24, 4, 31, 0x04, 31),
> > + /* CLK_CFG_8 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
> > + audio_h_parents, 0x080, 0x084, 0x088,
> > 0, 4, 7, 0x08, 0),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC,
> > "top_pwrap_ulposc",
> > + pwrap_ulposc_parents, 0x080, 0x084,
> > 0x088, 8, 4, 15, 0x08, 1),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
> > + atb_parents, 0x080, 0x084, 0x088, 16,
> > 4, 23, 0x08, 2),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
> > + sspm_parents, 0x080, 0x084, 0x088, 24,
> > 4, 31, 0x08, 3),
> > + /* CLK_CFG_9 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
> > + dp_parents, 0x08C, 0x090, 0x094, 0, 4,
> > 7, 0x08, 4),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
> > + edp_parents, 0x08C, 0x090, 0x094, 8,
> > 4, 15, 0x08, 5),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
> > + dpi_parents, 0x08C, 0x090, 0x094, 16,
> > 4, 23, 0x08, 6),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
> > + disp_pwm0_parents, 0x08C, 0x090,
> > 0x094, 24, 4, 31, 0x08, 7),
> > + /* CLK_CFG_10 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
> > + disp_pwm1_parents, 0x098, 0x09C,
> > 0x0A0, 0, 4, 7, 0x08, 8),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
> > + usb_parents, 0x098, 0x09C, 0x0A0, 8,
> > 4, 15, 0x08, 9),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
> > + ssusb_xhci_parents, 0x098, 0x09C,
> > 0x0A0, 16, 4, 23, 0x08, 10),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
> > + usb_2p_parents, 0x098, 0x09C, 0x0A0,
> > 24, 4, 31, 0x08, 11),
> > + /* CLK_CFG_11 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P,
> > "top_ssusb_xhci_2p",
> > + ssusb_xhci_2p_parents, 0x0A4, 0x0A8,
> > 0x0AC, 0, 4, 7, 0x08, 12),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
> > + usb_3p_parents, 0x0A4, 0x0A8, 0x0AC,
> > 8, 4, 15, 0x08, 13),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P,
> > "top_ssusb_xhci_3p",
> > + ssusb_xhci_3p_parents, 0x0A4, 0x0A8,
> > 0x0AC, 16, 4, 23, 0x08, 14),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
> > + i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24,
> > 4, 31, 0x08, 15),
> > + /* CLK_CFG_12 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
> > + seninf_parents, 0x0B0, 0x0B4, 0x0B8,
> > 0, 4, 7, 0x08, 16),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
> > + seninf1_parents, 0x0B0, 0x0B4, 0x0B8,
> > 8, 4, 15, 0x08, 17),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
> > + gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16,
> > 4, 23, 0x08, 18),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
> > + venc_parents, 0x0B0, 0x0B4, 0x0B8, 24,
> > 4, 31, 0x08, 19),
> > + /*
> > + * CLK_CFG_13
> > + * top_mcupm is main clock in co-processor, should not be
> > handled by Linux.
> > + */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
> > + vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0,
> > 4, 7, 0x08, 20),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
> > + pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8,
> > 4, 15, 0x08, 21),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
> > mcupm_parents,
> > + 0x0BC, 0x0C0, 0x0C4, 16, 4, 23,
> > 0x08, 22, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
> > + spmi_p_mst_parents, 0x0BC, 0x0C0,
> > 0x0C4, 24, 4, 31, 0x08, 23),
> > + /*
> > + * CLK_CFG_14
> > + * dvfsrc_sel is for internal DVFS usage, should not be
> > handled by Linux.
> > + */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
> > + spmi_m_mst_parents, 0x0C8, 0x0CC,
> > 0x0D0, 0, 4, 7, 0x08, 24),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
> > dvfsrc_parents,
> > + 0x0C8, 0x0CC, 0x0D0, 8, 4, 15,
> > 0x08, 25, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
> > + tl_parents, 0x0C8, 0x0CC, 0x0D0, 16,
> > 4, 23, 0x08, 26),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE,
> > "top_aes_msdcfde",
> > + aes_msdcfde_parents, 0x0C8, 0x0CC,
> > 0x0D0, 24, 4, 31, 0x08, 27),
> > + /* CLK_CFG_15 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
> > + dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC,
> > 0, 4, 7, 0x08, 28),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
> > + wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC,
> > 8, 4, 15, 0x08, 29),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
> > + hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16,
> > 4, 23, 0x08, 30),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
> > + hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC,
> > 24, 4, 31, 0x08, 31),
> > + /* CLK_CFG_16 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
> > + hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8,
> > 0, 4, 7, 0x0C, 0),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M,
> > "top_snps_eth_250m",
> > + snps_eth_250m_parents, 0x0E0, 0x0E4,
> > 0x0E8, 8, 4, 15, 0x0C, 1),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP,
> > "top_snps_eth_62p4m_ptp",
> > + snps_eth_62p4m_ptp_parents, 0x0E0,
> > 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII,
> > "snps_eth_50m_rmii",
> > + snps_eth_50m_rmii_parents, 0x0E0,
> > 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
> > + /* CLK_CFG_17 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
> > + adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0,
> > 4, 7, 0x0C, 4),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS,
> > "top_audio_local_bus",
> > + audio_local_bus_parents, 0x0EC, 0x0F0,
> > 0x0F4, 8, 4, 15, 0x0C, 5),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
> > + asm_h_parents, 0x0EC, 0x0F0, 0x0F4,
> > 16, 4, 23, 0x0C, 6),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
> > + asm_l_parents, 0x0EC, 0x0F0, 0x0F4,
> > 24, 4, 31, 0x0C, 7),
> > + /* CLK_CFG_18 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
> > + apll1_parents, 0x0F8, 0x0FC, 0x100, 0,
> > 4, 7, 0x0C, 8),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
> > + apll2_parents, 0x0F8, 0x0FC, 0x100, 8,
> > 4, 15, 0x0C, 9),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
> > + apll3_parents, 0x0F8, 0x0FC, 0x100,
> > 16, 4, 23, 0x0C, 10),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
> > + apll4_parents, 0x0F8, 0x0FC, 0x100,
> > 24, 4, 31, 0x0C, 11),
> > + /* CLK_CFG_19 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
> > + apll5_parents, 0x0104, 0x0108, 0x010C,
> > 0, 4, 7, 0x0C, 12),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
> > + i2so1_parents, 0x0104, 0x0108, 0x010C,
> > 8, 4, 15, 0x0C, 13),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
> > + i2so2_parents, 0x0104, 0x0108, 0x010C,
> > 16, 4, 23, 0x0C, 14),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
> > + i2si1_parents, 0x0104, 0x0108, 0x010C,
> > 24, 4, 31, 0x0C, 15),
> > + /* CLK_CFG_20 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
> > + i2si2_parents, 0x0110, 0x0114, 0x0118,
> > 0, 4, 7, 0x0C, 16),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
> > + dptx_parents, 0x0110, 0x0114, 0x0118,
> > 8, 4, 15, 0x0C, 17),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
> > + aud_iec_parents, 0x0110, 0x0114,
> > 0x0118, 16, 4, 23, 0x0C, 18),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
> > + a1sys_hp_parents, 0x0110, 0x0114,
> > 0x0118, 24, 4, 31, 0x0C, 19),
> > + /* CLK_CFG_21 */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
> > + a2sys_parents, 0x011C, 0x0120, 0x0124,
> > 0, 4, 7, 0x0C, 20),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
> > + a3sys_parents, 0x011C, 0x0120, 0x0124,
> > 8, 4, 15, 0x0C, 21),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
> > + a4sys_parents, 0x011C, 0x0120, 0x0124,
> > 16, 4, 23, 0x0C, 22),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
> > + ecc_parents, 0x011C, 0x0120, 0x0124,
> > 24, 4, 31, 0x0C, 23),
> > + /*
> > + * CLK_CFG_22
> > + * top_ulposc/top_srck are clock source of always on co-
> > processor,
> > + * should not be closed by Linux.
> > + */
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
> > + spinor_parents, 0x0128, 0x012C,
> > 0x0130, 0, 4, 7, 0x0C, 24),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
> > ulposc_parents,
> > + 0x0128, 0x012C, 0x0130, 8, 4,
> > 15, 0x0C, 25, CLK_IS_CRITICAL),
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
> > srck_parents,
> > + 0x0128, 0x012C, 0x0130, 16, 4,
> > 23, 0x0C, 26, CLK_IS_CRITICAL),
> > +};
> > +
> > +static const struct mtk_composite top_adj_divs[] = {
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0",
> > "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1",
> > "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2",
> > "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3",
> > "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4",
> > "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
> > + DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx",
> > 0x0320, 9, 0x0338, 8, 8),
> > +};
> > +static const struct mtk_gate_regs top0_cg_regs = {
> > + .set_ofs = 0x238,
> > + .clr_ofs = 0x238,
> > + .sta_ofs = 0x238,
> > +};
> > +
> > +static const struct mtk_gate_regs top1_cg_regs = {
> > + .set_ofs = 0x250,
> > + .clr_ofs = 0x250,
> > + .sta_ofs = 0x250,
> > +};
> > +
> > +#define GATE_TOP0(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr_inv)
> > +
> > +#define GATE_TOP1(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift,
> > &mtk_clk_gate_ops_no_setclr_inv)
> > +
> > +static const struct mtk_gate top_clks[] = {
> > + /* TOP0 */
> > + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0,
> > "cfgreg_clock_vpp0", "top_vpp", 0),
> > + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1,
> > "cfgreg_clock_vpp1", "top_vpp", 1),
> > + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0,
> > "cfgreg_clock_vdo0", "top_vpp", 2),
> > + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1,
> > "cfgreg_clock_vdo1", "top_vpp", 3),
> > + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS,
> > "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
> > + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0",
> > "clk26m", 5),
> > + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1",
> > "clk26m", 6),
> > + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0",
> > "clk26m", 7),
> > + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1",
> > "clk26m", 8),
> > + GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD,
> > "cfgreg_aud_f26m_aud", "clk26m", 9),
> > + GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses",
> > "univpll_d2", 15),
> > + GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF,
> > "cfgreg_f_pcie_phy_ref", "clk26m", 18),
> > + /* TOP1 */
> > + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
> > + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m",
> > 1),
> > + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref",
> > "clk26m", 2),
> > + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref",
> > "clk26m", 3),
> > + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref",
> > "clk26m", 4),
> > + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref",
> > "clk26m", 5),
> > + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref",
> > "clk26m", 6),
> > + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref",
> > "clk26m", 7),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_topck[] = {
> > + { .compatible = "mediatek,mt8188-topckgen", },
> > + {}
> > +};
> > +
> > +/* Register mux notifier for MFG mux */
> > +static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev,
> > struct clk *clk)
> > +{
> > + struct mtk_mux_nb *mfg_mux_nb;
> > +
> > + mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb),
> > GFP_KERNEL);
> > + if (!mfg_mux_nb)
> > + return -ENOMEM;
> > +
> > + mfg_mux_nb->ops = &clk_mux_ops;
> > + mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP
> > */
> > +
> > + return devm_mtk_clk_mux_notifier_register(dev, clk,
> > mfg_mux_nb);
> > +}
> > +
> > +static int clk_mt8188_topck_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *top_clk_data;
> > + struct device_node *node = pdev->dev.of_node;
> > + struct clk_hw *hw;
> > + int r;
> > + void __iomem *base;
> > +
> > + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> > + if (!top_clk_data)
> > + return -ENOMEM;
> > +
> > + base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(base)) {
> > + r = PTR_ERR(base);
> > + goto free_top_data;
> > + }
> > +
> > + r = mtk_clk_register_fixed_clks(top_fixed_clks,
> > ARRAY_SIZE(top_fixed_clks),
> > + top_clk_data);
> > + if (r)
> > + goto free_top_data;
> > +
> > + r = mtk_clk_register_factors(top_divs,
> > ARRAY_SIZE(top_divs), top_clk_data);
> > + if (r)
> > + goto unregister_fixed_clks;
> > +
> > + r = mtk_clk_register_muxes(top_mtk_muxes,
> > ARRAY_SIZE(top_mtk_muxes), node,
> > + &mt8188_clk_lock, top_clk_data);
> > + if (r)
> > + goto unregister_factors;
> > +
> > + hw = devm_clk_hw_register_mux(&pdev->dev,
> > "mfg_ck_fast_ref", mfg_fast_ref_parents,
> > + ARRAY_SIZE(mfg_fast_ref_paren
> > ts), CLK_SET_RATE_PARENT,
> > + (base + 0x250), 8, 1, 0,
> > &mt8188_clk_lock);
> > + if (IS_ERR(hw)) {
> > + r = PTR_ERR(hw);
> > + goto unregister_muxes;
> > + }
> > + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
> > +
> > + r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev,
> > + top_clk_data-
> > >hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
> > + if (r)
> > + goto unregister_muxes;
> > +
> > + r = mtk_clk_register_composites(top_adj_divs,
> > ARRAY_SIZE(top_adj_divs), base,
> > + &mt8188_clk_lock,
> > top_clk_data);
> > + if (r)
> > + goto unregister_muxes;
> > +
> > + r = mtk_clk_register_gates(node, top_clks,
> > ARRAY_SIZE(top_clks), top_clk_data);
> > + if (r)
> > + goto unregister_composite_divs;
> > +
> > + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
> > top_clk_data);
> > + if (r)
> > + goto unregister_gates;
> > +
> > + platform_set_drvdata(pdev, top_clk_data);
> > +
> > + return r;
> > +
> > +unregister_gates:
> > + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks),
> > top_clk_data);
> > +unregister_composite_divs:
> > + mtk_clk_unregister_composites(top_adj_divs,
> > ARRAY_SIZE(top_adj_divs), top_clk_data);
> > +unregister_muxes:
> > + mtk_clk_unregister_muxes(top_mtk_muxes,
> > ARRAY_SIZE(top_mtk_muxes), top_clk_data);
> > +unregister_factors:
> > + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs),
> > top_clk_data);
> > +unregister_fixed_clks:
> > + mtk_clk_unregister_fixed_clks(top_fixed_clks,
> > ARRAY_SIZE(top_fixed_clks), top_clk_data);
> > +free_top_data:
> > + mtk_free_clk_data(top_clk_data);
> > + return r;
> > +}
> > +
> > +static int clk_mt8188_topck_remove(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *top_clk_data =
> > platform_get_drvdata(pdev);
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + of_clk_del_provider(node);
> > + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks),
> > top_clk_data);
> > + mtk_clk_unregister_composites(top_adj_divs,
> > ARRAY_SIZE(top_adj_divs), top_clk_data);
> > + mtk_clk_unregister_muxes(top_mtk_muxes,
> > ARRAY_SIZE(top_mtk_muxes), top_clk_data);
> > + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs),
> > top_clk_data);
> > + mtk_clk_unregister_fixed_clks(top_fixed_clks,
> > ARRAY_SIZE(top_fixed_clks), top_clk_data);
> > + mtk_free_clk_data(top_clk_data);
> > +
> > + return 0;
> > +}
> > +
> > +static struct platform_driver clk_mt8188_topck_drv = {
> > + .probe = clk_mt8188_topck_probe,
> > + .remove = clk_mt8188_topck_remove,
>
> With the recently merged cleanup and refactor, you can use the
> expanded
> simple probe library for this. Please see clk-mt8192.c in latest
> -next.
>
>
> Thanks
> ChenYu
>
> > + .driver = {
> > + .name = "clk-mt8188-topck",
> > + .of_match_table = of_match_clk_mt8188_topck,
> > + },
> > +};
> > +builtin_platform_driver(clk_mt8188_topck_drv);
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (2 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 03/19] clk: mediatek: Add MT8188 topckgen " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:45 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure " Garmin.Chang
` (15 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 peripheral clock controller which provides clock
gate control for ethernet/flashif/pcie/ssusb.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8188-peri_ao.c | 56 +++++++++++++++++++++++
2 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-peri_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 89b1b331cad0..b8a3042f4809 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -83,7 +83,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
-obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
+ clk-mt8188-peri_ao.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-peri_ao.c b/drivers/clk/mediatek/clk-mt8188-peri_ao.c
new file mode 100644
index 000000000000..683010453a10
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-peri_ao.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs peri_ao_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x18,
+};
+
+#define GATE_PERI_AO(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate peri_ao_clks[] = {
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0),
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1),
+ GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3),
+ GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, "peri_ao_flashif_26m", "clk26m", 4),
+ GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, "peri_ao_flashiflashck", "top_spinor", 5),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_BUS, "peri_ao_ssusb_bus", "top_usb_top", 13),
+ GATE_PERI_AO(CLK_PERI_AO_SSUSB_XHCI, "peri_ao_ssusb_xhci", "top_ssusb_xhci", 14),
+ GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac_clk", "top_snps_eth_250m", 16),
+ GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_FMEM, "peri_ao_pcie_p0_fmem", "hd_466m_fmem_ck", 24),
+};
+
+static const struct mtk_clk_desc peri_ao_desc = {
+ .clks = peri_ao_clks,
+ .num_clks = ARRAY_SIZE(peri_ao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_peri_ao[] = {
+ { .compatible = "mediatek,mt8188-pericfg-ao", .data = &peri_ao_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_peri_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-peri_ao",
+ .of_match_table = of_match_clk_mt8188_peri_ao,
+ },
+};
+builtin_platform_driver(clk_mt8188_peri_ao_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral clock support
2023-01-19 12:48 ` [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral " Garmin.Chang
@ 2023-02-03 6:45 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:45 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:51 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 peripheral clock controller which provides clock
> gate control for ethernet/flashif/pcie/ssusb.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (3 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 04/19] clk: mediatek: Add MT8188 peripheral " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:48 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys " Garmin.Chang
` (14 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-infra_ao.c | 196 +++++++++++++++++++++
2 files changed, 197 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-infra_ao.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b8a3042f4809..a3393782f7e1 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -84,7 +84,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
- clk-mt8188-peri_ao.o
+ clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c
new file mode 100644
index 000000000000..edc0ba18c67f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs infra_ao0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra_ao1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra_ao2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra_ao3_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra_ao4_cg_regs = {
+ .set_ofs = 0xe0,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe8,
+};
+
+#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \
+ GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate infra_ao_clks[] = {
+ /* INFRA_AO0 */
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
+ /* infra_ao_sej is main clock is for secure engine with JTAG support */
+ GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
+ GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
+ GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8),
+ GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9),
+ GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
+ GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26),
+ GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
+ GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28),
+ GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
+ /* INFRA_AO1 */
+ GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
+ GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6),
+ /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */
+ GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc",
+ "clk26m", 7, CLK_IS_CRITICAL),
+ GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
+ GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13),
+ GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15),
+ GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16),
+ GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17),
+ GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18),
+ /* infra_ao_dapc is for device access permission control module */
+ GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc",
+ "top_axi", 20, CLK_IS_CRITICAL),
+ GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24),
+ GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
+ GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29),
+ GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
+ /* INFRA_AO2 */
+ GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0),
+ GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2),
+ GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
+ GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
+ GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm",
+ "top_sspm", 15, CLK_IS_CRITICAL),
+ GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk",
+ "top_axi", 17, CLK_IS_CRITICAL),
+ GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
+ GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
+ GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
+ /* INFRA_AO3 */
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2),
+ GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5),
+ GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8),
+ GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9),
+ GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10),
+ GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15),
+ GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16),
+ GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17),
+ GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20),
+ GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24),
+ /* infra_ao_dapc_sync is for device access permission control module */
+ GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync",
+ "top_axi", 25, CLK_IS_CRITICAL),
+ GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26),
+ /* INFRA_AO4 */
+ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */
+ GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set",
+ "top_axi", 0, CLK_IS_CRITICAL),
+ GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set",
+ "top_axi", 1, CLK_IS_CRITICAL),
+ GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0",
+ "pextp_pipe", 7),
+ GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P,
+ "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18),
+};
+
+static const struct mtk_clk_desc infra_ao_desc = {
+ .clks = infra_ao_clks,
+ .num_clks = ARRAY_SIZE(infra_ao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {
+ { .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_infra_ao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-infra_ao",
+ .of_match_table = of_match_clk_mt8188_infra_ao,
+ },
+};
+builtin_platform_driver(clk_mt8188_infra_ao_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure clock support
2023-01-19 12:48 ` [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure " Garmin.Chang
@ 2023-02-03 6:48 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:48 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:51 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 infrastructure clock controller which provides
> clock gate control for basic IP like pwm, uart, spi and so on.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (4 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 05/19] clk: mediatek: Add MT8188 infrastructure " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:53 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys " Garmin.Chang
` (13 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 camsys clock controllers which provide clock gate
control for camera IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8188-cam.c | 118 ++++++++++++++++++++++++++
2 files changed, 120 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-cam.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a3393782f7e1..dc247bf67e8b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -84,7 +84,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
- clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o
+ clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
+ clk-mt8188-cam.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-cam.c b/drivers/clk/mediatek/clk-mt8188-cam.c
new file mode 100644
index 000000000000..5f7cf9db12f2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-cam.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs cam_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate cam_main_clks[] = {
+ GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0),
+ GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1),
+ GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 2),
+ GATE_CAM(CLK_CAM_MAIN_CAM_SUBA, "cam_main_cam_suba", "top_cam", 3),
+ GATE_CAM(CLK_CAM_MAIN_CAM_SUBB, "cam_main_cam_subb", "top_cam", 4),
+ GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 7),
+ GATE_CAM(CLK_CAM_MAIN_SENINF, "cam_main_seninf", "top_cam", 8),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVA, "cam_main_gcamsva", "top_cam", 9),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVB, "cam_main_gcamsvb", "top_cam", 10),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVC, "cam_main_gcamsvc", "top_cam", 11),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVD, "cam_main_gcamsvd", "top_cam", 12),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVE, "cam_main_gcamsve", "top_cam", 13),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVF, "cam_main_gcamsvf", "top_cam", 14),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVG, "cam_main_gcamsvg", "top_cam", 15),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVH, "cam_main_gcamsvh", "top_cam", 16),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVI, "cam_main_gcamsvi", "top_cam", 17),
+ GATE_CAM(CLK_CAM_MAIN_GCAMSVJ, "cam_main_gcamsvj", "top_cam", 18),
+ GATE_CAM(CLK_CAM_MAIN_CAMSV_TOP, "cam_main_camsv", "top_cam", 19),
+ GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_A, "cam_main_camsv_cq_a", "top_cam", 20),
+ GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_B, "cam_main_camsv_cq_b", "top_cam", 21),
+ GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_C, "cam_main_camsv_cq_c", "top_cam", 22),
+ GATE_CAM(CLK_CAM_MAIN_FAKE_ENG, "cam_main_fake_eng", "top_cam", 28),
+ GATE_CAM(CLK_CAM_MAIN_CAM2MM0_GALS, "cam_main_cam2mm0_gals", "top_cam", 29),
+ GATE_CAM(CLK_CAM_MAIN_CAM2MM1_GALS, "cam_main_cam2mm1_gals", "top_cam", 30),
+ GATE_CAM(CLK_CAM_MAIN_CAM2SYS_GALS, "cam_main_cam2sys_gals", "top_cam", 31),
+};
+
+static const struct mtk_gate cam_rawa_clks[] = {
+ GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0),
+ GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1),
+ GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2),
+};
+
+static const struct mtk_gate cam_rawb_clks[] = {
+ GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0),
+ GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1),
+ GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2),
+};
+
+static const struct mtk_gate cam_yuva_clks[] = {
+ GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0),
+ GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1),
+ GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2),
+};
+
+static const struct mtk_gate cam_yuvb_clks[] = {
+ GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0),
+ GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1),
+ GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
+};
+
+static const struct mtk_clk_desc cam_main_desc = {
+ .clks = cam_main_clks,
+ .num_clks = ARRAY_SIZE(cam_main_clks),
+};
+
+static const struct mtk_clk_desc cam_rawa_desc = {
+ .clks = cam_rawa_clks,
+ .num_clks = ARRAY_SIZE(cam_rawa_clks),
+};
+
+static const struct mtk_clk_desc cam_rawb_desc = {
+ .clks = cam_rawb_clks,
+ .num_clks = ARRAY_SIZE(cam_rawb_clks),
+};
+
+static const struct mtk_clk_desc cam_yuva_desc = {
+ .clks = cam_yuva_clks,
+ .num_clks = ARRAY_SIZE(cam_yuva_clks),
+};
+
+static const struct mtk_clk_desc cam_yuvb_desc = {
+ .clks = cam_yuvb_clks,
+ .num_clks = ARRAY_SIZE(cam_yuvb_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_cam[] = {
+ { .compatible = "mediatek,mt8188-camsys", .data = &cam_main_desc },
+ { .compatible = "mediatek,mt8188-camsys-rawa", .data = &cam_rawa_desc },
+ { .compatible = "mediatek,mt8188-camsys-rawb", .data = &cam_rawb_desc },
+ { .compatible = "mediatek,mt8188-camsys-yuva", .data = &cam_yuva_desc },
+ { .compatible = "mediatek,mt8188-camsys-yuvb", .data = &cam_yuvb_desc },
+ { /* sentinel */}
+};
+
+static struct platform_driver clk_mt8188_cam_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-cam",
+ .of_match_table = of_match_clk_mt8188_cam,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_cam_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys clock support
2023-01-19 12:48 ` [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys " Garmin.Chang
@ 2023-02-03 6:53 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:53 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 camsys clock controllers which provide clock gate
> control for camera IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (5 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 06/19] clk: mediatek: Add MT8188 camsys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:55 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys " Garmin.Chang
` (12 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 ccusys clock controller which provides clock gate
control in Camera Computing Unit.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-ccu.c | 48 +++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-ccu.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index dc247bf67e8b..dbd140b81763 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
- clk-mt8188-cam.o
+ clk-mt8188-cam.o clk-mt8188-ccu.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c
new file mode 100644
index 000000000000..b7380060f906
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-ccu.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ccu_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_CCU(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ccu_clks[] = {
+ GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0),
+ GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
+ GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
+};
+
+static const struct mtk_clk_desc ccu_desc = {
+ .clks = ccu_clks,
+ .num_clks = ARRAY_SIZE(ccu_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_ccu[] = {
+ { .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc},
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_ccu_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-ccu",
+ .of_match_table = of_match_clk_mt8188_ccu,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_ccu_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys clock support
2023-01-19 12:48 ` [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys " Garmin.Chang
@ 2023-02-03 6:55 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:55 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 ccusys clock controller which provides clock gate
> control in Camera Computing Unit.
If this is also for camera related functions, could you fold this into
the previous CAM clock driver? That would save a bit of space.
The code looks OK.
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-ccu.c | 48 +++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-ccu.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index dc247bf67e8b..dbd140b81763 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> - clk-mt8188-cam.o
> + clk-mt8188-cam.o clk-mt8188-ccu.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c
> new file mode 100644
> index 000000000000..b7380060f906
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-ccu.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs ccu_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_CCU(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate ccu_clks[] = {
> + GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0),
> + GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
> + GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
> +};
> +
> +static const struct mtk_clk_desc ccu_desc = {
> + .clks = ccu_clks,
> + .num_clks = ARRAY_SIZE(ccu_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_ccu[] = {
> + { .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc},
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_ccu_drv = {
> + .probe = mtk_clk_simple_probe,
> + .remove = mtk_clk_simple_remove,
> + .driver = {
> + .name = "clk-mt8188-ccu",
> + .of_match_table = of_match_clk_mt8188_ccu,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8188_ccu_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (6 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 07/19] clk: mediatek: Add MT8188 ccusys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:58 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys " Garmin.Chang
` (11 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 imgsys clock controllers which provide clock gate
control for image IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-img.c | 110 ++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-img.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index dbd140b81763..be835d5e179d 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
- clk-mt8188-cam.o clk-mt8188-ccu.o
+ clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-img.c b/drivers/clk/mediatek/clk-mt8188-img.c
new file mode 100644
index 000000000000..b6ac0a9a2446
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-img.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs imgsys_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMGSYS(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate imgsys_main_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW1, "imgsys_main_traw1", "top_img", 2),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_VCORE_GALS, "imgsys_main_vcore_gals", "top_img", 3),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_DIP0, "imgsys_main_dip0", "top_img", 8),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE0, "imgsys_main_wpe0", "top_img", 9),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_IPE, "imgsys_main_ipe", "top_img", 10),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE1, "imgsys_main_wpe1", "top_img", 12),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE2, "imgsys_main_wpe2", "top_img", 13),
+ GATE_IMGSYS(CLK_IMGSYS_MAIN_GALS, "imgsys_main_gals", "top_img", 31),
+};
+
+static const struct mtk_gate imgsys_wpe1_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS_WPE1_LARB11, "imgsys_wpe1_larb11", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS_WPE1, "imgsys_wpe1", "top_img", 1),
+};
+
+static const struct mtk_gate imgsys_wpe2_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS_WPE2_LARB11, "imgsys_wpe2_larb11", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS_WPE2, "imgsys_wpe2", "top_img", 1),
+};
+
+static const struct mtk_gate imgsys_wpe3_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS_WPE3_LARB11, "imgsys_wpe3_larb11", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS_WPE3, "imgsys_wpe3", "top_img", 1),
+};
+
+static const struct mtk_gate imgsys1_dip_top_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_LARB10, "imgsys1_dip_larb10", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_DIP_TOP, "imgsys1_dip_dip_top", "top_img", 1),
+};
+
+static const struct mtk_gate imgsys1_dip_nr_clks[] = {
+ GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_LARB15, "imgsys1_dip_nr_larb15", "top_img", 0),
+ GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1),
+};
+
+static const struct mtk_clk_desc imgsys_main_desc = {
+ .clks = imgsys_main_clks,
+ .num_clks = ARRAY_SIZE(imgsys_main_clks),
+};
+
+static const struct mtk_clk_desc imgsys_wpe1_desc = {
+ .clks = imgsys_wpe1_clks,
+ .num_clks = ARRAY_SIZE(imgsys_wpe1_clks),
+};
+
+static const struct mtk_clk_desc imgsys_wpe2_desc = {
+ .clks = imgsys_wpe2_clks,
+ .num_clks = ARRAY_SIZE(imgsys_wpe2_clks),
+};
+
+static const struct mtk_clk_desc imgsys_wpe3_desc = {
+ .clks = imgsys_wpe3_clks,
+ .num_clks = ARRAY_SIZE(imgsys_wpe3_clks),
+};
+
+static const struct mtk_clk_desc imgsys1_dip_top_desc = {
+ .clks = imgsys1_dip_top_clks,
+ .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks),
+};
+
+static const struct mtk_clk_desc imgsys1_dip_nr_desc = {
+ .clks = imgsys1_dip_nr_clks,
+ .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = {
+ { .compatible = "mediatek,mt8188-imgsys", .data = &imgsys_main_desc,},
+ { .compatible = "mediatek,mt8188-imgsys-wpe1", .data = &imgsys_wpe1_desc },
+ { .compatible = "mediatek,mt8188-imgsys-wpe2", .data = &imgsys_wpe2_desc },
+ { .compatible = "mediatek,mt8188-imgsys-wpe3", .data = &imgsys_wpe3_desc },
+ { .compatible = "mediatek,mt8188-imgsys1-dip-top", .data = &imgsys1_dip_top_desc},
+ { .compatible = "mediatek,mt8188-imgsys1-dip-nr", .data = &imgsys1_dip_nr_desc},
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_imgsys_main_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-imgsys_main",
+ .of_match_table = of_match_clk_mt8188_imgsys_main,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_imgsys_main_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys clock support
2023-01-19 12:48 ` [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys " Garmin.Chang
@ 2023-02-03 6:58 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:58 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 imgsys clock controllers which provide clock gate
> control for image IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (7 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 08/19] clk: mediatek: Add MT8188 imgsys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 6:59 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg " Garmin.Chang
` (10 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 ipesys clock controller which provides clock gate
control for Image Process Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8188-ipe.c | 50 +++++++++++++++++++++++++++
2 files changed, 52 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-ipe.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index be835d5e179d..4a599122f761 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -85,7 +85,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
- clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o
+ clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
+ clk-mt8188-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-ipe.c b/drivers/clk/mediatek/clk-mt8188-ipe.c
new file mode 100644
index 000000000000..c18afe0d61b3
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-ipe.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ipe_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IPE(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipe_clks[] = {
+ GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
+ GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
+ GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),
+ GATE_IPE(CLK_IPESYS_TOP, "ipesys_top", "top_ipe", 3),
+ GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
+};
+
+static const struct mtk_clk_desc ipe_desc = {
+ .clks = ipe_clks,
+ .num_clks = ARRAY_SIZE(ipe_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_ipe[] = {
+ { .compatible = "mediatek,mt8188-ipesys", .data = &ipe_desc, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_ipe_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-ipe",
+ .of_match_table = of_match_clk_mt8188_ipe,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_ipe_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys clock support
2023-01-19 12:48 ` [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys " Garmin.Chang
@ 2023-02-03 6:59 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:59 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 ipesys clock controller which provides clock gate
> control for Image Process Engine.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (8 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 09/19] clk: mediatek: Add MT8188 ipesys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:02 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys " Garmin.Chang
` (9 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 mfg clock controller which provides clock gate
control for GPU.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-mfg.c | 47 +++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 4a599122f761..a0fd87a882b5 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
- clk-mt8188-ipe.o
+ clk-mt8188-ipe.o clk-mt8188-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c
new file mode 100644
index 000000000000..57b0afb5f4df
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mfgcfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
+
+static const struct mtk_gate mfgcfg_clks[] = {
+ GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "top_mfg_core_tmp", 0),
+};
+
+static const struct mtk_clk_desc mfgcfg_desc = {
+ .clks = mfgcfg_clks,
+ .num_clks = ARRAY_SIZE(mfgcfg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = {
+ { .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc, },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_mfgcfg_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-mfgcfg",
+ .of_match_table = of_match_clk_mt8188_mfgcfg,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_mfgcfg_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support
2023-01-19 12:48 ` [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg " Garmin.Chang
@ 2023-02-03 7:02 ` Chen-Yu Tsai
2023-03-09 5:30 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:02 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 mfg clock controller which provides clock gate
> control for GPU.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-mfg.c | 47 +++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 4a599122f761..a0fd87a882b5 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> - clk-mt8188-ipe.o
> + clk-mt8188-ipe.o clk-mt8188-mfg.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c
> new file mode 100644
> index 000000000000..57b0afb5f4df
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
> +
> +static const struct mtk_gate mfgcfg_clks[] = {
> + GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "top_mfg_core_tmp", 0),
Are you sure the parent isn't "mfg_ck_fast_ref"?
ChenYu
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg clock support
2023-02-03 7:02 ` Chen-Yu Tsai
@ 2023-03-09 5:30 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:30 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:02 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 mfg clock controller which provides clock gate
> > control for GPU.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-mfg.c | 47
> > +++++++++++++++++++++++++++
> > 2 files changed, 48 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 4a599122f761..a0fd87a882b5 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > - clk-mt8188-ipe.o
> > + clk-mt8188-ipe.o clk-mt8188-
> > mfg.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c
> > b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > new file mode 100644
> > index 000000000000..57b0afb5f4df
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > @@ -0,0 +1,47 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> > + .set_ofs = 0x4,
> > + .clr_ofs = 0x8,
> > + .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_MFG(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs,
> > _shift, \
> > + &mtk_clk_gate_ops_setclr,
> > CLK_SET_RATE_PARENT)
> > +
> > +static const struct mtk_gate mfgcfg_clks[] = {
> > + GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d",
> > "top_mfg_core_tmp", 0),
>
> Are you sure the parent isn't "mfg_ck_fast_ref"?
Thank you for your suggestions.
OK, I will chnage to mfg_ck_fast_ref in v6.
>
> ChenYu
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (9 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 10/19] clk: mediatek: Add MT8188 mfgcfg " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:17 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 " Garmin.Chang
` (8 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vdec clock controllers which provide clock gate
control for video decoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-vdec.c | 90 ++++++++++++++++++++++++++
2 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a0fd87a882b5..7d09e9fc6538 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
- clk-mt8188-ipe.o clk-mt8188-mfg.o
+ clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c
new file mode 100644
index 000000000000..e05a27957136
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-vdec.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs vde0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vde1_cg_regs = {
+ .set_ofs = 0x200,
+ .clr_ofs = 0x204,
+ .sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vde2_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_VDE0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vde0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDE1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vde1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDE2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vde2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate vde1_clks[] = {
+ /* VDE1_0 */
+ GATE_VDE0(CLK_VDE1_SOC_VDEC, "vde1_soc_vdec", "top_vdec", 0),
+ GATE_VDE0(CLK_VDE1_SOC_VDEC_ACTIVE, "vde1_soc_vdec_active", "top_vdec", 4),
+ GATE_VDE0(CLK_VDE1_SOC_VDEC_ENG, "vde1_soc_vdec_eng", "top_vdec", 8),
+ /* VDE1_1 */
+ GATE_VDE1(CLK_VDE1_SOC_LAT, "vde1_soc_lat", "top_vdec", 0),
+ GATE_VDE1(CLK_VDE1_SOC_LAT_ACTIVE, "vde1_soc_lat_active", "top_vdec", 4),
+ GATE_VDE1(CLK_VDE1_SOC_LAT_ENG, "vde1_soc_lat_eng", "top_vdec", 8),
+ /* VDE12 */
+ GATE_VDE2(CLK_VDE1_SOC_LARB1, "vde1_soc_larb1", "top_vdec", 0),
+};
+
+static const struct mtk_gate vde2_clks[] = {
+ /* VDE2_0 */
+ GATE_VDE0(CLK_VDE2_VDEC, "vde2_vdec", "top_vdec", 0),
+ GATE_VDE0(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "top_vdec", 4),
+ GATE_VDE0(CLK_VDE2_VDEC_ENG, "vde2_vdec_eng", "top_vdec", 8),
+ /* VDE2_1 */
+ GATE_VDE1(CLK_VDE2_LAT, "vde2_lat", "top_vdec", 0),
+ /* VDE2_2 */
+ GATE_VDE2(CLK_VDE2_LARB1, "vde2_larb1", "top_vdec", 0),
+};
+
+static const struct mtk_clk_desc vde1_desc = {
+ .clks = vde1_clks,
+ .num_clks = ARRAY_SIZE(vde1_clks),
+};
+
+static const struct mtk_clk_desc vde2_desc = {
+ .clks = vde2_clks,
+ .num_clks = ARRAY_SIZE(vde2_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_vde[] = {
+ { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vde1_desc },
+ { .compatible = "mediatek,mt8188-vdecsys", .data = &vde2_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_vde_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-vde",
+ .of_match_table = of_match_clk_mt8188_vde,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_vde_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys clock support
2023-01-19 12:48 ` [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys " Garmin.Chang
@ 2023-02-03 7:17 ` Chen-Yu Tsai
2023-03-09 5:26 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:17 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vdec clock controllers which provide clock gate
> control for video decoder.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-vdec.c | 90 ++++++++++++++++++++++++++
> 2 files changed, 91 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index a0fd87a882b5..7d09e9fc6538 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> - clk-mt8188-ipe.o clk-mt8188-mfg.o
> + clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c
> new file mode 100644
> index 000000000000..e05a27957136
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vde0_cg_regs = {
Could you replace all instances of "vde" (both upper and lower case)
with "vdec" to be consistent with usages elsewhere?
> + .set_ofs = 0x0,
> + .clr_ofs = 0x4,
> + .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs vde1_cg_regs = {
> + .set_ofs = 0x200,
> + .clr_ofs = 0x204,
> + .sta_ofs = 0x200,
> +};
> +
> +static const struct mtk_gate_regs vde2_cg_regs = {
> + .set_ofs = 0x8,
> + .clr_ofs = 0xc,
> + .sta_ofs = 0x8,
> +};
> +
> +#define GATE_VDE0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vde0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDE1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vde1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDE2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vde2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate vde1_clks[] = {
> + /* VDE1_0 */
> + GATE_VDE0(CLK_VDE1_SOC_VDEC, "vde1_soc_vdec", "top_vdec", 0),
> + GATE_VDE0(CLK_VDE1_SOC_VDEC_ACTIVE, "vde1_soc_vdec_active", "top_vdec", 4),
> + GATE_VDE0(CLK_VDE1_SOC_VDEC_ENG, "vde1_soc_vdec_eng", "top_vdec", 8),
> + /* VDE1_1 */
> + GATE_VDE1(CLK_VDE1_SOC_LAT, "vde1_soc_lat", "top_vdec", 0),
> + GATE_VDE1(CLK_VDE1_SOC_LAT_ACTIVE, "vde1_soc_lat_active", "top_vdec", 4),
> + GATE_VDE1(CLK_VDE1_SOC_LAT_ENG, "vde1_soc_lat_eng", "top_vdec", 8),
> + /* VDE12 */
Add an underscore like the above?
ChenYu
> + GATE_VDE2(CLK_VDE1_SOC_LARB1, "vde1_soc_larb1", "top_vdec", 0),
> +};
> +
> +static const struct mtk_gate vde2_clks[] = {
> + /* VDE2_0 */
> + GATE_VDE0(CLK_VDE2_VDEC, "vde2_vdec", "top_vdec", 0),
> + GATE_VDE0(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "top_vdec", 4),
> + GATE_VDE0(CLK_VDE2_VDEC_ENG, "vde2_vdec_eng", "top_vdec", 8),
> + /* VDE2_1 */
> + GATE_VDE1(CLK_VDE2_LAT, "vde2_lat", "top_vdec", 0),
> + /* VDE2_2 */
> + GATE_VDE2(CLK_VDE2_LARB1, "vde2_larb1", "top_vdec", 0),
> +};
> +
> +static const struct mtk_clk_desc vde1_desc = {
> + .clks = vde1_clks,
> + .num_clks = ARRAY_SIZE(vde1_clks),
> +};
> +
> +static const struct mtk_clk_desc vde2_desc = {
> + .clks = vde2_clks,
> + .num_clks = ARRAY_SIZE(vde2_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_vde[] = {
> + { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vde1_desc },
> + { .compatible = "mediatek,mt8188-vdecsys", .data = &vde2_desc },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_vde_drv = {
> + .probe = mtk_clk_simple_probe,
> + .remove = mtk_clk_simple_remove,
> + .driver = {
> + .name = "clk-mt8188-vde",
> + .of_match_table = of_match_clk_mt8188_vde,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8188_vde_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys clock support
2023-02-03 7:17 ` Chen-Yu Tsai
@ 2023-03-09 5:26 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:26 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:17 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 vdec clock controllers which provide clock gate
> > control for video decoder.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-vdec.c | 90
> > ++++++++++++++++++++++++++
> > 2 files changed, 91 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vdec.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index a0fd87a882b5..7d09e9fc6538 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > - clk-mt8188-ipe.o clk-mt8188-
> > mfg.o
> > + clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c
> > b/drivers/clk/mediatek/clk-mt8188-vdec.c
> > new file mode 100644
> > index 000000000000..e05a27957136
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c
> > @@ -0,0 +1,90 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vde0_cg_regs = {
>
> Could you replace all instances of "vde" (both upper and lower case)
> with "vdec" to be consistent with usages elsewhere?
Thank you for your suggestions.
OK, I will modify this series in v6.
>
> > + .set_ofs = 0x0,
> > + .clr_ofs = 0x4,
> > + .sta_ofs = 0x0,
> > +};
> > +
> > +static const struct mtk_gate_regs vde1_cg_regs = {
> > + .set_ofs = 0x200,
> > + .clr_ofs = 0x204,
> > + .sta_ofs = 0x200,
> > +};
> > +
> > +static const struct mtk_gate_regs vde2_cg_regs = {
> > + .set_ofs = 0x8,
> > + .clr_ofs = 0xc,
> > + .sta_ofs = 0x8,
> > +};
> > +
> > +#define GATE_VDE0(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &vde0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDE1(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &vde1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +#define GATE_VDE2(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &vde2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate vde1_clks[] = {
> > + /* VDE1_0 */
> > + GATE_VDE0(CLK_VDE1_SOC_VDEC, "vde1_soc_vdec", "top_vdec",
> > 0),
> > + GATE_VDE0(CLK_VDE1_SOC_VDEC_ACTIVE, "vde1_soc_vdec_active",
> > "top_vdec", 4),
> > + GATE_VDE0(CLK_VDE1_SOC_VDEC_ENG, "vde1_soc_vdec_eng",
> > "top_vdec", 8),
> > + /* VDE1_1 */
> > + GATE_VDE1(CLK_VDE1_SOC_LAT, "vde1_soc_lat", "top_vdec", 0),
> > + GATE_VDE1(CLK_VDE1_SOC_LAT_ACTIVE, "vde1_soc_lat_active",
> > "top_vdec", 4),
> > + GATE_VDE1(CLK_VDE1_SOC_LAT_ENG, "vde1_soc_lat_eng",
> > "top_vdec", 8),
> > + /* VDE12 */
>
> Add an underscore like the above?
>
> ChenYu
OK, I will add underscore in v6.
>
> > + GATE_VDE2(CLK_VDE1_SOC_LARB1, "vde1_soc_larb1", "top_vdec",
> > 0),
> > +};
> > +
> > +static const struct mtk_gate vde2_clks[] = {
> > + /* VDE2_0 */
> > + GATE_VDE0(CLK_VDE2_VDEC, "vde2_vdec", "top_vdec", 0),
> > + GATE_VDE0(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active",
> > "top_vdec", 4),
> > + GATE_VDE0(CLK_VDE2_VDEC_ENG, "vde2_vdec_eng", "top_vdec",
> > 8),
> > + /* VDE2_1 */
> > + GATE_VDE1(CLK_VDE2_LAT, "vde2_lat", "top_vdec", 0),
> > + /* VDE2_2 */
> > + GATE_VDE2(CLK_VDE2_LARB1, "vde2_larb1", "top_vdec", 0),
> > +};
> > +
> > +static const struct mtk_clk_desc vde1_desc = {
> > + .clks = vde1_clks,
> > + .num_clks = ARRAY_SIZE(vde1_clks),
> > +};
> > +
> > +static const struct mtk_clk_desc vde2_desc = {
> > + .clks = vde2_clks,
> > + .num_clks = ARRAY_SIZE(vde2_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_vde[] = {
> > + { .compatible = "mediatek,mt8188-vdecsys-soc", .data =
> > &vde1_desc },
> > + { .compatible = "mediatek,mt8188-vdecsys", .data =
> > &vde2_desc },
> > + { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver clk_mt8188_vde_drv = {
> > + .probe = mtk_clk_simple_probe,
> > + .remove = mtk_clk_simple_remove,
> > + .driver = {
> > + .name = "clk-mt8188-vde",
> > + .of_match_table = of_match_clk_mt8188_vde,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8188_vde_drv);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (10 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 11/19] clk: mediatek: Add MT8188 vdecsys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:19 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 13/19] clk: mediatek: Add MT8188 vdosys1 " Garmin.Chang
` (7 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vdosys0 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8188-vdo0.c | 134 +++++++++++++++++++++++++
2 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 7d09e9fc6538..df78c0777fef 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
- clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
+ clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
+ clk-mt8188-vdo0.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c
new file mode 100644
index 000000000000..30dd64374ace
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs vdo0_0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo0_1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs vdo0_2_cg_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+#define GATE_VDO0_0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO0_1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO0_2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flags)
+
+static const struct mtk_gate vdo0_clks[] = {
+ /* VDO0_0 */
+ GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
+ GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
+ GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
+ GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
+ GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
+ GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
+ GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
+ GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
+ GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
+ GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
+ GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
+ GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
+ GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
+ GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
+ GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
+ GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
+ GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
+ GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
+ GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
+ /* VDO0_1 */
+ GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
+ GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
+ GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
+ GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
+ GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
+ GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
+ GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
+ GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
+ GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
+ GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
+ GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
+ /* VDO0_2 */
+ GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
+ GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
+ GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
+ "top_edp", 16, CLK_SET_RATE_PARENT),
+};
+
+static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
+ if (r)
+ goto free_vdo0_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
+free_vdo0_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static int clk_mt8188_vdo0_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_vdo0_drv = {
+ .probe = clk_mt8188_vdo0_probe,
+ .remove = clk_mt8188_vdo0_remove,
+ .driver = {
+ .name = "clk-mt8188-vdo0",
+ },
+};
+builtin_platform_driver(clk_mt8188_vdo0_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-01-19 12:48 ` [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 " Garmin.Chang
@ 2023-02-03 7:19 ` Chen-Yu Tsai
2023-02-03 10:49 ` AngeloGioacchino Del Regno
2023-03-09 5:15 ` Garmin Chang (張家銘)
0 siblings, 2 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:19 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
AngeloGioacchino Del Regno
On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vdosys0 clock controller which provides clock gate
> control in video system. This is integrated with mtk-mmsys
> driver which will populate device by platform_device_register_data
> to start vdosys clock driver.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mt8188-vdo0.c | 134 +++++++++++++++++++++++++
> 2 files changed, 136 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 7d09e9fc6538..df78c0777fef 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> - clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
> + clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> + clk-mt8188-vdo0.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> new file mode 100644
> index 000000000000..30dd64374ace
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> + .set_ofs = 0x124,
> + .clr_ofs = 0x128,
> + .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO0_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr, _flags)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> + /* VDO0_0 */
> + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
> + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
> + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
> + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
> + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
> + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
> + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
> + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
> + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
> + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
> + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
> + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
> + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
> + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
> + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
> + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
> + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
> + /* VDO0_1 */
> + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
> + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
> + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
> + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
> + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
> + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
> + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
> + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
> + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
> + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
> + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
> + /* VDO0_2 */
> + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
> + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
> + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
> + "top_edp", 16, CLK_SET_RATE_PARENT),
> +};
> +
> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
This API was changed. Please rebase onto the latest -next and update.
Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
clock drivers is being developed. He didn't mention a timeline though.
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-02-03 7:19 ` Chen-Yu Tsai
@ 2023-02-03 10:49 ` AngeloGioacchino Del Regno
2023-03-09 5:49 ` Garmin Chang (張家銘)
2023-03-09 5:15 ` Garmin Chang (張家銘)
1 sibling, 1 reply; 55+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-02-03 10:49 UTC (permalink / raw)
To: Chen-Yu Tsai, Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>>
>> Add MT8188 vdosys0 clock controller which provides clock gate
>> control in video system. This is integrated with mtk-mmsys
>> driver which will populate device by platform_device_register_data
>> to start vdosys clock driver.
>>
>> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
>> ---
>> drivers/clk/mediatek/Makefile | 3 +-
>> drivers/clk/mediatek/clk-mt8188-vdo0.c | 134 +++++++++++++++++++++++++
>> 2 files changed, 136 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>>
>> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
>> index 7d09e9fc6538..df78c0777fef 100644
>> --- a/drivers/clk/mediatek/Makefile
>> +++ b/drivers/clk/mediatek/Makefile
>> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
>> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
>> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
>> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
>> - clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o
>> + clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
>> + clk-mt8188-vdo0.o
>> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
>> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>> new file mode 100644
>> index 000000000000..30dd64374ace
>> --- /dev/null
>> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>> @@ -0,0 +1,134 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +//
>> +// Copyright (c) 2022 MediaTek Inc.
>> +// Author: Garmin Chang <garmin.chang@mediatek.com>
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
>> +
>> +#include "clk-gate.h"
>> +#include "clk-mtk.h"
>> +
>> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
>> + .set_ofs = 0x104,
>> + .clr_ofs = 0x108,
>> + .sta_ofs = 0x100,
>> +};
>> +
>> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
>> + .set_ofs = 0x114,
>> + .clr_ofs = 0x118,
>> + .sta_ofs = 0x110,
>> +};
>> +
>> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
>> + .set_ofs = 0x124,
>> + .clr_ofs = 0x128,
>> + .sta_ofs = 0x120,
>> +};
>> +
>> +#define GATE_VDO0_0(_id, _name, _parent, _shift) \
>> + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_1(_id, _name, _parent, _shift) \
>> + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_2(_id, _name, _parent, _shift) \
>> + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
>> +
>> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \
>> + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
>> + &mtk_clk_gate_ops_setclr, _flags)
>> +
>> +static const struct mtk_gate vdo0_clks[] = {
>> + /* VDO0_0 */
>> + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
>> + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
>> + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
>> + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
>> + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
>> + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
>> + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
>> + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
>> + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
>> + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
>> + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
>> + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
>> + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
>> + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
>> + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
>> + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
>> + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
>> + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
>> + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
>> + /* VDO0_1 */
>> + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
>> + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
>> + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
>> + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
>> + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
>> + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
>> + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
>> + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
>> + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
>> + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
>> + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
>> + /* VDO0_2 */
>> + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
>> + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
>> + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
>> + "top_edp", 16, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *node = dev->parent->of_node;
>> + struct clk_hw_onecell_data *clk_data;
>> + int r;
>> +
>> + clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
>> + if (!clk_data)
>> + return -ENOMEM;
>> +
>> + r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);
>
> This API was changed. Please rebase onto the latest -next and update.
>
> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> clock drivers is being developed. He didn't mention a timeline though.
I've already tested the new simple probe variant for non-DT clock drivers and
it works fine on MT8173, MT8192 and MT8195.
Timeline - I should be able to push the part 2 series next week, which will include
more conversion to simple probe and almost all clock drivers changed to allow
building as modules.
Cheers,
Angelo
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-02-03 10:49 ` AngeloGioacchino Del Regno
@ 2023-03-09 5:49 ` Garmin Chang (張家銘)
2023-03-09 11:25 ` AngeloGioacchino Del Regno
0 siblings, 1 reply; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:49 UTC (permalink / raw)
To: wenst@chromium.org, angelogioacchino.delregno@collabora.com
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 11:49 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
> > On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> > Garmin.Chang@mediatek.com> wrote:
> > >
> > > Add MT8188 vdosys0 clock controller which provides clock gate
> > > control in video system. This is integrated with mtk-mmsys
> > > driver which will populate device by
> > > platform_device_register_data
> > > to start vdosys clock driver.
> > >
> > > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > > ---
> > > drivers/clk/mediatek/Makefile | 3 +-
> > > drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
> > > +++++++++++++++++++++++++
> > > 2 files changed, 136 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
> > >
> > > diff --git a/drivers/clk/mediatek/Makefile
> > > b/drivers/clk/mediatek/Makefile
> > > index 7d09e9fc6538..df78c0777fef 100644
> > > --- a/drivers/clk/mediatek/Makefile
> > > +++ b/drivers/clk/mediatek/Makefile
> > > @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > > mcu.o clk-mt8186-topckgen.o clk-mt
> > > obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > > mt8188-topckgen.o \
> > > clk-mt8188-peri_ao.o clk-
> > > mt8188-infra_ao.o \
> > > clk-mt8188-cam.o clk-mt8188-
> > > ccu.o clk-mt8188-img.o \
> > > - clk-mt8188-ipe.o clk-mt8188-
> > > mfg.o clk-mt8188-vdec.o
> > > + clk-mt8188-ipe.o clk-mt8188-
> > > mfg.o clk-mt8188-vdec.o \
> > > + clk-mt8188-vdo0.o
> > > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > > diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > new file mode 100644
> > > index 000000000000..30dd64374ace
> > > --- /dev/null
> > > +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > > @@ -0,0 +1,134 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +//
> > > +// Copyright (c) 2022 MediaTek Inc.
> > > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > > +
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/platform_device.h>
> > > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > > +
> > > +#include "clk-gate.h"
> > > +#include "clk-mtk.h"
> > > +
> > > +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> > > + .set_ofs = 0x104,
> > > + .clr_ofs = 0x108,
> > > + .sta_ofs = 0x100,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> > > + .set_ofs = 0x114,
> > > + .clr_ofs = 0x118,
> > > + .sta_ofs = 0x110,
> > > +};
> > > +
> > > +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> > > + .set_ofs = 0x124,
> > > + .clr_ofs = 0x128,
> > > + .sta_ofs = 0x120,
> > > +};
> > > +
> > > +#define GATE_VDO0_0(_id, _name, _parent,
> > > _shift) \
> > > + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_1(_id, _name, _parent,
> > > _shift) \
> > > + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_2(_id, _name, _parent,
> > > _shift) \
> > > + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
> > > &mtk_clk_gate_ops_setclr)
> > > +
> > > +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
> > > _flags) \
> > > + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
> > > _shift, \
> > > + &mtk_clk_gate_ops_setclr, _flags)
> > > +
> > > +static const struct mtk_gate vdo0_clks[] = {
> > > + /* VDO0_0 */
> > > + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
> > > "top_vpp", 0),
> > > + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
> > > "top_vpp", 2),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
> > > "top_vpp", 4),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
> > > "top_vpp", 6),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
> > > "top_vpp", 8),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
> > > "top_vpp", 10),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
> > > "top_vpp", 17),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
> > > "top_vpp", 19),
> > > + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> > > + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> > > + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
> > > "top_vpp", 23),
> > > + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
> > > "top_vpp", 24),
> > > + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0",
> > > "top_vpp", 25),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
> > > "top_vpp", 26),
> > > + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
> > > "top_vpp", 27),
> > > + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
> > > 28),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
> > > "top_vpp", 29),
> > > + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
> > > "top_vpp", 30),
> > > + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
> > > "top_vpp", 31),
> > > + /* VDO0_1 */
> > > + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0,
> > > "vdo0_disp_postmask0", "top_vpp", 0),
> > > + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
> > > "top_vpp", 1),
> > > + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
> > > "top_vpp", 5),
> > > + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
> > > "top_vpp", 6),
> > > + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
> > > "top_vpp", 7),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals",
> > > "top_vpp", 10),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
> > > "top_vpp", 11),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
> > > 12),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
> > > "top_vpp", 13),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb",
> > > "top_vpp", 14),
> > > + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
> > > 15),
> > > + /* VDO0_2 */
> > > + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
> > > "top_dsi_occ", 0),
> > > + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
> > > "top_dsi_occ", 8),
> > > + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
> > > "vdo0_dp_intf0_dp_intf",
> > > + "top_edp", 16, CLK_SET_RATE_PARENT),
> > > +};
> > > +
> > > +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct device_node *node = dev->parent->of_node;
> > > + struct clk_hw_onecell_data *clk_data;
> > > + int r;
> > > +
> > > + clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> > > + if (!clk_data)
> > > + return -ENOMEM;
> > > +
> > > + r = mtk_clk_register_gates(node, vdo0_clks,
> > > ARRAY_SIZE(vdo0_clks), clk_data);
> >
> > This API was changed. Please rebase onto the latest -next and
> > update.
> >
> > Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> > clock drivers is being developed. He didn't mention a timeline
> > though.
>
> I've already tested the new simple probe variant for non-DT clock
> drivers and
> it works fine on MT8173, MT8192 and MT8195.
>
> Timeline - I should be able to push the part 2 series next week,
> which will include
> more conversion to simple probe and almost all clock drivers changed
> to allow
> building as modules.
>
> Cheers,
> Angelo
>
Thank you for your suggestions.
When the new simple probe variant and building as modules are ready, I
will rebase latest-next and update it.
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-03-09 5:49 ` Garmin Chang (張家銘)
@ 2023-03-09 11:25 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 55+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-03-09 11:25 UTC (permalink / raw)
To: Garmin Chang (張家銘), wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
Il 09/03/23 06:49, Garmin Chang (張家銘) ha scritto:
> On Fri, 2023-02-03 at 11:49 +0100, AngeloGioacchino Del Regno wrote:
>> Il 03/02/23 08:19, Chen-Yu Tsai ha scritto:
>>> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
>>> Garmin.Chang@mediatek.com> wrote:
>>>>
>>>> Add MT8188 vdosys0 clock controller which provides clock gate
>>>> control in video system. This is integrated with mtk-mmsys
>>>> driver which will populate device by
>>>> platform_device_register_data
>>>> to start vdosys clock driver.
>>>>
>>>> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
>>>> ---
>>>> drivers/clk/mediatek/Makefile | 3 +-
>>>> drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
>>>> +++++++++++++++++++++++++
>>>> 2 files changed, 136 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>>
>>>> diff --git a/drivers/clk/mediatek/Makefile
>>>> b/drivers/clk/mediatek/Makefile
>>>> index 7d09e9fc6538..df78c0777fef 100644
>>>> --- a/drivers/clk/mediatek/Makefile
>>>> +++ b/drivers/clk/mediatek/Makefile
>>>> @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
>>>> mcu.o clk-mt8186-topckgen.o clk-mt
>>>> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
>>>> mt8188-topckgen.o \
>>>> clk-mt8188-peri_ao.o clk-
>>>> mt8188-infra_ao.o \
>>>> clk-mt8188-cam.o clk-mt8188-
>>>> ccu.o clk-mt8188-img.o \
>>>> - clk-mt8188-ipe.o clk-mt8188-
>>>> mfg.o clk-mt8188-vdec.o
>>>> + clk-mt8188-ipe.o clk-mt8188-
>>>> mfg.o clk-mt8188-vdec.o \
>>>> + clk-mt8188-vdo0.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
>>>> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
>>>> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> new file mode 100644
>>>> index 000000000000..30dd64374ace
>>>> --- /dev/null
>>>> +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
>>>> @@ -0,0 +1,134 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-only
>>>> +//
>>>> +// Copyright (c) 2022 MediaTek Inc.
>>>> +// Author: Garmin Chang <garmin.chang@mediatek.com>
>>>> +
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
>>>> +
>>>> +#include "clk-gate.h"
>>>> +#include "clk-mtk.h"
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_0_cg_regs = {
>>>> + .set_ofs = 0x104,
>>>> + .clr_ofs = 0x108,
>>>> + .sta_ofs = 0x100,
>>>> +};
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_1_cg_regs = {
>>>> + .set_ofs = 0x114,
>>>> + .clr_ofs = 0x118,
>>>> + .sta_ofs = 0x110,
>>>> +};
>>>> +
>>>> +static const struct mtk_gate_regs vdo0_2_cg_regs = {
>>>> + .set_ofs = 0x124,
>>>> + .clr_ofs = 0x128,
>>>> + .sta_ofs = 0x120,
>>>> +};
>>>> +
>>>> +#define GATE_VDO0_0(_id, _name, _parent,
>>>> _shift) \
>>>> + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_1(_id, _name, _parent,
>>>> _shift) \
>>>> + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_2(_id, _name, _parent,
>>>> _shift) \
>>>> + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
>>>> &mtk_clk_gate_ops_setclr)
>>>> +
>>>> +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
>>>> _flags) \
>>>> + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
>>>> _shift, \
>>>> + &mtk_clk_gate_ops_setclr, _flags)
>>>> +
>>>> +static const struct mtk_gate vdo0_clks[] = {
>>>> + /* VDO0_0 */
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
>>>> "top_vpp", 0),
>>>> + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
>>>> "top_vpp", 2),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
>>>> "top_vpp", 4),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
>>>> "top_vpp", 6),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
>>>> "top_vpp", 8),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
>>>> "top_vpp", 10),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
>>>> "top_vpp", 17),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
>>>> "top_vpp", 19),
>>>> + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
>>>> + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
>>>> + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
>>>> "top_vpp", 23),
>>>> + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
>>>> "top_vpp", 24),
>>>> + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0",
>>>> "top_vpp", 25),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
>>>> "top_vpp", 26),
>>>> + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
>>>> "top_vpp", 27),
>>>> + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
>>>> 28),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
>>>> "top_vpp", 29),
>>>> + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
>>>> "top_vpp", 30),
>>>> + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
>>>> "top_vpp", 31),
>>>> + /* VDO0_1 */
>>>> + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0,
>>>> "vdo0_disp_postmask0", "top_vpp", 0),
>>>> + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
>>>> "top_vpp", 1),
>>>> + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
>>>> "top_vpp", 5),
>>>> + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
>>>> "top_vpp", 6),
>>>> + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
>>>> "top_vpp", 7),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals",
>>>> "top_vpp", 10),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
>>>> "top_vpp", 11),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
>>>> 12),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
>>>> "top_vpp", 13),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb",
>>>> "top_vpp", 14),
>>>> + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
>>>> 15),
>>>> + /* VDO0_2 */
>>>> + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
>>>> "top_dsi_occ", 0),
>>>> + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
>>>> "top_dsi_occ", 8),
>>>> + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
>>>> "vdo0_dp_intf0_dp_intf",
>>>> + "top_edp", 16, CLK_SET_RATE_PARENT),
>>>> +};
>>>> +
>>>> +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct device *dev = &pdev->dev;
>>>> + struct device_node *node = dev->parent->of_node;
>>>> + struct clk_hw_onecell_data *clk_data;
>>>> + int r;
>>>> +
>>>> + clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
>>>> + if (!clk_data)
>>>> + return -ENOMEM;
>>>> +
>>>> + r = mtk_clk_register_gates(node, vdo0_clks,
>>>> ARRAY_SIZE(vdo0_clks), clk_data);
>>>
>>> This API was changed. Please rebase onto the latest -next and
>>> update.
>>>
>>> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
>>> clock drivers is being developed. He didn't mention a timeline
>>> though.
>>
>> I've already tested the new simple probe variant for non-DT clock
>> drivers and
>> it works fine on MT8173, MT8192 and MT8195.
>>
>> Timeline - I should be able to push the part 2 series next week,
>> which will include
>> more conversion to simple probe and almost all clock drivers changed
>> to allow
>> building as modules.
>>
>> Cheers,
>> Angelo
>>
> Thank you for your suggestions.
> When the new simple probe variant and building as modules are ready, I
> will rebase latest-next and update it.
It's *finally* ready as it's fully tested and reviewed.
You can go on with a rebase on top of it:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=726914
Regards,
Angelo
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 clock support
2023-02-03 7:19 ` Chen-Yu Tsai
2023-02-03 10:49 ` AngeloGioacchino Del Regno
@ 2023-03-09 5:15 ` Garmin Chang (張家銘)
1 sibling, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:15 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org,
angelogioacchino.delregno@collabora.com
On Fri, 2023-02-03 at 15:19 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 vdosys0 clock controller which provides clock gate
> > control in video system. This is integrated with mtk-mmsys
> > driver which will populate device by platform_device_register_data
> > to start vdosys clock driver.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 3 +-
> > drivers/clk/mediatek/clk-mt8188-vdo0.c | 134
> > +++++++++++++++++++++++++
> > 2 files changed, 136 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo0.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 7d09e9fc6538..df78c0777fef 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -86,7 +86,8 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > - clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o
> > + clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > + clk-mt8188-vdo0.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > new file mode 100644
> > index 000000000000..30dd64374ace
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c
> > @@ -0,0 +1,134 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vdo0_0_cg_regs = {
> > + .set_ofs = 0x104,
> > + .clr_ofs = 0x108,
> > + .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs vdo0_1_cg_regs = {
> > + .set_ofs = 0x114,
> > + .clr_ofs = 0x118,
> > + .sta_ofs = 0x110,
> > +};
> > +
> > +static const struct mtk_gate_regs vdo0_2_cg_regs = {
> > + .set_ofs = 0x124,
> > + .clr_ofs = 0x128,
> > + .sta_ofs = 0x120,
> > +};
> > +
> > +#define GATE_VDO0_0(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_1(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_2(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift,
> > _flags) \
> > + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs,
> > _shift, \
> > + &mtk_clk_gate_ops_setclr, _flags)
> > +
> > +static const struct mtk_gate vdo0_clks[] = {
> > + /* VDO0_0 */
> > + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0",
> > "top_vpp", 0),
> > + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0",
> > "top_vpp", 2),
> > + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0",
> > "top_vpp", 4),
> > + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0",
> > "top_vpp", 6),
> > + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0",
> > "top_vpp", 8),
> > + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0",
> > "top_vpp", 10),
> > + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0",
> > "top_vpp", 17),
> > + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0",
> > "top_vpp", 19),
> > + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
> > + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
> > + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0",
> > "top_vpp", 23),
> > + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0",
> > "top_vpp", 24),
> > + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp",
> > 25),
> > + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0",
> > "top_vpp", 26),
> > + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0",
> > "top_vpp", 27),
> > + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp",
> > 28),
> > + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0",
> > "top_vpp", 29),
> > + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0",
> > "top_vpp", 30),
> > + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0",
> > "top_vpp", 31),
> > + /* VDO0_1 */
> > + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0",
> > "top_vpp", 0),
> > + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1",
> > "top_vpp", 1),
> > + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2",
> > "top_vpp", 5),
> > + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3",
> > "top_vpp", 6),
> > + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4",
> > "top_vpp", 7),
> > + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp",
> > 10),
> > + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common",
> > "top_vpp", 11),
> > + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp",
> > 12),
> > + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu",
> > "top_vpp", 13),
> > + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp",
> > 14),
> > + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp",
> > 15),
> > + /* VDO0_2 */
> > + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi",
> > "top_dsi_occ", 0),
> > + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi",
> > "top_dsi_occ", 8),
> > + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF,
> > "vdo0_dp_intf0_dp_intf",
> > + "top_edp", 16, CLK_SET_RATE_PARENT),
> > +};
> > +
> > +static int clk_mt8188_vdo0_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->parent->of_node;
> > + struct clk_hw_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_gates(node, vdo0_clks,
> > ARRAY_SIZE(vdo0_clks), clk_data);
>
> This API was changed. Please rebase onto the latest -next and update.
Thank you for your suggestions.
OK I will modify it in v6.
>
> Angelo (CC-ed) also mentioned a new simple probe variant for non-DT
> clock drivers is being developed. He didn't mention a timeline
> though.
When the new simple probe variant is ready, I will rebase latest-next
and update it.
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 13/19] clk: mediatek: Add MT8188 vdosys1 clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (11 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 12/19] clk: mediatek: Add MT8188 vdosys0 " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:22 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys " Garmin.Chang
` (6 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vdosys1 clock controller which provides clock gate
control in video system. This is integrated with mtk-mmsys
driver which will populate device by platform_device_register_data
to start vdosys clock driver.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-vdo1.c | 181 +++++++++++++++++++++++++
2 files changed, 182 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo1.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index df78c0777fef..c654f4288e09 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
- clk-mt8188-vdo0.o
+ clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c
new file mode 100644
index 000000000000..be658c6a95bf
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs vdo1_0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo1_1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs vdo1_2_cg_regs = {
+ .set_ofs = 0x124,
+ .clr_ofs = 0x128,
+ .sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs vdo1_3_cg_regs = {
+ .set_ofs = 0x134,
+ .clr_ofs = 0x138,
+ .sta_ofs = 0x130,
+};
+
+static const struct mtk_gate_regs vdo1_4_cg_regs = {
+ .set_ofs = 0x144,
+ .clr_ofs = 0x148,
+ .sta_ofs = 0x140,
+};
+
+#define GATE_VDO1_0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO1_1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO1_2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO1_3(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, _flags)
+
+#define GATE_VDO1_4(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vdo1_clks[] = {
+ /* VDO1_0 */
+ GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
+ GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
+ GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
+ GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
+ GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, "vdo1_fake_eng1", "top_vpp", 4),
+ GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
+ GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
+ GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
+ GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
+ GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
+ GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
+ GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
+ /* VDO1_1 */
+ GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 0),
+ GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 1),
+ GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2),
+ GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 3),
+ GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 4),
+ GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 5),
+ GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 6),
+ GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 7),
+ GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 8),
+ GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, "vdo1_dp_intf0_mmck", "top_vpp", 9),
+ GATE_VDO1_1(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm_ck", "top_vpp", 10),
+ GATE_VDO1_1(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm_ck", "top_vpp", 11),
+ GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 13),
+ GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 14),
+ GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 15),
+ GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 16),
+ GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 17),
+ GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, "vdo1_dsc_vdo1_dl_async", "top_vpp", 18),
+ GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, "vdo1_merge_vdo1_dl_async", "top_vpp", 19),
+ GATE_VDO1_1(CLK_VDO1_PADDING0, "vdo1_padding0", "top_vpp", 20),
+ GATE_VDO1_1(CLK_VDO1_PADDING1, "vdo1_padding1", "top_vpp", 21),
+ GATE_VDO1_1(CLK_VDO1_PADDING2, "vdo1_padding2", "top_vpp", 22),
+ GATE_VDO1_1(CLK_VDO1_PADDING3, "vdo1_padding3", "top_vpp", 23),
+ GATE_VDO1_1(CLK_VDO1_PADDING4, "vdo1_padding4", "top_vpp", 24),
+ GATE_VDO1_1(CLK_VDO1_PADDING5, "vdo1_padding5", "top_vpp", 25),
+ GATE_VDO1_1(CLK_VDO1_PADDING6, "vdo1_padding6", "top_vpp", 26),
+ GATE_VDO1_1(CLK_VDO1_PADDING7, "vdo1_padding7", "top_vpp", 27),
+ GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, "vdo1_disp_rsz0", "top_vpp", 28),
+ GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, "vdo1_disp_rsz1", "top_vpp", 29),
+ GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, "vdo1_disp_rsz2", "top_vpp", 30),
+ GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, "vdo1_disp_rsz3", "top_vpp", 31),
+ /* VDO1_2 */
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
+ GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
+ GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
+ GATE_VDO1_2(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
+ GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
+ GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
+ GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
+ /* VDO1_3 */
+ GATE_VDO1_3(CLK_VDO1_DPI0, "vdo1_dpi0_ck", "top_vpp", 0),
+ GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0_ck", "top_vpp", 1),
+ GATE_VDO1_3(CLK_VDO1_DPI1, "vdo1_dpi1_ck", "top_vpp", 8),
+ GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1_ck", "top_vpp", 9),
+ GATE_VDO1_3_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT),
+ GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),
+ /* VDO1_4 */
+ GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),
+};
+
+static int clk_mt8188_vdo1_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
+ if (r)
+ goto free_vdo1_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
+free_vdo1_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static int clk_mt8188_vdo1_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_vdo1_drv = {
+ .probe = clk_mt8188_vdo1_probe,
+ .remove = clk_mt8188_vdo1_remove,
+ .driver = {
+ .name = "clk-mt8188-vdo1",
+ },
+};
+builtin_platform_driver(clk_mt8188_vdo1_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 13/19] clk: mediatek: Add MT8188 vdosys1 clock support
2023-01-19 12:48 ` [PATCH v5 13/19] clk: mediatek: Add MT8188 vdosys1 " Garmin.Chang
@ 2023-02-03 7:22 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:22 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:51 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vdosys1 clock controller which provides clock gate
> control in video system. This is integrated with mtk-mmsys
> driver which will populate device by platform_device_register_data
> to start vdosys clock driver.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-vdo1.c | 181 +++++++++++++++++++++++++
> 2 files changed, 182 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vdo1.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index df78c0777fef..c654f4288e09 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> - clk-mt8188-vdo0.o
> + clk-mt8188-vdo0.o clk-mt8188-vdo1.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c
> new file mode 100644
> index 000000000000..be658c6a95bf
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vdo1_0_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo1_1_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo1_2_cg_regs = {
> + .set_ofs = 0x124,
> + .clr_ofs = 0x128,
> + .sta_ofs = 0x120,
> +};
> +
> +static const struct mtk_gate_regs vdo1_3_cg_regs = {
> + .set_ofs = 0x134,
> + .clr_ofs = 0x138,
> + .sta_ofs = 0x130,
> +};
> +
> +static const struct mtk_gate_regs vdo1_4_cg_regs = {
> + .set_ofs = 0x144,
> + .clr_ofs = 0x148,
> + .sta_ofs = 0x140,
> +};
> +
> +#define GATE_VDO1_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO1_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO1_2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO1_3(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr, _flags)
You could reverse GATE_VDO1_3 and GATE_VDO1_3_FLAGS, and then define
GATE_VDO1_3 with GATE_VDO1_3_FLAGS. You could do the same for vdosys0
driver as well.
> +#define GATE_VDO1_4(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo1_clks[] = {
> + /* VDO1_0 */
> + GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
> + GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1),
> + GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2),
> + GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3),
> + GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, "vdo1_fake_eng1", "top_vpp", 4),
> + GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5),
> + GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6),
> + GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7),
> + GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8),
> + GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9),
> + GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10),
> + GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11),
> + /* VDO1_1 */
> + GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 0),
> + GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 1),
> + GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2),
> + GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 3),
> + GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 4),
> + GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 5),
> + GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 6),
> + GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 7),
> + GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 8),
> + GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, "vdo1_dp_intf0_mmck", "top_vpp", 9),
> + GATE_VDO1_1(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm_ck", "top_vpp", 10),
> + GATE_VDO1_1(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm_ck", "top_vpp", 11),
> + GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 13),
> + GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 14),
> + GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 15),
> + GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 16),
> + GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 17),
> + GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, "vdo1_dsc_vdo1_dl_async", "top_vpp", 18),
> + GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, "vdo1_merge_vdo1_dl_async", "top_vpp", 19),
> + GATE_VDO1_1(CLK_VDO1_PADDING0, "vdo1_padding0", "top_vpp", 20),
> + GATE_VDO1_1(CLK_VDO1_PADDING1, "vdo1_padding1", "top_vpp", 21),
> + GATE_VDO1_1(CLK_VDO1_PADDING2, "vdo1_padding2", "top_vpp", 22),
> + GATE_VDO1_1(CLK_VDO1_PADDING3, "vdo1_padding3", "top_vpp", 23),
> + GATE_VDO1_1(CLK_VDO1_PADDING4, "vdo1_padding4", "top_vpp", 24),
> + GATE_VDO1_1(CLK_VDO1_PADDING5, "vdo1_padding5", "top_vpp", 25),
> + GATE_VDO1_1(CLK_VDO1_PADDING6, "vdo1_padding6", "top_vpp", 26),
> + GATE_VDO1_1(CLK_VDO1_PADDING7, "vdo1_padding7", "top_vpp", 27),
> + GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, "vdo1_disp_rsz0", "top_vpp", 28),
> + GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, "vdo1_disp_rsz1", "top_vpp", 29),
> + GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, "vdo1_disp_rsz2", "top_vpp", 30),
> + GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, "vdo1_disp_rsz3", "top_vpp", 31),
> + /* VDO1_2 */
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0),
> + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1),
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2),
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16),
> + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17),
> + GATE_VDO1_2(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18),
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19),
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20),
> + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21),
> + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22),
> + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23),
> + /* VDO1_3 */
> + GATE_VDO1_3(CLK_VDO1_DPI0, "vdo1_dpi0_ck", "top_vpp", 0),
> + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0_ck", "top_vpp", 1),
> + GATE_VDO1_3(CLK_VDO1_DPI1, "vdo1_dpi1_ck", "top_vpp", 8),
> + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1_ck", "top_vpp", 9),
> + GATE_VDO1_3_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT),
> + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),
> + /* VDO1_4 */
> + GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),
> +};
> +
> +static int clk_mt8188_vdo1_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
Same as vdosys0 patch, this API was changed and the usage here needs to
be updated.
ChenYu
> + if (r)
> + goto free_vdo1_data;
> +
> + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> + if (r)
> + goto unregister_gates;
> +
> + platform_set_drvdata(pdev, clk_data);
> +
> + return r;
> +
> +unregister_gates:
> + mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
> +free_vdo1_data:
> + mtk_free_clk_data(clk_data);
> + return r;
> +}
> +
> +static int clk_mt8188_vdo1_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(node);
> + mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);
> + mtk_free_clk_data(clk_data);
> +
> + return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_vdo1_drv = {
> + .probe = clk_mt8188_vdo1_probe,
> + .remove = clk_mt8188_vdo1_remove,
> + .driver = {
> + .name = "clk-mt8188-vdo1",
> + },
> +};
> +builtin_platform_driver(clk_mt8188_vdo1_drv);
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (12 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 13/19] clk: mediatek: Add MT8188 vdosys1 " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:25 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang
` (5 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-venc.c | 52 ++++++++++++++++++++++++++
2 files changed, 53 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index c654f4288e09..22a3840160fc 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
- clk-mt8188-vdo0.o clk-mt8188-vdo1.o
+ clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c b/drivers/clk/mediatek/clk-mt8188-venc.c
new file mode 100644
index 000000000000..375ef99e2349
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-venc.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs ven1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VEN1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate ven1_clks[] = {
+ GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc", 0),
+ GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc", 4),
+ GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc", "top_venc", 8),
+ GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec", "top_venc", 12),
+ GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1", "top_venc", 16),
+ GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc", 28),
+ GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram", "top_venc", 31),
+};
+
+static const struct mtk_clk_desc ven1_desc = {
+ .clks = ven1_clks,
+ .num_clks = ARRAY_SIZE(ven1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_ven1[] = {
+ { .compatible = "mediatek,mt8188-vencsys", .data = &ven1_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_ven1_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-ven1",
+ .of_match_table = of_match_clk_mt8188_ven1,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_ven1_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support
2023-01-19 12:48 ` [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys " Garmin.Chang
@ 2023-02-03 7:25 ` Chen-Yu Tsai
2023-03-09 5:28 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:25 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vencsys clock controllers which provide clock gate
> control for video encoder.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-venc.c | 52 ++++++++++++++++++++++++++
> 2 files changed, 53 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index c654f4288e09..22a3840160fc 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> - clk-mt8188-vdo0.o clk-mt8188-vdo1.o
> + clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c b/drivers/clk/mediatek/clk-mt8188-venc.c
> new file mode 100644
> index 000000000000..375ef99e2349
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-venc.c
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs ven1_cg_regs = {
Like the vdecsys patch, please change "ven" to "venc" to be consistent
with usages elsewhere.
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_VEN1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate ven1_clks[] = {
> + GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc", 0),
> + GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc", 4),
> + GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc", "top_venc", 8),
> + GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec", "top_venc", 12),
> + GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1", "top_venc", 16),
> + GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc", 28),
> + GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram", "top_venc", 31),
Is ckeN in both the macro name and clock name necessary? We don't really
care about the index.
ChenYu
> +};
> +
> +static const struct mtk_clk_desc ven1_desc = {
> + .clks = ven1_clks,
> + .num_clks = ARRAY_SIZE(ven1_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_ven1[] = {
> + { .compatible = "mediatek,mt8188-vencsys", .data = &ven1_desc },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_ven1_drv = {
> + .probe = mtk_clk_simple_probe,
> + .remove = mtk_clk_simple_remove,
> + .driver = {
> + .name = "clk-mt8188-ven1",
> + .of_match_table = of_match_clk_mt8188_ven1,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8188_ven1_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support
2023-02-03 7:25 ` Chen-Yu Tsai
@ 2023-03-09 5:28 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 5:28 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:25 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 vencsys clock controllers which provide clock gate
> > control for video encoder.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-venc.c | 52
> > ++++++++++++++++++++++++++
> > 2 files changed, 53 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index c654f4288e09..22a3840160fc 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > - clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o
> > + clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c
> > b/drivers/clk/mediatek/clk-mt8188-venc.c
> > new file mode 100644
> > index 000000000000..375ef99e2349
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-venc.c
> > @@ -0,0 +1,52 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs ven1_cg_regs = {
>
> Like the vdecsys patch, please change "ven" to "venc" to be
> consistent
> with usages elsewhere.
Thank you for your suggestions.
OK, I will modify this series in v6.
>
> > + .set_ofs = 0x4,
> > + .clr_ofs = 0x8,
> > + .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_VEN1(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate ven1_clks[] = {
> > + GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc",
> > 0),
> > + GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc",
> > 4),
> > + GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc",
> > "top_venc", 8),
> > + GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec",
> > "top_venc", 12),
> > + GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1",
> > "top_venc", 16),
> > + GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc",
> > 28),
> > + GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram",
> > "top_venc", 31),
>
> Is ckeN in both the macro name and clock name necessary? We don't
> really
> care about the index.
>
> ChenYu
OK, I will modify it in v6.
>
> > +};
> > +
> > +static const struct mtk_clk_desc ven1_desc = {
> > + .clks = ven1_clks,
> > + .num_clks = ARRAY_SIZE(ven1_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_ven1[] = {
> > + { .compatible = "mediatek,mt8188-vencsys", .data =
> > &ven1_desc },
> > + { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver clk_mt8188_ven1_drv = {
> > + .probe = mtk_clk_simple_probe,
> > + .remove = mtk_clk_simple_remove,
> > + .driver = {
> > + .name = "clk-mt8188-ven1",
> > + .of_match_table = of_match_clk_mt8188_ven1,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8188_ven1_drv);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (13 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-01-19 15:45 ` Matthias Brugger
2023-02-03 7:33 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang
` (4 subsequent siblings)
19 siblings, 2 replies; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vppsys0 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8188-vpp0.c | 143 +++++++++++++++++++++++++
2 files changed, 145 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 22a3840160fc..48deecc6b520 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
- clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
+ clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
+ clk-mt8188-vpp0.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c
new file mode 100644
index 000000000000..e7b46142d653
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs vpp0_0_cg_regs = {
+ .set_ofs = 0x24,
+ .clr_ofs = 0x28,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs vpp0_1_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x34,
+ .sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs vpp0_2_cg_regs = {
+ .set_ofs = 0x3c,
+ .clr_ofs = 0x40,
+ .sta_ofs = 0x38,
+};
+
+#define GATE_VPP0_0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP0_1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP0_2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vpp0_clks[] = {
+ /* VPP0_0 */
+ GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
+ GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
+ GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
+ GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
+ GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
+ GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
+ GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
+ GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
+ GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
+ GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
+ GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
+ GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
+ /* VPP0_1 */
+ GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
+ GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
+ GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
+ GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
+ GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
+ "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
+ GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
+ GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
+ GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
+ GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
+ GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
+ GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
+ GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
+ GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
+ GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
+ GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
+ GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
+ GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
+ GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
+ GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
+ GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
+ GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
+ "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
+ GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
+ GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
+ GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
+ GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
+ GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
+ GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
+ GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
+ GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
+ /* VPP0_2 */
+ GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
+ GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
+ GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
+ GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
+};
+
+static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
+ if (r)
+ goto free_vpp0_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
+free_vpp0_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static int clk_mt8188_vpp0_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_vpp0_drv = {
+ .probe = clk_mt8188_vpp0_probe,
+ .remove = clk_mt8188_vpp0_remove,
+ .driver = {
+ .name = "clk-mt8188-vpp0",
+ },
+};
+builtin_platform_driver(clk_mt8188_vpp0_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support
2023-01-19 12:48 ` [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang
@ 2023-01-19 15:45 ` Matthias Brugger
2023-02-03 7:33 ` Chen-Yu Tsai
1 sibling, 0 replies; 55+ messages in thread
From: Matthias Brugger @ 2023-01-19 15:45 UTC (permalink / raw)
To: Garmin.Chang, Rob Herring, Krzysztof Kozlowski, Michael Turquette,
Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On 19/01/2023 13:48, Garmin.Chang wrote:
> Add MT8188 vppsys0 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mt8188-vpp0.c | 143 +++++++++++++++++++++++++
> 2 files changed, 145 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 22a3840160fc..48deecc6b520 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> - clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
> + clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> + clk-mt8188-vpp0.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> new file mode 100644
> index 000000000000..e7b46142d653
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> + .set_ofs = 0x24,
> + .clr_ofs = 0x28,
> + .sta_ofs = 0x20,
> +};
> +
> +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> + .set_ofs = 0x30,
> + .clr_ofs = 0x34,
> + .sta_ofs = 0x2c,
> +};
> +
> +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> + .set_ofs = 0x3c,
> + .clr_ofs = 0x40,
> + .sta_ofs = 0x38,
> +};
> +
> +#define GATE_VPP0_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp0_clks[] = {
> + /* VPP0_0 */
> + GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> + GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> + GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
> + GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
> + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
> + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
> + GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
> + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
> + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
> + GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
> + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
> + /* VPP0_1 */
> + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> + "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
> + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
> + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
> + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
> + GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
> + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
> + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> + GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
> + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> + "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
> + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
> + GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
> + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
> + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
> + GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
> + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
> + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
> + GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
> + /* VPP0_2 */
> + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
> + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
> + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
> + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
> +};
> +
> +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> + if (r)
> + goto free_vpp0_data;
> +
> + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> + if (r)
> + goto unregister_gates;
> +
> + platform_set_drvdata(pdev, clk_data);
> +
> + return r;
> +
> +unregister_gates:
> + mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> +free_vpp0_data:
> + mtk_free_clk_data(clk_data);
> + return r;
> +}
> +
> +static int clk_mt8188_vpp0_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(node);
> + mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
> + mtk_free_clk_data(clk_data);
> +
> + return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_vpp0_drv = {
> + .probe = clk_mt8188_vpp0_probe,
> + .remove = clk_mt8188_vpp0_remove,
> + .driver = {
> + .name = "clk-mt8188-vpp0",
> + },
> +};
> +builtin_platform_driver(clk_mt8188_vpp0_drv);
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support
2023-01-19 12:48 ` [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang
2023-01-19 15:45 ` Matthias Brugger
@ 2023-02-03 7:33 ` Chen-Yu Tsai
2023-03-09 3:23 ` Garmin Chang (張家銘)
1 sibling, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:33 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vppsys0 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mt8188-vpp0.c | 143 +++++++++++++++++++++++++
> 2 files changed, 145 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 22a3840160fc..48deecc6b520 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> - clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o
> + clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> + clk-mt8188-vpp0.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> new file mode 100644
> index 000000000000..e7b46142d653
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> + .set_ofs = 0x24,
> + .clr_ofs = 0x28,
> + .sta_ofs = 0x20,
> +};
> +
> +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> + .set_ofs = 0x30,
> + .clr_ofs = 0x34,
> + .sta_ofs = 0x2c,
> +};
> +
> +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> + .set_ofs = 0x3c,
> + .clr_ofs = 0x40,
> + .sta_ofs = 0x38,
> +};
> +
> +#define GATE_VPP0_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP0_2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp0_clks[] = {
> + /* VPP0_0 */
> + GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> + GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> + GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
> + GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
> + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
> + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
> + GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14),
> + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
> + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
> + GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
> + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
> + /* VPP0_1 */
> + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> + "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4),
> + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5),
> + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
> + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
> + GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
> + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
> + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> + GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
> + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> + "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22),
> + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
> + GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
> + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
> + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
> + GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
> + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28),
> + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29),
> + GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30),
> + /* VPP0_2 */
> + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
> + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1),
> + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
> + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3),
> +};
> +
> +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
This API has changed. Please rebase and update.
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support
2023-02-03 7:33 ` Chen-Yu Tsai
@ 2023-03-09 3:23 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 3:23 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:33 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 vppsys0 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 3 +-
> > drivers/clk/mediatek/clk-mt8188-vpp0.c | 143
> > +++++++++++++++++++++++++
> > 2 files changed, 145 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 22a3840160fc..48deecc6b520 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > - clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> > + clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > + clk-mt8188-vpp0.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > new file mode 100644
> > index 000000000000..e7b46142d653
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > @@ -0,0 +1,143 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> > + .set_ofs = 0x24,
> > + .clr_ofs = 0x28,
> > + .sta_ofs = 0x20,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> > + .set_ofs = 0x30,
> > + .clr_ofs = 0x34,
> > + .sta_ofs = 0x2c,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> > + .set_ofs = 0x3c,
> > + .clr_ofs = 0x40,
> > + .sta_ofs = 0x38,
> > +};
> > +
> > +#define GATE_VPP0_0(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_1(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_2(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp0_clks[] = {
> > + /* VPP0_0 */
> > + GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> > + GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> > + GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp",
> > 7),
> > + GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp",
> > 8),
> > + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx",
> > "top_vpp", 10),
> > + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx",
> > "top_vpp", 11),
> > + GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> > + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay",
> > "top_vpp", 14),
> > + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC,
> > "vpp0_vpp12vpp0_async", "top_vpp", 15),
> > + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top",
> > "top_vpp", 16),
> > + GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp",
> > 17),
> > + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp",
> > 18),
> > + /* VPP0_1 */
> > + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM,
> > "vpp0_smi_common_mmsram", "top_vpp", 0),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM,
> > "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM,
> > "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM,
> > "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> > + "vpp0_gals_vencsys_core1_mmsram", "top_vpp",
> > 4),
> > + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM,
> > "vpp0_gals_infra_mmsram", "top_vpp", 5),
> > + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM,
> > "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM,
> > "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM,
> > "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> > + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM,
> > "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> > + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu",
> > "top_vpp", 10),
> > + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS,
> > "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> > + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp",
> > 12),
> > + GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp",
> > 13),
> > + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1",
> > "top_vpp", 16),
> > + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER,
> > "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> > + GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp",
> > 18),
> > + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4,
> > "vpp0_smi_common_larb4", "top_vpp", 19),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1,
> > "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS,
> > "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> > + "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp",
> > 22),
> > + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp",
> > 23),
> > + GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp",
> > 24),
> > + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp",
> > "top_vpp", 25),
> > + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color",
> > "top_vpp", 26),
> > + GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp",
> > 27),
> > + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma",
> > "top_vpp", 28),
> > + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma",
> > "top_vpp", 29),
> > + GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp",
> > 30),
> > + /* VPP0_2 */
> > + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay",
> > "top_wpe_vpp", 0),
> > + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async",
> > "top_wpe_vpp", 1),
> > + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay",
> > "top_wpe_vpp", 2),
> > + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async",
> > "top_wpe_vpp", 3),
> > +};
> > +
> > +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->parent->of_node;
> > + struct clk_hw_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_gates(node, vpp0_clks,
> > ARRAY_SIZE(vpp0_clks), clk_data);
>
> This API has changed. Please rebase and update.
Thank you for your suggestions.
OK I will modify it in v6.
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (14 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-01-19 15:48 ` Matthias Brugger
2023-02-03 7:35 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys " Garmin.Chang
` (3 subsequent siblings)
19 siblings, 2 replies; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-vpp1.c | 138 +++++++++++++++++++++++++
2 files changed, 139 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 48deecc6b520..37663de293bf 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
- clk-mt8188-vpp0.o
+ clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c
new file mode 100644
index 000000000000..2bff3a52c93f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs vpp1_0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vpp1_1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+#define GATE_VPP1_0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_VPP1_1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate vpp1_clks[] = {
+ /* VPP1_0 */
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
+ GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
+ GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
+ GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
+ GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
+ GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
+ GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
+ GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
+ GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
+ /* VPP1_1 */
+ GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
+ GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
+ GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
+ GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
+ GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
+ GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
+ GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
+ GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
+ GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
+ GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
+ GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
+ GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
+ GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
+ GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
+ GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
+ GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
+ GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
+ GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
+ GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
+ GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
+};
+
+static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
+ if (!clk_data)
+ return -ENOMEM;
+
+ r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
+ if (r)
+ goto free_vpp1_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_gates;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return r;
+
+unregister_gates:
+ mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
+free_vpp1_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static int clk_mt8188_vpp1_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->parent->of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+}
+
+static struct platform_driver clk_mt8188_vpp1_drv = {
+ .probe = clk_mt8188_vpp1_probe,
+ .remove = clk_mt8188_vpp1_remove,
+ .driver = {
+ .name = "clk-mt8188-vpp1",
+ },
+};
+builtin_platform_driver(clk_mt8188_vpp1_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support
2023-01-19 12:48 ` [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang
@ 2023-01-19 15:48 ` Matthias Brugger
2023-02-03 7:35 ` Chen-Yu Tsai
1 sibling, 0 replies; 55+ messages in thread
From: Matthias Brugger @ 2023-01-19 15:48 UTC (permalink / raw)
To: Garmin.Chang, Rob Herring, Krzysztof Kozlowski, Michael Turquette,
Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On 19/01/2023 13:48, Garmin.Chang wrote:
> Add MT8188 vppsys1 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-vpp1.c | 138 +++++++++++++++++++++++++
> 2 files changed, 139 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 48deecc6b520..37663de293bf 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> - clk-mt8188-vpp0.o
> + clk-mt8188-vpp0.o clk-mt8188-vpp1.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> new file mode 100644
> index 000000000000..2bff3a52c93f
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +#define GATE_VPP1_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP1_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp1_clks[] = {
> + /* VPP1_0 */
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
> + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
> + GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> + GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> + GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> + GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> + /* VPP1_1 */
> + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
> + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
> + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
> + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
> + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
> + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
> + GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
> + GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> + GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
> + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
> +};
> +
> +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> + if (r)
> + goto free_vpp1_data;
> +
> + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> + if (r)
> + goto unregister_gates;
> +
> + platform_set_drvdata(pdev, clk_data);
> +
> + return r;
> +
> +unregister_gates:
> + mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> +free_vpp1_data:
> + mtk_free_clk_data(clk_data);
> + return r;
> +}
> +
> +static int clk_mt8188_vpp1_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(node);
> + mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
> + mtk_free_clk_data(clk_data);
> +
> + return 0;
> +}
> +
> +static struct platform_driver clk_mt8188_vpp1_drv = {
> + .probe = clk_mt8188_vpp1_probe,
> + .remove = clk_mt8188_vpp1_remove,
> + .driver = {
> + .name = "clk-mt8188-vpp1",
> + },
> +};
> +builtin_platform_driver(clk_mt8188_vpp1_drv);
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support
2023-01-19 12:48 ` [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang
2023-01-19 15:48 ` Matthias Brugger
@ 2023-02-03 7:35 ` Chen-Yu Tsai
2023-03-09 3:21 ` Garmin Chang (張家銘)
1 sibling, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:35 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:58 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 vppsys1 clock controller which provides clock gate
> controller for Video Processor Pipe.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-vpp1.c | 138 +++++++++++++++++++++++++
> 2 files changed, 139 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 48deecc6b520..37663de293bf 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> - clk-mt8188-vpp0.o
> + clk-mt8188-vpp0.o clk-mt8188-vpp1.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> new file mode 100644
> index 000000000000..2bff3a52c93f
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +#define GATE_VPP1_0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VPP1_1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vpp1_clks[] = {
> + /* VPP1_0 */
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13),
> + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27),
> + GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> + GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> + GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> + GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> + /* VPP1_1 */
> + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0),
> + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5),
> + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7),
> + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10),
> + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11),
> + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12),
> + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13),
> + GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17),
> + GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> + GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20),
> + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21),
> + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26),
> +};
> +
> +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->parent->of_node;
> + struct clk_hw_onecell_data *clk_data;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + r = mtk_clk_register_gates(node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data);
Same here. Please update.
Once fixed,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 clock support
2023-02-03 7:35 ` Chen-Yu Tsai
@ 2023-03-09 3:21 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 3:21 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:35 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:58 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 vppsys1 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-vpp1.c | 138
> > +++++++++++++++++++++++++
> > 2 files changed, 139 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp1.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 48deecc6b520..37663de293bf 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > - clk-mt8188-vpp0.o
> > + clk-mt8188-vpp0.o clk-mt8188-
> > vpp1.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > new file mode 100644
> > index 000000000000..2bff3a52c93f
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp1_0_cg_regs = {
> > + .set_ofs = 0x104,
> > + .clr_ofs = 0x108,
> > + .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp1_1_cg_regs = {
> > + .set_ofs = 0x114,
> > + .clr_ofs = 0x118,
> > + .sta_ofs = 0x110,
> > +};
> > +
> > +#define GATE_VPP1_0(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP1_1(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp1_clks[] = {
> > + /* VPP1_0 */
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl",
> > "top_vpp", 0),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc",
> > "top_vpp", 1),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot",
> > "top_vpp", 2),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad",
> > "top_vpp", 3),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot",
> > "top_vpp", 4),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad",
> > "top_vpp", 5),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot",
> > "top_vpp", 6),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad",
> > "top_vpp", 7),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma",
> > "top_vpp", 8),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg",
> > "top_vpp", 9),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma",
> > "top_vpp", 10),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg",
> > "top_vpp", 11),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma",
> > "top_vpp", 12),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg",
> > "top_vpp", 13),
> > + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split",
> > "top_vpp", 14),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY,
> > "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz",
> > "top_vpp", 16),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP,
> > "vpp1_svpp1_mdp_tdshp", "top_vpp", 17),
> > + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR,
> > "vpp1_svpp1_mdp_color", "top_vpp", 18),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY,
> > "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz",
> > "top_vpp", 20),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE,
> > "vpp1_svpp2_vpp_merge", "top_vpp", 21),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP,
> > "vpp1_svpp2_mdp_tdshp", "top_vpp", 22),
> > + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR,
> > "vpp1_svpp2_mdp_color", "top_vpp", 23),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz",
> > "top_vpp", 24),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE,
> > "vpp1_svpp3_vpp_merge", "top_vpp", 25),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP,
> > "vpp1_svpp3_mdp_tdshp", "top_vpp", 26),
> > + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR,
> > "vpp1_svpp3_mdp_color", "top_vpp", 27),
> > + GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28),
> > + GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29),
> > + GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30),
> > + GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31),
> > + /* VPP1_1 */
> > + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr",
> > "top_vpp", 0),
> > + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal",
> > "top_vpp", 1),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr",
> > "top_vpp", 2),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal",
> > "top_vpp", 3),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr",
> > "top_vpp", 4),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal",
> > "top_vpp", 5),
> > + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex",
> > "top_vpp", 7),
> > + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY,
> > "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8),
> > + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY,
> > "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9),
> > + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async",
> > "top_vpp", 10),
> > + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay",
> > "top_vpp", 11),
> > + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng",
> > "top_vpp", 12),
> > + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng",
> > "top_vpp", 13),
> > + GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta",
> > "top_vpp", 16),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi",
> > "top_vpp", 17),
> > + GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18),
> > + GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp",
> > 19),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi",
> > "top_vpp", 20),
> > + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ",
> > "top_vpp", 21),
> > + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m",
> > "top_vpp", 26),
> > +};
> > +
> > +static int clk_mt8188_vpp1_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->parent->of_node;
> > + struct clk_hw_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_gates(node, vpp1_clks,
> > ARRAY_SIZE(vpp1_clks), clk_data);
>
> Same here. Please update.
Thank you for your suggestions.
OK. I'll moidfy it in v6.
>
> Once fixed,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (15 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 16/19] clk: mediatek: Add MT8188 vppsys1 " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:31 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper " Garmin.Chang
` (2 subsequent siblings)
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 wpesys clock controllers which provide clock gate
control in Wrapping Engine.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8188-wpe.c | 101 ++++++++++++++++++++++++++
2 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-wpe.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 37663de293bf..ed35546819a9 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -88,7 +88,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
- clk-mt8188-vpp0.o clk-mt8188-vpp1.o
+ clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-wpe.c b/drivers/clk/mediatek/clk-mt8188-wpe.c
new file mode 100644
index 000000000000..d104402ae80b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-wpe.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs wpe_top_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = {
+ .set_ofs = 0x58,
+ .clr_ofs = 0x58,
+ .sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = {
+ .set_ofs = 0x5c,
+ .clr_ofs = 0x5c,
+ .sta_ofs = 0x5c,
+};
+
+#define GATE_WPE_TOP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate wpe_top_clks[] = {
+ GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16),
+ GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18),
+ GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20),
+ GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24),
+};
+
+static const struct mtk_gate wpe_vpp0_clks[] = {
+ /* WPE_VPP00 */
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16),
+ GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17),
+ /* WPE_VPP0_1 */
+ GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0),
+ GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1),
+ GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2),
+ GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3),
+ GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4),
+};
+
+static const struct mtk_clk_desc wpe_top_desc = {
+ .clks = wpe_top_clks,
+ .num_clks = ARRAY_SIZE(wpe_top_clks),
+};
+
+static const struct mtk_clk_desc wpe_vpp0_desc = {
+ .clks = wpe_vpp0_clks,
+ .num_clks = ARRAY_SIZE(wpe_vpp0_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_wpe[] = {
+ { .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc },
+ { .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_wpe_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-wpe",
+ .of_match_table = of_match_clk_mt8188_wpe,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_wpe_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys clock support
2023-01-19 12:48 ` [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys " Garmin.Chang
@ 2023-02-03 7:31 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:31 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 wpesys clock controllers which provide clock gate
> control in Wrapping Engine.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (16 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 17/19] clk: mediatek: Add MT8188 wpesys " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:36 ` Chen-Yu Tsai
2023-01-19 12:48 ` [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp " Garmin.Chang
2023-02-03 6:23 ` [PATCH v5 00/19] MediaTek MT8188 " Chen-Yu Tsai
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 imp i2c wrapper clock controllers which provide clock gate
control in I2C IP blocks.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 3 +-
.../clk/mediatek/clk-mt8188-imp_iic_wrap.c | 78 +++++++++++++++++++
2 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ed35546819a9..8befaedfdd3d 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -88,7 +88,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-cam.o clk-mt8188-ccu.o clk-mt8188-img.o \
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
- clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o
+ clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o \
+ clk-mt8188-imp_iic_wrap.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c
new file mode 100644
index 000000000000..e9b951f95fba
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
+ .set_ofs = 0xe08,
+ .clr_ofs = 0xe04,
+ .sta_ofs = 0xe00,
+};
+
+#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imp_iic_wrap_c_clks[] = {
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0,
+ "imp_iic_wrap_c_ap_clock_i2c0", "top_i2c", 0),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2,
+ "imp_iic_wrap_c_ap_clock_i2c2", "top_i2c", 1),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3,
+ "imp_iic_wrap_c_ap_clock_i2c3", "top_i2c", 2),
+};
+
+static const struct mtk_gate imp_iic_wrap_w_clks[] = {
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1,
+ "imp_iic_wrap_w_ap_clock_i2c1", "top_i2c", 0),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4,
+ "imp_iic_wrap_w_ap_clock_i2c4", "top_i2c", 1),
+};
+
+static const struct mtk_gate imp_iic_wrap_en_clks[] = {
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5,
+ "imp_iic_wrap_en_ap_clock_i2c5", "top_i2c", 0),
+ GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6,
+ "imp_iic_wrap_en_ap_clock_i2c6", "top_i2c", 1),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
+ .clks = imp_iic_wrap_c_clks,
+ .num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
+ .clks = imp_iic_wrap_w_clks,
+ .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_en_desc = {
+ .clks = imp_iic_wrap_en_clks,
+ .num_clks = ARRAY_SIZE(imp_iic_wrap_en_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_imp_iic_wrap[] = {
+ { .compatible = "mediatek,mt8188-imp-iic-wrap-c", .data = &imp_iic_wrap_c_desc },
+ { .compatible = "mediatek,mt8188-imp-iic-wrap-w", .data = &imp_iic_wrap_w_desc },
+ { .compatible = "mediatek,mt8188-imp-iic-wrap-en", .data = &imp_iic_wrap_en_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_imp_iic_wrap_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-imp_iic_wrap",
+ .of_match_table = of_match_clk_mt8188_imp_iic_wrap,
+ },
+};
+
+builtin_platform_driver(clk_mt8188_imp_iic_wrap_drv);
+MODULE_LICENSE("GPL");
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper clock support
2023-01-19 12:48 ` [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper " Garmin.Chang
@ 2023-02-03 7:36 ` Chen-Yu Tsai
0 siblings, 0 replies; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:36 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 imp i2c wrapper clock controllers which provide clock gate
> control in I2C IP blocks.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (17 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 18/19] clk: mediatek: Add MT8188 imp i2c wrapper " Garmin.Chang
@ 2023-01-19 12:48 ` Garmin.Chang
2023-02-03 7:39 ` Chen-Yu Tsai
2023-02-03 6:23 ` [PATCH v5 00/19] MediaTek MT8188 " Chen-Yu Tsai
19 siblings, 1 reply; 55+ messages in thread
From: Garmin.Chang @ 2023-01-19 12:48 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev,
Garmin.Chang
Add MT8188 adsp clock controller which provides clock gate
control for Audio DSP.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
---
drivers/clk/mediatek/Makefile | 2 +-
.../clk/mediatek/clk-mt8188-adsp_audio26m.c | 45 +++++++++++++++++++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 8befaedfdd3d..b56ae9bee1d8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -89,7 +89,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o \
- clk-mt8188-imp_iic_wrap.o
+ clk-mt8188-imp_iic_wrap.o clk-mt8188-adsp_audio26m.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
new file mode 100644
index 000000000000..f91381a1316c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2022 MediaTek Inc.
+// Author: Garmin Chang <garmin.chang@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x80,
+};
+
+#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr, CLK_IGNORE_UNUSED)
+
+static const struct mtk_gate adsp_audio26m_clks[] = {
+ GATE_ADSP_FLAGS(CLK_AUDIODSP_AUDIO26M, "audiodsp_audio26m", "clk26m", 3),
+};
+
+static const struct mtk_clk_desc adsp_audio26m_desc = {
+ .clks = adsp_audio26m_clks,
+ .num_clks = ARRAY_SIZE(adsp_audio26m_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8188_adsp_audio26m[] = {
+ { .compatible = "mediatek,mt8188-adsp-audio26m", .data = &adsp_audio26m_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8188_adsp_audio26m_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8188-adsp_audio26m",
+ .of_match_table = of_match_clk_mt8188_adsp_audio26m,
+ },
+};
+builtin_platform_driver(clk_mt8188_adsp_audio26m_drv);
--
2.18.0
^ permalink raw reply related [flat|nested] 55+ messages in thread* Re: [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp clock support
2023-01-19 12:48 ` [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp " Garmin.Chang
@ 2023-02-03 7:39 ` Chen-Yu Tsai
2023-03-09 3:17 ` Garmin Chang (張家銘)
0 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 7:39 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 9:02 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Add MT8188 adsp clock controller which provides clock gate
> control for Audio DSP.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> .../clk/mediatek/clk-mt8188-adsp_audio26m.c | 45 +++++++++++++++++++
> 2 files changed, 46 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 8befaedfdd3d..b56ae9bee1d8 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -89,7 +89,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o
> clk-mt8188-ipe.o clk-mt8188-mfg.o clk-mt8188-vdec.o \
> clk-mt8188-vdo0.o clk-mt8188-vdo1.o clk-mt8188-venc.o \
> clk-mt8188-vpp0.o clk-mt8188-vpp1.o clk-mt8188-wpe.o \
> - clk-mt8188-imp_iic_wrap.o
> + clk-mt8188-imp_iic_wrap.o clk-mt8188-adsp_audio26m.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> new file mode 100644
> index 000000000000..f91381a1316c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
> + .set_ofs = 0x80,
> + .clr_ofs = 0x80,
> + .sta_ofs = 0x80,
> +};
> +
> +#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr, CLK_IGNORE_UNUSED)
Why CLK_IGNORE_UNUSED?
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp clock support
2023-02-03 7:39 ` Chen-Yu Tsai
@ 2023-03-09 3:17 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 3:17 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 15:39 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 9:02 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Add MT8188 adsp clock controller which provides clock gate
> > control for Audio DSP.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > .../clk/mediatek/clk-mt8188-adsp_audio26m.c | 45
> > +++++++++++++++++++
> > 2 files changed, 46 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 8befaedfdd3d..b56ae9bee1d8 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -89,7 +89,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > clk-mt8188-vpp0.o clk-mt8188-
> > vpp1.o clk-mt8188-wpe.o \
> > - clk-mt8188-imp_iic_wrap.o
> > + clk-mt8188-imp_iic_wrap.o clk-
> > mt8188-adsp_audio26m.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > new file mode 100644
> > index 000000000000..f91381a1316c
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs adsp_audio26m_cg_regs = {
> > + .set_ofs = 0x80,
> > + .clr_ofs = 0x80,
> > + .sta_ofs = 0x80,
> > +};
> > +
> > +#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \
> > + GATE_MTK_FLAGS(_id, _name, _parent, &adsp_audio26m_cg_regs,
> > _shift, \
> > + &mtk_clk_gate_ops_no_setclr, CLK_IGNORE_UNUSED)
>
> Why CLK_IGNORE_UNUSED?
Thank you for your review.
Because ADSP_INFRA is always on, it is unnecessary to add
CLK_IGNORE_UNUSED now. I wiil remove it in v6. Please see commit
https://patchwork.kernel.org/project/linux-mediatek/patch/20221223080553.9397-3-Garmin.Chang@mediatek.com/
Add ignore_unused before to avoid "ADSP_INFRA is turned off". If
ADSP_INFRA is turned off, accessing registers will cause the system to
hang.
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PATCH v5 00/19] MediaTek MT8188 clock support
2023-01-19 12:48 [PATCH v5 00/19] MediaTek MT8188 clock support Garmin.Chang
` (18 preceding siblings ...)
2023-01-19 12:48 ` [PATCH v5 19/19] clk: mediatek: Add MT8188 adsp " Garmin.Chang
@ 2023-02-03 6:23 ` Chen-Yu Tsai
2023-03-09 2:55 ` Garmin Chang (張家銘)
19 siblings, 1 reply; 55+ messages in thread
From: Chen-Yu Tsai @ 2023-02-03 6:23 UTC (permalink / raw)
To: Garmin.Chang
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Michael Turquette, Stephen Boyd, Richard Cochran,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, linux-clk, netdev
On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <Garmin.Chang@mediatek.com> wrote:
>
> Base on tag: next-20230119, linux-next/master
There are some recent changes to the MediaTek clk driver library
that makes this series incompatible. Could you rebase onto next-202302xx
and send a new version?
Thanks
^ permalink raw reply [flat|nested] 55+ messages in thread* Re: [PATCH v5 00/19] MediaTek MT8188 clock support
2023-02-03 6:23 ` [PATCH v5 00/19] MediaTek MT8188 " Chen-Yu Tsai
@ 2023-03-09 2:55 ` Garmin Chang (張家銘)
0 siblings, 0 replies; 55+ messages in thread
From: Garmin Chang (張家銘) @ 2023-03-09 2:55 UTC (permalink / raw)
To: wenst@chromium.org
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mturquette@baylibre.com, devicetree@vger.kernel.org,
sboyd@kernel.org, linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group, richardcochran@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
linux-clk@vger.kernel.org, netdev@vger.kernel.org
On Fri, 2023-02-03 at 14:23 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:49 PM Garmin.Chang <
> Garmin.Chang@mediatek.com> wrote:
> >
> > Base on tag: next-20230119, linux-next/master
>
> There are some recent changes to the MediaTek clk driver library
> that makes this series incompatible. Could you rebase onto next-
> 202302xx
> and send a new version?
>
> Thanks
OK. I'll rebase onto next 202303xx, thanks.
^ permalink raw reply [flat|nested] 55+ messages in thread