[PATCH v1] ufs: core: Change MCQ interrupt enable flow

[PATCH v1] ufs: core: Change MCQ interrupt enable flow

[peter.wang]

From: Peter Wang <peter.wang@mediatek.com>

Move the MCQ interrupt enable process to
ufshcd_mcq_make_queues_operational to ensure that interrupts
are set correctly when making queues operational, similar to
ufshcd_make_hba_operational. This change addresses the issue
where ufshcd_mcq_make_queues_operational was not fully
operational due to missing interrupt enablement.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/core/ufs-mcq.c | 11 +++++++++++
 drivers/ufs/core/ufshcd.c  | 13 ++-----------
 include/ufs/ufshcd.h       |  1 +
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c
index cc88aaa106da..c9bdd4140fd0 100644
--- a/drivers/ufs/core/ufs-mcq.c
+++ b/drivers/ufs/core/ufs-mcq.c
@@ -29,6 +29,10 @@
 #define MCQ_ENTRY_SIZE_IN_DWORD	8
 #define CQE_UCD_BA GENMASK_ULL(63, 7)
 
+#define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\
+				 UFSHCD_ERROR_MASK |\
+				 MCQ_CQ_EVENT_STATUS)
+
 /* Max mcq register polling time in microseconds */
 #define MCQ_POLL_US 500000
 
@@ -355,9 +359,16 @@ EXPORT_SYMBOL_GPL(ufshcd_mcq_poll_cqe_lock);
 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba)
 {
 	struct ufs_hw_queue *hwq;
+	u32 intrs;
 	u16 qsize;
 	int i;
 
+	/* Enable required interrupts */
+	intrs = UFSHCD_ENABLE_MCQ_INTRS;
+	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
+		intrs &= ~MCQ_CQ_EVENT_STATUS;
+	ufshcd_enable_intr(hba, intrs);
+
 	for (i = 0; i < hba->nr_hw_queues; i++) {
 		hwq = &hba->uhq[i];
 		hwq->id = i;
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 0735bd5df1cc..585d56e04daf 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -45,11 +45,6 @@
 				 UTP_TASK_REQ_COMPL |\
 				 UFSHCD_ERROR_MASK)
 
-#define UFSHCD_ENABLE_MCQ_INTRS	(UTP_TASK_REQ_COMPL |\
-				 UFSHCD_ERROR_MASK |\
-				 MCQ_CQ_EVENT_STATUS)
-
-
 /* UIC command timeout, unit: ms */
 enum {
 	UIC_CMD_TIMEOUT_DEFAULT	= 500,
@@ -369,7 +364,7 @@ EXPORT_SYMBOL_GPL(ufshcd_disable_irq);
  * @hba: per adapter instance
  * @intrs: interrupt bits
  */
-static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
+void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
 {
 	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
 	u32 new_val = old_val | intrs;
@@ -377,6 +372,7 @@ static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
 	if (new_val != old_val)
 		ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
 }
+EXPORT_SYMBOL_GPL(ufshcd_enable_intr);
 
 /**
  * ufshcd_disable_intr - disable interrupts
@@ -8927,16 +8923,11 @@ static int ufshcd_alloc_mcq(struct ufs_hba *hba)
 static void ufshcd_config_mcq(struct ufs_hba *hba)
 {
 	int ret;
-	u32 intrs;
 
 	ret = ufshcd_mcq_vops_config_esi(hba);
 	hba->mcq_esi_enabled = !ret;
 	dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
 
-	intrs = UFSHCD_ENABLE_MCQ_INTRS;
-	if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
-		intrs &= ~MCQ_CQ_EVENT_STATUS;
-	ufshcd_enable_intr(hba, intrs);
 	ufshcd_mcq_make_queues_operational(hba);
 	ufshcd_mcq_config_mac(hba, hba->nutrs);
 
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index ea0021f067c9..d8e06de0afbb 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1292,6 +1292,7 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
 
 void ufshcd_enable_irq(struct ufs_hba *hba);
 void ufshcd_disable_irq(struct ufs_hba *hba);
+void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs);
 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
 int ufshcd_hba_enable(struct ufs_hba *hba);
 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
-- 
2.45.2

Re: [PATCH v1] ufs: core: Change MCQ interrupt enable flow

[Bart Van Assche]

On 9/23/25 2:08 AM, peter.wang@mediatek.com wrote:
> -static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
> +void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
>   {
>   	u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
>   	u32 new_val = old_val | intrs;
> @@ -377,6 +372,7 @@ static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
>   	if (new_val != old_val)
>   		ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
>   }
> +EXPORT_SYMBOL_GPL(ufshcd_enable_intr);

Please do not export ufshcd_enable_intr() - this function should not be
called from outside the UFS driver core.

Thanks,

Bart.

Re: [PATCH v1] ufs: core: Change MCQ interrupt enable flow

[Peter Wang (王信友)]

On Tue, 2025-09-23 at 08:54 -0700, Bart Van Assche wrote:
> 
> On 9/23/25 2:08 AM, peter.wang@mediatek.com wrote:
> > -static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
> > +void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
> >   {
> >       u32 old_val = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
> >       u32 new_val = old_val | intrs;
> > @@ -377,6 +372,7 @@ static void ufshcd_enable_intr(struct ufs_hba
> > *hba, u32 intrs)
> >       if (new_val != old_val)
> >               ufshcd_writel(hba, new_val, REG_INTERRUPT_ENABLE);
> >   }
> > +EXPORT_SYMBOL_GPL(ufshcd_enable_intr);
> 
> Please do not export ufshcd_enable_intr() - this function should not
> be
> called from outside the UFS driver core.
> 
> Thanks,
> 
> Bart.

Hi Bart,

Okay, I will remove this next version.

Thanks.
Peter