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From: <peter.wang@mediatek.com>
To: <linux-scsi@vger.kernel.org>, <martin.petersen@oracle.com>
Cc: <wsd_upstream@mediatek.com>, <linux-mediatek@lists.infradead.org>,
	<peter.wang@mediatek.com>, <chun-hung.wu@mediatek.com>,
	<alice.chao@mediatek.com>, <cc.chou@mediatek.com>,
	<chaotian.jing@mediatek.com>, <jiajie.hao@mediatek.com>,
	<yi-fan.peng@mediatek.com>, <qilin.tan@mediatek.com>,
	<lin.gui@mediatek.com>, <tun-yu.yu@mediatek.com>,
	<eddie.huang@mediatek.com>, <naomi.chu@mediatek.com>,
	<ed.tsai@mediatek.com>, <bvanassche@acm.org>
Subject: [PATCH v2 1/8] ufs: host: mediatek: Correct clock scaling with PM QoS flow
Date: Wed, 24 Sep 2025 17:43:23 +0800	[thread overview]
Message-ID: <20250924094527.2992256-2-peter.wang@mediatek.com> (raw)
In-Reply-To: <20250924094527.2992256-1-peter.wang@mediatek.com>

From: Peter Wang <peter.wang@mediatek.com>

Correct clock scaling with PM QoS during suspend and resume.
Ensure PM QoS is released during suspend if scaling up and
re-applied after resume. This prevents performance issues
and maintains proper power management.

Signed-off-by: Peter Wang <peter.wang@mediatek.com>
---
 drivers/ufs/core/ufshcd.c       |  3 ++-
 drivers/ufs/host/ufs-mediatek.c | 10 ++++++++++
 include/ufs/ufshcd.h            |  1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index c9eb89dccd1e..436e2a16363c 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -1075,13 +1075,14 @@ void ufshcd_pm_qos_exit(struct ufs_hba *hba)
  * @hba: per adapter instance
  * @on: If True, vote for perf PM QoS mode otherwise power save mode
  */
-static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
+void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
 {
 	if (!hba->pm_qos_enabled)
 		return;
 
 	cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE);
 }
+EXPORT_SYMBOL_GPL(ufshcd_pm_qos_update);
 
 /**
  * ufshcd_set_clk_freq - set UFS controller clock frequencies
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 758a393a9de1..009031fee744 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1744,6 +1744,7 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
 {
 	int err;
 	struct arm_smccc_res res;
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
 	if (status == PRE_CHANGE) {
 		if (ufshcd_is_auto_hibern8_supported(hba))
@@ -1773,6 +1774,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
 
 	ufs_mtk_sram_pwr_ctrl(false, res);
 
+	/* Release pm_qos if in scale-up mode during suspend */
+	if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up))
+		ufshcd_pm_qos_update(hba, false);
+
 	return 0;
 fail:
 	/*
@@ -1788,6 +1793,7 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 {
 	int err;
 	struct arm_smccc_res res;
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
 	if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
 		ufs_mtk_dev_vreg_set_lpm(hba, false);
@@ -1798,6 +1804,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 	if (err)
 		goto fail;
 
+	/* Request pm_qos if in scale-up mode after resume */
+	if (ufshcd_is_clkscaling_supported(hba) && (host->clk_scale_up))
+		ufshcd_pm_qos_update(hba, true);
+
 	if (ufshcd_is_link_hibern8(hba)) {
 		err = ufs_mtk_link_set_hpm(hba);
 		if (err)
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index ea0021f067c9..53b837b024ce 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1483,5 +1483,6 @@ int ufshcd_write_ee_control(struct ufs_hba *hba);
 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
 			     const u16 *other_mask, u16 set, u16 clr);
 void ufshcd_force_error_recovery(struct ufs_hba *hba);
+void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on);
 
 #endif /* End of Header */
-- 
2.45.2



  reply	other threads:[~2025-09-24  9:45 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-24  9:43 [PATCH v2 0/8] Enhance UFS Mediatek Driver peter.wang
2025-09-24  9:43 ` peter.wang [this message]
2025-09-24 21:56   ` [PATCH v2 1/8] ufs: host: mediatek: Correct clock scaling with PM QoS flow Bart Van Assche
2025-09-24  9:43 ` [PATCH v2 2/8] ufs: host: mediatek: Adjust clock scaling for PM flow peter.wang
2025-09-24  9:43 ` [PATCH v2 3/8] ufs: host: mediatek: Handle clock scaling for high gear in " peter.wang
2025-09-24  9:43 ` [PATCH v2 4/8] ufs: host: mediatek: Adjust sync length for FASTAUTO mode peter.wang
2025-09-24 21:56   ` Bart Van Assche
2025-09-24  9:43 ` [PATCH v2 5/8] ufs: host: mediatek: Fix shutdown/suspend race condition peter.wang
2025-09-24  9:43 ` [PATCH v2 6/8] ufs: host: mediatek: Remove duplicate function peter.wang
2025-09-24  9:43 ` [PATCH v2 7/8] ufs: host: mediatek: Add support for new platform with MMIO_OTSD_CTR peter.wang
2025-09-24  9:43 ` [PATCH v2 8/8] ufs: host: mediatek: Support new feature for MT6991 peter.wang
2025-09-30 12:54 ` [PATCH v2 0/8] Enhance UFS Mediatek Driver Chun-Hung Wu (巫駿宏)
2025-10-08  7:31 ` Peter Wang (王信友)
2025-10-08 16:15   ` Bart Van Assche
2025-10-22  1:56 ` Martin K. Petersen

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