* reenabling interrupts on return from function
@ 2002-06-15 21:49 Justin Carlson
2002-06-15 22:22 ` Justin Carlson
0 siblings, 1 reply; 3+ messages in thread
From: Justin Carlson @ 2002-06-15 21:49 UTC (permalink / raw)
To: linux-mips
I'm obviously missing something basic here.
Looking at stackframe.h, I see this code as a part of RESTORE_SOME
mfc0 t0, CP0_STATUS; \
.set pop; \
ori t0, 0x1f; \
xori t0, 0x1f; \
mtc0 t0, CP0_STATUS;
Here, we're explicitly clearing the IE bit (among others) in the status
register, and we leave it cleared. The status register is not touched
again until we do an eret.
First, why do we explicitly clear the IE bit, when we're running with
the EXL bit set? And where is the black magic that is re-enabling
interrupts for the return to usermode?
I must be missing something really fundamental here. Anyone care to
point out my obvious gaps of knowledge? :)
Thanks,
Justin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: reenabling interrupts on return from function
2002-06-15 21:49 reenabling interrupts on return from function Justin Carlson
@ 2002-06-15 22:22 ` Justin Carlson
2002-06-19 15:16 ` Maciej W. Rozycki
0 siblings, 1 reply; 3+ messages in thread
From: Justin Carlson @ 2002-06-15 22:22 UTC (permalink / raw)
To: Justin Carlson; +Cc: linux-mips
On Sat, 2002-06-15 at 14:49, Justin Carlson wrote:
> I'm obviously missing something basic here.
>
> Looking at stackframe.h, I see this code as a part of RESTORE_SOME
>
>
> mfc0 t0, CP0_STATUS; \
> .set pop; \
> ori t0, 0x1f; \
> xori t0, 0x1f; \
> mtc0 t0, CP0_STATUS;
>
OK, this was a stupid question; the answer was staring me in the face
(the restoration of the status register from the stack), and I didn't
see it.
However, I still don't see the point of the above code. Why do we
explicitly clear bits 4-0 of the status register just before reloading
it from the system stack?
-Justin
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: reenabling interrupts on return from function
2002-06-15 22:22 ` Justin Carlson
@ 2002-06-19 15:16 ` Maciej W. Rozycki
0 siblings, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2002-06-19 15:16 UTC (permalink / raw)
To: Justin Carlson; +Cc: linux-mips
On 15 Jun 2002, Justin Carlson wrote:
> However, I still don't see the point of the above code. Why do we
> explicitly clear bits 4-0 of the status register just before reloading
> it from the system stack?
Not to receive an interrupt in the middle of register restoration.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
^ permalink raw reply [flat|nested] 3+ messages in thread
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