* [Q]: Was this chunk of a patch really intended?
@ 2002-08-16 9:35 Jan-Benedict Glaw
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From: Jan-Benedict Glaw @ 2002-08-16 9:35 UTC (permalink / raw)
To: linux-mips mailing list
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Hi!
I'm once again looking at R4k6 V1.7 support. Diffing out the patch which
removed V1.7 support, I find this chunk:
---------------------------------------------------------------------------
@@ -1010,14 +921,12 @@
blast_dcache32_page_indexed(page);
}
out:
- __restore_flags(flags);
}
static void r4k_flush_cache_page_d32i32_r4600(struct vm_area_struct *vma,
unsigned long page)
{
struct mm_struct *mm = vma->vm_mm;
- unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
@@ -1032,7 +941,6 @@
#ifdef DEBUG_CACHE
printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
- __save_and_cli(flags);
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pmdp = pmd_offset(pgdp, page);
@@ -1062,7 +970,6 @@
blast_dcache32_page_indexed(page ^ dcache_waybit);
}
out:
- __restore_flags(flags);
}
/* If the addresses passed to these routines are valid, they are
---------------------------------------------------------------------------
Depending on this function's name, I think this part of the patch is not
that shiny. I'd suspect to leave __save_and_cli()/__restore_flags() in
this function, or to rename the function, as it used for more than only
R4600:
--------------------------------------------------------------------------
switch(mips_cpu.cputype) {
case CPU_R4600: /* QED style two way caches? */
case CPU_R4700:
case CPU_R5000:
case CPU_NEVADA:
_flush_cache_page = r4k_flush_cache_page_d32i32_r4600;
}
--------------------------------------------------------------------------
MfG, JBG
--
Jan-Benedict Glaw . jbglaw@lug-owl.de . +49-172-7608481
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