* [patch] Cobalt IRQ handler CP0 interlock?
@ 2003-02-20 17:31 Maciej W. Rozycki
2003-02-20 18:53 ` Ralf Baechle
0 siblings, 1 reply; 6+ messages in thread
From: Maciej W. Rozycki @ 2003-02-20 17:31 UTC (permalink / raw)
To: Ralf Baechle, linux-mips
Hello,
Does Cobalt have a processor that implements its pipeline differently or
interlocks on CP0 loads? If not, I'll apply the following fix.
Maciej
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
patch-mips-2.4.20-20030214-cobalt-int-0
diff -up --recursive --new-file linux-mips-2.4.20-20030214.macro/arch/mips/cobalt/int-handler.S linux-mips-2.4.20-20030214/arch/mips/cobalt/int-handler.S
--- linux-mips-2.4.20-20030214.macro/arch/mips/cobalt/int-handler.S 2003-01-28 03:56:27.000000000 +0000
+++ linux-mips-2.4.20-20030214/arch/mips/cobalt/int-handler.S 2003-02-15 10:28:15.000000000 +0000
@@ -31,6 +31,7 @@
*/
mfc0 s0,CP0_CAUSE # get raw irq status
mfc0 a0,CP0_STATUS # get irq mask
+ nop
and s0,s0,a0 # compute masked irq status
andi a0,s0,CAUSEF_IP2 /* Check for Galileo timer */
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [patch] Cobalt IRQ handler CP0 interlock?
2003-02-20 17:31 [patch] Cobalt IRQ handler CP0 interlock? Maciej W. Rozycki
@ 2003-02-20 18:53 ` Ralf Baechle
2003-02-21 12:11 ` Maciej W. Rozycki
0 siblings, 1 reply; 6+ messages in thread
From: Ralf Baechle @ 2003-02-20 18:53 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips
On Thu, Feb 20, 2003 at 06:31:02PM +0100, Maciej W. Rozycki wrote:
> Does Cobalt have a processor that implements its pipeline differently or
> interlocks on CP0 loads? If not, I'll apply the following fix.
Mfc0 doesn't need a nops on any R4000 class CPU I know of.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [patch] Cobalt IRQ handler CP0 interlock?
2003-02-20 18:53 ` Ralf Baechle
@ 2003-02-21 12:11 ` Maciej W. Rozycki
2003-02-21 12:23 ` Ralf Baechle
0 siblings, 1 reply; 6+ messages in thread
From: Maciej W. Rozycki @ 2003-02-21 12:11 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips
On Thu, 20 Feb 2003, Ralf Baechle wrote:
> > Does Cobalt have a processor that implements its pipeline differently or
> > interlocks on CP0 loads? If not, I'll apply the following fix.
>
> Mfc0 doesn't need a nops on any R4000 class CPU I know of.
Well, my MIPS R4k manual is vague on this matter and my IDT software
manual for R3k, R4k, R5k is even explicit on the load delay slot of mfc0.
But a run-time test proves otherwise.
I stand corrected then unless someone finds a counter-example.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [patch] Cobalt IRQ handler CP0 interlock?
2003-02-21 12:11 ` Maciej W. Rozycki
@ 2003-02-21 12:23 ` Ralf Baechle
2003-02-21 12:41 ` Maciej W. Rozycki
0 siblings, 1 reply; 6+ messages in thread
From: Ralf Baechle @ 2003-02-21 12:23 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips
On Fri, Feb 21, 2003 at 01:11:58PM +0100, Maciej W. Rozycki wrote:
> > > Does Cobalt have a processor that implements its pipeline differently or
> > > interlocks on CP0 loads? If not, I'll apply the following fix.
> >
> > Mfc0 doesn't need a nops on any R4000 class CPU I know of.
>
> Well, my MIPS R4k manual is vague on this matter and my IDT software
> manual for R3k, R4k, R5k is even explicit on the load delay slot of mfc0.
> But a run-time test proves otherwise.
>
> I stand corrected then unless someone finds a counter-example.
All I can say it's working fine like this since 1984 for R4000 class CPUs.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [patch] Cobalt IRQ handler CP0 interlock?
2003-02-21 12:23 ` Ralf Baechle
@ 2003-02-21 12:41 ` Maciej W. Rozycki
2003-02-21 12:46 ` Ralf Baechle
0 siblings, 1 reply; 6+ messages in thread
From: Maciej W. Rozycki @ 2003-02-21 12:41 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips
On Fri, 21 Feb 2003, Ralf Baechle wrote:
> All I can say it's working fine like this since 1984 for R4000 class CPUs.
You meant something like "since 1991", I suppose. Even R2000 is there
since 1986 only. ;-)
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [patch] Cobalt IRQ handler CP0 interlock?
2003-02-21 12:41 ` Maciej W. Rozycki
@ 2003-02-21 12:46 ` Ralf Baechle
0 siblings, 0 replies; 6+ messages in thread
From: Ralf Baechle @ 2003-02-21 12:46 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: linux-mips
On Fri, Feb 21, 2003 at 01:41:16PM +0100, Maciej W. Rozycki wrote:
> > All I can say it's working fine like this since 1984 for R4000 class CPUs.
>
> You meant something like "since 1991", I suppose. Even R2000 is there
> since 1986 only. ;-)
Typo. I actually meant 1994, the year in which I started working with MIPS
and on Linux/MIPS at that time on R4400.
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
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2003-02-20 17:31 [patch] Cobalt IRQ handler CP0 interlock? Maciej W. Rozycki
2003-02-20 18:53 ` Ralf Baechle
2003-02-21 12:11 ` Maciej W. Rozycki
2003-02-21 12:23 ` Ralf Baechle
2003-02-21 12:41 ` Maciej W. Rozycki
2003-02-21 12:46 ` Ralf Baechle
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