Re: way selection bit for multi-way cache

["Mike Uhler" <uhler@mips.com>]

> On Thu, Apr 10, 2003 at 11:50:53AM -0700, Mike Uhler wrote:
> 
> > I can't comment on anything but MIPS32 and MIPS64 CPUs, but the
> > MIPS32 and MIPS64 standard is to use the bits above the index field
> > to specify the way.  See the figure entitled "Usage of Address Fields
> > to Select Index and Way" in the CACHE instruction description of the
> > MIPS32 and MIPS64 Architecture for Programmer's manuals.
> 
> The question came up between Jun and me when revising the way of handling
> multi-way caches.  There is the MIPS32 / MIPS64 way of selecting the
> cache way - but that scheme was originally already introduced by the
> R4600.  The second somewhat less common scheme is using the lowest bits
> of the address.  That was originally introduced with the R10000 but a
> few other processors such as the R5432 and the TX49 series are using it
> as well.  Unfortunately there has been way to much creativity (usually
> a positive property but ...) among designers so this posting is an
> attempt to achieve completeness.
> 
>   Ralf

Exactly why we made it a standard in MIPS32 and MIPS64.
-- 

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