[PATCH 2.6.X] Fix Cobalt PCI cache line sizes

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* [PATCH 2.6.X] Fix Cobalt PCI cache line sizes
@ 2006-01-29 21:33 Peter Horton
  2006-01-30  4:02 ` Ralf Baechle
  0 siblings, 1 reply; 2+ messages in thread
From: Peter Horton @ 2006-01-29 21:33 UTC (permalink / raw)
  To: linux-mips; +Cc: ralf

Correct cache line sizes.

P.

Index: linux.git/arch/mips/pci/fixup-cobalt.c
===================================================================
--- linux.git.orig/arch/mips/pci/fixup-cobalt.c	2006-01-29 12:35:50.000000000 +0000
+++ linux.git/arch/mips/pci/fixup-cobalt.c	2006-01-29 12:36:59.000000000 +0000
@@ -52,7 +52,7 @@
 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
 	if (lt < 64)
 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
@@ -69,7 +69,7 @@
 	 * host bridge.
 	 */
 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 
 	/*
 	 * The code described by the comment below has been removed

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH 2.6.X] Fix Cobalt PCI cache line sizes
  2006-01-29 21:33 [PATCH 2.6.X] Fix Cobalt PCI cache line sizes Peter Horton
@ 2006-01-30  4:02 ` Ralf Baechle
  0 siblings, 0 replies; 2+ messages in thread
From: Ralf Baechle @ 2006-01-30  4:02 UTC (permalink / raw)
  To: Peter Horton; +Cc: linux-mips

On Sun, Jan 29, 2006 at 09:33:48PM +0000, Peter Horton wrote:

> Correct cache line sizes.

Thanks, applied.

  Ralf

PS: If you would please add the Signed-off-by lines also in the future.

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2006-01-29 21:33 [PATCH 2.6.X] Fix Cobalt PCI cache line sizes Peter Horton
2006-01-30  4:02 ` Ralf Baechle

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