[PATCH] [MIPS] Fixed PCI resource fixup

[PATCH] [MIPS] Fixed PCI resource fixup

[Yoichi Yuasa]

Hi Ralf,

This patch has fixed IDE resources problem about Cobalt.

pcibios_fixup_device_resources() changes non-movable resources.
It cannot be changed if there is IORESOURCE_PCI_FIXED in the resource flags. 

Yoichi

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/pci/pci.c mips/arch/mips/pci/pci.c
--- mips-orig/arch/mips/pci/pci.c	2006-12-18 15:53:10.735222250 +0900
+++ mips/arch/mips/pci/pci.c	2006-12-18 15:56:59.805538250 +0900
@@ -232,7 +232,8 @@ static void __init pcibios_fixup_device_
 	int i;
 
 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-		if (!dev->resource[i].start)
+		if (!dev->resource[i].start ||
+		    dev->resource[i].flags & IORESOURCE_PCI_FIXED)
 			continue;
 		if (dev->resource[i].flags & IORESOURCE_IO)
 			offset = hose->io_offset;

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Ralf Baechle]

On Thu, Jan 11, 2007 at 02:55:58PM +0900, Yoichi Yuasa wrote:

> This patch has fixed IDE resources problem about Cobalt.
> 
> pcibios_fixup_device_resources() changes non-movable resources.
> It cannot be changed if there is IORESOURCE_PCI_FIXED in the resource flags. 

<Ralf> anemo: Have you seen Yoichi's patch?
<anemo> Ralf: yes, but I could not see why ...  My impression is IORESOURCE_PCI_FIXED and io_offset adjustment is irrerevant.
<Ralf> This whole fixup thing is really meant to handle machines where there is an offset between PCI bus addresses and CPU physical addresses.
<Ralf> And that exists regardless of IORESOURCE_PCI_FIXED
<anemo> I thought so too.  So I can not see why youichi's patch fix something.
<Ralf> This may be the explanation:
<Ralf> static struct pci_controller cobalt_pci_controller = {
<Ralf>         .pci_ops        = &gt64111_pci_ops,
<Ralf>         .mem_resource   = &cobalt_mem_resource,
<Ralf>         .mem_offset     = 0,
<Ralf>         .io_resource    = &cobalt_io_resource,
<Ralf>         .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
<Ralf> };
<Ralf> I think he should have io_offset = 0.

Which is what other GT-64120 platforms are using, so I wonder why that is
different on Cobalt.

  Ralf

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Yoichi Yuasa]

On Thu, 11 Jan 2007 14:31:16 +0000
Ralf Baechle <ralf@linux-mips.org> wrote:

> On Thu, Jan 11, 2007 at 02:55:58PM +0900, Yoichi Yuasa wrote:
> 
> > This patch has fixed IDE resources problem about Cobalt.
> > 
> > pcibios_fixup_device_resources() changes non-movable resources.
> > It cannot be changed if there is IORESOURCE_PCI_FIXED in the resource flags. 
> 
> <Ralf> anemo: Have you seen Yoichi's patch?
> <anemo> Ralf: yes, but I could not see why ...  My impression is IORESOURCE_PCI_FIXED and io_offset adjustment is irrerevant.
> <Ralf> This whole fixup thing is really meant to handle machines where there is an offset between PCI bus addresses and CPU physical addresses.
> <Ralf> And that exists regardless of IORESOURCE_PCI_FIXED
> <anemo> I thought so too.  So I can not see why youichi's patch fix something.
> <Ralf> This may be the explanation:
> <Ralf> static struct pci_controller cobalt_pci_controller = {
> <Ralf>         .pci_ops        = &gt64111_pci_ops,
> <Ralf>         .mem_resource   = &cobalt_mem_resource,
> <Ralf>         .mem_offset     = 0,
> <Ralf>         .io_resource    = &cobalt_io_resource,
> <Ralf>         .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
> <Ralf> };
> <Ralf> I think he should have io_offset = 0.

When I tried io_offset = 0, tulip net driver didn't work.

> Which is what other GT-64120 platforms are using, so I wonder why that is
> different on Cobalt.

I don't know, but io_offset is needed for Cobalt.

Yoichi

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Atsushi Nemoto]

On Thu, 11 Jan 2007 23:47:47 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> > <Ralf> I think he should have io_offset = 0.
> 
> When I tried io_offset = 0, tulip net driver didn't work.
> 
> > Which is what other GT-64120 platforms are using, so I wonder why that is
> > different on Cobalt.
> 
> I don't know, but io_offset is needed for Cobalt.

If io_offset = 0, GT-64120 must be programmed to remap physicall
address GT_DEF_PCI0_IO_BASE to PCI IO address 0.  Maybe other GT-64120
users have such configuraion?

---
Atsushi Nemoto

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Yoichi Yuasa]

On Fri, 12 Jan 2007 00:45:31 +0900 (JST)
Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:

> On Thu, 11 Jan 2007 23:47:47 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> > > <Ralf> I think he should have io_offset = 0.
> > 
> > When I tried io_offset = 0, tulip net driver didn't work.
> > 
> > > Which is what other GT-64120 platforms are using, so I wonder why that is
> > > different on Cobalt.
> > 
> > I don't know, but io_offset is needed for Cobalt.
> 
> If io_offset = 0, GT-64120 must be programmed to remap physicall
> address GT_DEF_PCI0_IO_BASE to PCI IO address 0.  Maybe other GT-64120
> users have such configuraion?

GT-64111(used for Cobalt) has no remap register.
It cannot be programmed to address remap.

Yoichi

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Atsushi Nemoto]

On Fri, 12 Jan 2007 11:46:18 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> > If io_offset = 0, GT-64120 must be programmed to remap physicall
> > address GT_DEF_PCI0_IO_BASE to PCI IO address 0.  Maybe other GT-64120
> > users have such configuraion?
> 
> GT-64111(used for Cobalt) has no remap register.
> It cannot be programmed to address remap.

Then, inb(0) converted to physical address 0x10000000
(GT_DEF_PCI0_IO_BASE), and on PCI bus it is PCI IO address 0? or
0x10000000?

If PCI IO address was 0, io_offset should be 0.  Otherwise, io_offset
should be -0x10000000, as current code does.

So if it does not work now, something's going wrong... but I have no
idea now.

---
Atsushi Nemoto

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Peter Horton]

Ralf Baechle wrote:
> On Thu, Jan 11, 2007 at 02:55:58PM +0900, Yoichi Yuasa wrote:
> 
>> This patch has fixed IDE resources problem about Cobalt.
>>
>> pcibios_fixup_device_resources() changes non-movable resources.
>> It cannot be changed if there is IORESOURCE_PCI_FIXED in the resource flags. 
> 
> <Ralf> anemo: Have you seen Yoichi's patch?
> <anemo> Ralf: yes, but I could not see why ...  My impression is IORESOURCE_PCI_FIXED and io_offset adjustment is irrerevant.
> <Ralf> This whole fixup thing is really meant to handle machines where there is an offset between PCI bus addresses and CPU physical addresses.
> <Ralf> And that exists regardless of IORESOURCE_PCI_FIXED
> <anemo> I thought so too.  So I can not see why youichi's patch fix something.
> <Ralf> This may be the explanation:
> <Ralf> static struct pci_controller cobalt_pci_controller = {
> <Ralf>         .pci_ops        = &gt64111_pci_ops,
> <Ralf>         .mem_resource   = &cobalt_mem_resource,
> <Ralf>         .mem_offset     = 0,
> <Ralf>         .io_resource    = &cobalt_io_resource,
> <Ralf>         .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
> <Ralf> };
> <Ralf> I think he should have io_offset = 0.
> 
> Which is what other GT-64120 platforms are using, so I wonder why that is
> different on Cobalt.
> 

The GT-64111 passes the CPU addresses straight onto the PCI bus and does 
not remove the offset of the Galileo's PCI window in CPU space. This 
means the only PCI I/O addresses that can be supported are 0x1000.0000 
to 0x11ff.ffff, hence the negative 'io_offset'.

I assume the GT-64120 remaps the PCI addresses somehow to remove the offset.

P.

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Alan]

On Fri, 12 Jan 2007 14:16:39 +0000
Peter Horton <phorton@bitbox.co.uk> wrote:

> Ralf Baechle wrote:
> > On Thu, Jan 11, 2007 at 02:55:58PM +0900, Yoichi Yuasa wrote:
> > 
> >> This patch has fixed IDE resources problem about Cobalt.
> >>
> >> pcibios_fixup_device_resources() changes non-movable resources.
> >> It cannot be changed if there is IORESOURCE_PCI_FIXED in the resource flags. 
> > 
> > <Ralf> anemo: Have you seen Yoichi's patch?
> > <anemo> Ralf: yes, but I could not see why ...  My impression is IORESOURCE_PCI_FIXED and io_offset adjustment is irrerevant.
> > <Ralf> This whole fixup thing is really meant to handle machines where there is an offset between PCI bus addresses and CPU physical addresses.
> > <Ralf> And that exists regardless of IORESOURCE_PCI_FIXED
> > <anemo> I thought so too.  So I can not see why youichi's patch fix something.
> > <Ralf> This may be the explanation:
> > <Ralf> static struct pci_controller cobalt_pci_controller = {
> > <Ralf>         .pci_ops        = &gt64111_pci_ops,
> > <Ralf>         .mem_resource   = &cobalt_mem_resource,
> > <Ralf>         .mem_offset     = 0,
> > <Ralf>         .io_resource    = &cobalt_io_resource,
> > <Ralf>         .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
> > <Ralf> };
> > <Ralf> I think he should have io_offset = 0.
> > 
> > Which is what other GT-64120 platforms are using, so I wonder why that is
> > different on Cobalt.
> > 
> 
> The GT-64111 passes the CPU addresses straight onto the PCI bus and does 
> not remove the offset of the Galileo's PCI window in CPU space. This 
> means the only PCI I/O addresses that can be supported are 0x1000.0000 
> to 0x11ff.ffff, hence the negative 'io_offset'.
> 
> I assume the GT-64120 remaps the PCI addresses somehow to remove the offset.
> 
> P.


-- 
--
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Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Alan]

On Fri, 12 Jan 2007 14:40:42 +0000
Alan <alan@lxorguk.ukuu.org.uk> wrote:

Sorry hit the wrong button

> > The GT-64111 passes the CPU addresses straight onto the PCI bus and does 
> > not remove the offset of the Galileo's PCI window in CPU space. This 
> > means the only PCI I/O addresses that can be supported are 0x1000.0000 
> > to 0x11ff.ffff, hence the negative 'io_offset'.

Does this mean it can't hit PCI I/O space legacy addresses (0x1F0 etc) ?

If so can you set CONFIG_NO_ATA_LEGACY in your platform configuration

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Yoichi Yuasa]

On Fri, 12 Jan 2007 22:54:59 +0900 (JST)
Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:

> On Fri, 12 Jan 2007 11:46:18 +0900, Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> wrote:
> > > If io_offset = 0, GT-64120 must be programmed to remap physicall
> > > address GT_DEF_PCI0_IO_BASE to PCI IO address 0.  Maybe other GT-64120
> > > users have such configuraion?
> > 
> > GT-64111(used for Cobalt) has no remap register.
> > It cannot be programmed to address remap.
> 
> Then, inb(0) converted to physical address 0x10000000
> (GT_DEF_PCI0_IO_BASE), and on PCI bus it is PCI IO address 0? or
> 0x10000000?

When PCI base address register set 0x1000(I/O space), inb(0x1000) reads wrong value
(tulip net driver reads wrong eeprom data).

When PCI base address register set 0x10001000(I/O space), inb(0x1000) reads valid value.
PCI I/O address and CPU bus address seem to have to be same.

> 
> If PCI IO address was 0, io_offset should be 0.  Otherwise, io_offset
> should be -0x10000000, as current code does.

Based on the above result, io_offset should be -0x10000000.

> So if it does not work now, something's going wrong... but I have no
> idea now.

Yoichi

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Peter Horton]

Ralf Baechle wrote:
> On Fri, Jan 12, 2007 at 02:49:05PM +0000, Alan wrote:
> 
>>>> The GT-64111 passes the CPU addresses straight onto the PCI bus and does 
>>>> not remove the offset of the Galileo's PCI window in CPU space. This 
>>>> means the only PCI I/O addresses that can be supported are 0x1000.0000 
>>>> to 0x11ff.ffff, hence the negative 'io_offset'.
>> Does this mean it can't hit PCI I/O space legacy addresses (0x1F0 etc) ?
>>
>> If so can you set CONFIG_NO_ATA_LEGACY in your platform configuration
> 
> In the meantime I checked this against the Galileo documentation.  Which
> says just like Yoichi and Peter that the GT-64111 is passing local
> addresses in the configured PCI memory or I/O windows straight through to
> the PCI bus.  Reconfiguring the PCI I/O window to start at physical address
> zero is not really an option because the CPU has it's exception vectors
> there.
> 
> There is one inconsistency in the whole story still.  Cobalts use a PC-style
> legacy RTC chip at I/O port 0x70 and that seems to work just fine.  I suspect
> the the VIA Apollo SuperIO chip makes this work by just dropping some of the
> high I/O port address bits ...
> 

I've just checked on the Qube2 here and the RTC can be found at 
0x1000.0070, 0x1001.0070 etc so the VIA bridge is only decoding the low 
16 address lines for I/O space. Handy really otherwise it wouldn't work 
with the GT-64111 :-)

P.

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Ralf Baechle]

On Mon, Jan 15, 2007 at 01:37:30PM +0000, Peter Horton wrote:

Time to get this going again ...

> I've just checked on the Qube2 here and the RTC can be found at 
> 0x1000.0070, 0x1001.0070 etc so the VIA bridge is only decoding the low 
> 16 address lines for I/O space. Handy really otherwise it wouldn't work 
> with the GT-64111 :-)

Thanks, that's what I was expecting.  So to resume the discussion about
how to fix this I suggest:

 o Set cobalt_io_resource to the 0x10001000 - 0x10010000 range.
 o Set ioport_resource to the 0x10000000 - 0x10010000 range.
 o set mips_io_port_base to 0xa0000000
 o set cobalt_pci_controller.io_offset back to 0

And then since we're not longer cheating about the true value of the
port addresses on the PCI bus used, add 0x10000000 to all of the start
and end values in cobalt_io_resources.

Does that sound reasonable?

  Ralf

Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Yoichi Yuasa]

On Mon, 22 Jan 2007 20:35:17 +0000
Ralf Baechle <ralf@linux-mips.org> wrote:

> On Mon, Jan 15, 2007 at 01:37:30PM +0000, Peter Horton wrote:
> 
> Time to get this going again ...
> 
> > I've just checked on the Qube2 here and the RTC can be found at 
> > 0x1000.0070, 0x1001.0070 etc so the VIA bridge is only decoding the low 
> > 16 address lines for I/O space. Handy really otherwise it wouldn't work 
> > with the GT-64111 :-)
> 
> Thanks, that's what I was expecting.  So to resume the discussion about
> how to fix this I suggest:
> 
>  o Set cobalt_io_resource to the 0x10001000 - 0x10010000 range.
>  o Set ioport_resource to the 0x10000000 - 0x10010000 range.

IDE fixed resources are out of range.

>  o set mips_io_port_base to 0xa0000000
>  o set cobalt_pci_controller.io_offset back to 0
> 
> And then since we're not longer cheating about the true value of the
> port addresses on the PCI bus used, add 0x10000000 to all of the start
> and end values in cobalt_io_resources.
> 
> Does that sound reasonable?

sounds good, excluding above problem.

Yoichi