From: Ralf Baechle <ralf@linux-mips.org>
To: figo zhang <figo1802@gmail.com>
Cc: linux-mips@linux-mips.org
Subject: Re: why it not write those 6bits to entrylo0/1 register?
Date: Wed, 18 Nov 2009 15:08:09 +0100 [thread overview]
Message-ID: <20091118140809.GA6615@linux-mips.org> (raw)
In-Reply-To: <c6ed1ac50911170137u7463ad53k1568e722696ca570@mail.gmail.com>
On Tue, Nov 17, 2009 at 05:37:25PM +0800, figo zhang wrote:
> > > so, if i set a page attrubite is PAGE_READONLY, this attribute will set
> > to
> > > pte , right? so ,
> > > why it should shift 6 bits?
> >
>
> Thanks a lot. I am puzzle that if i set a page attrubite is PAGE_READONLY,
> tlb_write_indexed()
> will write the 6 bits to entrylo0 register? i am using 24KEC soc.
Yes, tlb_write_indexed() does that. Equally tlb_write_random() writes a
TLB entry into the TLB. Basically we use tlb_write_indexed() to overwrite
and update an existing TLB entry. But if there is no TLB entry yet then
we just use tlb_write_random() an allow the CPU to pick an arbitrary entry.
Ralf
next prev parent reply other threads:[~2009-11-18 14:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-17 8:12 why it not write those 6bits to entrylo0/1 register? figo zhang
2009-11-17 8:40 ` Ralf Baechle
2009-11-17 8:59 ` figo zhang
2009-11-17 9:26 ` Ralf Baechle
2009-11-17 9:37 ` figo zhang
2009-11-18 14:08 ` Ralf Baechle [this message]
2009-11-25 6:52 ` figo zhang
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