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From: figo zhang <figo1802@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: why it not write those 6bits to entrylo0/1 register?
Date: Wed, 25 Nov 2009 14:52:51 +0800	[thread overview]
Message-ID: <c6ed1ac50911242252u5e43f7ffh3fd599ca8f59ff43@mail.gmail.com> (raw)
In-Reply-To: <20091117084047.GA2923@linux-mips.org>

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>
> No, the low 6 bits contain other information maintained by the kernel.
> Shifting right by 6 bits is used to drop these software bits.  The
> hardware bits are stored in bits 6 and up in a pte so the shift operation
> is going to move them into the right place.
>

yes, i know why shout shift this 6 bits, see this :

entrylo[01]:
  3130 29                         6 5 3 2 1 0
  -------------------------------------------
  | | PFN                         | C |D|V|G|
  -------------------------------------------

linux pte:
  31                     12 111098 7 6 5 3 2 1 0
  -------------------------------------------
  | PFN                | C |D|V|G|B|M|A|W|R|P|
  -------------------------------------------

so , the linux PTE has the least significant 6 bits is mantain by linux PTE,
the hardware
PTE entrylo[0~1] have no such bits, so it need to shift .

ralf, is some description on the kernel code? if it has, it would be easy
understand .

>
> > D:
> > V:
> > G:
> >
> > and how the kernel write the this 6 bit to entrylo0/1 register?
>
> A TLB write instruction about 5 lines further down in the code.
>
>  Ralf
>

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      parent reply	other threads:[~2009-11-25  6:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-11-17  8:12 why it not write those 6bits to entrylo0/1 register? figo zhang
2009-11-17  8:40 ` Ralf Baechle
2009-11-17  8:59   ` figo zhang
2009-11-17  9:26     ` Ralf Baechle
2009-11-17  9:37       ` figo zhang
2009-11-18 14:08         ` Ralf Baechle
2009-11-25  6:52   ` figo zhang [this message]

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