From: figo zhang <figo1802@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: why it not write those 6bits to entrylo0/1 register?
Date: Tue, 17 Nov 2009 17:37:25 +0800 [thread overview]
Message-ID: <c6ed1ac50911170137u7463ad53k1568e722696ca570@mail.gmail.com> (raw)
In-Reply-To: <20091117092601.GB2923@linux-mips.org>
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2009/11/17 Ralf Baechle <ralf@linux-mips.org>
> On Tue, Nov 17, 2009 at 04:59:59PM +0800, figo zhang wrote:
>
> > > > why this right shift 6 bits? this 6 bits contain some important bit,
> such
> > > > as:
> > > > C: [bit3~5]: cohereny attribute of page
> > >
> > > No, the low 6 bits contain other information maintained by the kernel.
> > > Shifting right by 6 bits is used to drop these software bits. The
> > > hardware bits are stored in bits 6 and up in a pte so the shift
> operation
> > > is going to move them into the right place.
> > >
> >
> > But i have see the kernel code: include/asm-mips/pgtable-bits.h:
> > #define _CACHE_UNCACHED (2<<3)
> > #define _CACHE_CACHABLE_NONCOHERENT (3<<3)
> > #define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
>
> This is code for the special case where CONFIG_64BIT_PHYS_ADDR and
> CONFIG_CPU_MIPS32 are both defined. In that case tlb-r4k.c also won't do
> shifting.
>
> > in include/asm-mips/pgtbale.h:
> > #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
> > PAGE_CACHABLE_DEFAULT)
> >
> > so, if i set a page attrubite is PAGE_READONLY, this attribute will set
> to
> > pte , right? so ,
> > why it should shift 6 bits?
>
Thanks a lot. I am puzzle that if i set a page attrubite is PAGE_READONLY,
tlb_write_indexed()
will write the 6 bits to entrylo0 register? i am using 24KEC soc.
Thanks,
Figo.zhang
> >
> > >
> > > > D:
> > > > V:
> > > > G:
> > > >
> > > > and how the kernel write the this 6 bit to entrylo0/1 register?
> > >
> > > A TLB write instruction about 5 lines further down in the code.
> > >
> >
> > which function write those 6 bits to register? tlb_write_indexed() ? if i
> > want set pages cache attribute is uncached/write-back , how it can set it
> > correctly to MIPS?
>
> See drivers/char/mem.c; search for pgprot_noncached(). This is where
> for uncached mmaps pick the apropriate page protection and cache bits.
> Several other drivers may do equivalent things.
>
> Ralf
>
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next prev parent reply other threads:[~2009-11-17 9:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-11-17 8:12 why it not write those 6bits to entrylo0/1 register? figo zhang
2009-11-17 8:40 ` Ralf Baechle
2009-11-17 8:59 ` figo zhang
2009-11-17 9:26 ` Ralf Baechle
2009-11-17 9:37 ` figo zhang [this message]
2009-11-18 14:08 ` Ralf Baechle
2009-11-25 6:52 ` figo zhang
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