* [PATCH 1/2] MIPS: Add more CPU identifiers for Octeon II CPUs.
@ 2011-09-20 22:49 David Daney
2011-09-20 22:49 ` [PATCH 2/2] MIPS: Add probes for more " David Daney
2011-09-23 23:49 ` [PATCH 1/2] MIPS: Add more CPU identifiers for " Ralf Baechle
0 siblings, 2 replies; 6+ messages in thread
From: David Daney @ 2011-09-20 22:49 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
The CPU identifiers for cn68XX, cn66XX and cn61XX are known, so add
them.
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/include/asm/cpu.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 5f95a4b..2f7f418 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -135,6 +135,9 @@
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
+#define PRID_IMP_CAVIUM_CN68XX 0x9100
+#define PRID_IMP_CAVIUM_CN66XX 0x9200
+#define PRID_IMP_CAVIUM_CN61XX 0x9300
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
--
1.7.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] MIPS: Add probes for more Octeon II CPUs.
2011-09-20 22:49 [PATCH 1/2] MIPS: Add more CPU identifiers for Octeon II CPUs David Daney
@ 2011-09-20 22:49 ` David Daney
2011-09-23 23:50 ` Ralf Baechle
2011-09-23 23:49 ` [PATCH 1/2] MIPS: Add more CPU identifiers for " Ralf Baechle
1 sibling, 1 reply; 6+ messages in thread
From: David Daney @ 2011-09-20 22:49 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium().
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/kernel/cpu-probe.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ebc0cd2..aa327a7 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -978,7 +978,10 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
platform:
set_elf_platform(cpu, "octeon");
break;
+ case PRID_IMP_CAVIUM_CN61XX:
case PRID_IMP_CAVIUM_CN63XX:
+ case PRID_IMP_CAVIUM_CN66XX:
+ case PRID_IMP_CAVIUM_CN68XX:
c->cputype = CPU_CAVIUM_OCTEON2;
__cpu_name[cpu] = "Cavium Octeon II";
set_elf_platform(cpu, "octeon2");
--
1.7.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] MIPS: Add more CPU identifiers for Octeon II CPUs.
2011-09-20 22:49 [PATCH 1/2] MIPS: Add more CPU identifiers for Octeon II CPUs David Daney
2011-09-20 22:49 ` [PATCH 2/2] MIPS: Add probes for more " David Daney
@ 2011-09-23 23:49 ` Ralf Baechle
1 sibling, 0 replies; 6+ messages in thread
From: Ralf Baechle @ 2011-09-23 23:49 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
Queued for 3.2. Thanks,
Ralf
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 0/5] MIPS: perf: Add support for 64-bit MIPS hardware counters.
@ 2011-09-22 17:26 David Daney
2011-09-22 17:26 ` [PATCH 2/2] MIPS: Add probes for more Octeon II CPUs David Daney
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2011-09-22 17:26 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney, Deng-Cheng Zhu
MIPS hardware performance counters may have either 32-bit or 64-bit
wide counter registers. The current implementation only supports the
32-bit variety.
These patches aim to add support for 64-bit wide counters while
mantaining support for 32-bit.
Tested with perf top and perf record, which both work well on an
Octeon/Debian based system.
Changes from v4:
o Rebased against 3.1.0-rc6
Changes from v3:
o Rebased against 2.6.39.
o Re-Include Octeon processor support.
Changes from v2:
o Quit sign extending 32-bit counter values.
o Remove usless local_irq_save() in several places.
Changes from v1:
o Removed Octeon processor support to a separate patch set.
o Rebased against v5 of Deng-Cheng Zhu's cleanups:
http://patchwork.linux-mips.org/patch/2011/
http://patchwork.linux-mips.org/patch/2012/
http://patchwork.linux-mips.org/patch/2013/
http://patchwork.linux-mips.org/patch/2014/
http://patchwork.linux-mips.org/patch/2015/
o Tried to fix problem where 32-bit counters generated way too many
interrupts.
David Daney (5):
MIPS: Add accessor macros for 64-bit performance counter registers.
MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
MIPS: perf: Reorganize contents of perf support files.
MIPS: perf: Add support for 64-bit perf counters.
MIPS: perf: Add Octeon support for hardware perf.
arch/mips/Kconfig | 2 +-
arch/mips/include/asm/mipsregs.h | 8 +
arch/mips/kernel/Makefile | 5 +-
arch/mips/kernel/perf_event.c | 519 +--------------
arch/mips/kernel/perf_event_mipsxx.c | 1265 ++++++++++++++++++++++++----------
5 files changed, 933 insertions(+), 866 deletions(-)
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
--
1.7.2.3
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/2] MIPS: Add probes for more Octeon II CPUs.
2011-09-22 17:26 [PATCH v5 0/5] MIPS: perf: Add support for 64-bit MIPS hardware counters David Daney
@ 2011-09-22 17:26 ` David Daney
2011-09-22 17:30 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2011-09-22 17:26 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium().
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/kernel/cpu-probe.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ebc0cd2..aa327a7 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -978,7 +978,10 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
platform:
set_elf_platform(cpu, "octeon");
break;
+ case PRID_IMP_CAVIUM_CN61XX:
case PRID_IMP_CAVIUM_CN63XX:
+ case PRID_IMP_CAVIUM_CN66XX:
+ case PRID_IMP_CAVIUM_CN68XX:
c->cputype = CPU_CAVIUM_OCTEON2;
__cpu_name[cpu] = "Cavium Octeon II";
set_elf_platform(cpu, "octeon2");
--
1.7.2.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] MIPS: Add probes for more Octeon II CPUs.
2011-09-22 17:26 ` [PATCH 2/2] MIPS: Add probes for more Octeon II CPUs David Daney
@ 2011-09-22 17:30 ` David Daney
0 siblings, 0 replies; 6+ messages in thread
From: David Daney @ 2011-09-22 17:30 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips, ralf
Crap, this is the wrong patch, it is from the other patch set.
I will now send the right 2/5
On 09/22/2011 10:26 AM, David Daney wrote:
> Detect cn61XX, cn66XX and cn68XX CPUs in cpu_probe_cavium().
>
> Signed-off-by: David Daney<david.daney@cavium.com>
> ---
> arch/mips/kernel/cpu-probe.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index ebc0cd2..aa327a7 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -978,7 +978,10 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
> platform:
> set_elf_platform(cpu, "octeon");
> break;
> + case PRID_IMP_CAVIUM_CN61XX:
> case PRID_IMP_CAVIUM_CN63XX:
> + case PRID_IMP_CAVIUM_CN66XX:
> + case PRID_IMP_CAVIUM_CN68XX:
> c->cputype = CPU_CAVIUM_OCTEON2;
> __cpu_name[cpu] = "Cavium Octeon II";
> set_elf_platform(cpu, "octeon2");
^ permalink raw reply [flat|nested] 6+ messages in thread
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2011-09-20 22:49 [PATCH 1/2] MIPS: Add more CPU identifiers for Octeon II CPUs David Daney
2011-09-20 22:49 ` [PATCH 2/2] MIPS: Add probes for more " David Daney
2011-09-23 23:50 ` Ralf Baechle
2011-09-23 23:49 ` [PATCH 1/2] MIPS: Add more CPU identifiers for " Ralf Baechle
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2011-09-22 17:26 [PATCH v5 0/5] MIPS: perf: Add support for 64-bit MIPS hardware counters David Daney
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