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* [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT
@ 2014-01-15 19:05 Florian Fainelli
  2014-01-15 19:05 ` Florian Fainelli
  2014-01-22 23:11 ` Ralf Baechle
  0 siblings, 2 replies; 4+ messages in thread
From: Florian Fainelli @ 2014-01-15 19:05 UTC (permalink / raw)
  To: linux-mips; +Cc: ralf, blogic, Florian Fainelli

When a platform overrides the dcache_line_size detection in its
cpu-features-override.h file, check that the value matches
(1 << CONFIG_MIPS_L1_SHIFT) to ensure both settings are correct.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/include/asm/cpu-features.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 6e70b03..9052fb9 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -279,6 +279,10 @@
 
 #ifndef cpu_dcache_line_size
 #define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
+#else
+#if (cpu_dcache_line_size() != (1 << CONFIG_MIPS_L1_CACHE_SHIFT))
+#error "cpu_dcache_line_size does not match CONFIG_MIPS_L1_CACHE_SHIFT"
+#endif
 #endif
 #ifndef cpu_icache_line_size
 #define cpu_icache_line_size()	cpu_data[0].icache.linesz
-- 
1.8.3.2

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT
  2014-01-15 19:05 [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT Florian Fainelli
@ 2014-01-15 19:05 ` Florian Fainelli
  2014-01-22 23:11 ` Ralf Baechle
  1 sibling, 0 replies; 4+ messages in thread
From: Florian Fainelli @ 2014-01-15 19:05 UTC (permalink / raw)
  To: linux-mips; +Cc: ralf, blogic, Florian Fainelli

When a platform overrides the dcache_line_size detection in its
cpu-features-override.h file, check that the value matches
(1 << CONFIG_MIPS_L1_SHIFT) to ensure both settings are correct.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/include/asm/cpu-features.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 6e70b03..9052fb9 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -279,6 +279,10 @@
 
 #ifndef cpu_dcache_line_size
 #define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
+#else
+#if (cpu_dcache_line_size() != (1 << CONFIG_MIPS_L1_CACHE_SHIFT))
+#error "cpu_dcache_line_size does not match CONFIG_MIPS_L1_CACHE_SHIFT"
+#endif
 #endif
 #ifndef cpu_icache_line_size
 #define cpu_icache_line_size()	cpu_data[0].icache.linesz
-- 
1.8.3.2

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT
  2014-01-15 19:05 [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT Florian Fainelli
  2014-01-15 19:05 ` Florian Fainelli
@ 2014-01-22 23:11 ` Ralf Baechle
  2014-01-22 23:20   ` Florian Fainelli
  1 sibling, 1 reply; 4+ messages in thread
From: Ralf Baechle @ 2014-01-22 23:11 UTC (permalink / raw)
  To: Florian Fainelli; +Cc: linux-mips, blogic

On Wed, Jan 15, 2014 at 11:05:22AM -0800, Florian Fainelli wrote:

> When a platform overrides the dcache_line_size detection in its
> cpu-features-override.h file, check that the value matches
> (1 << CONFIG_MIPS_L1_SHIFT) to ensure both settings are correct.

Conceptually wrong - the two values serve an entirely different purpose.
dcache_line_size is used for cache maintenance by the MIPS code while
CONFIG_MIPS_L1_SHIFT - which has to be a constant due to the way it's
being used - are being used to define L1_CACHE_SHIFT in <asm/cache.h>
which in turn is being used primarily to optimize the memory layout of
various structures for performance - and in case of IP27 we lie, set
L1_CACHE_SHIFT to 7 which is the size of the S-cache.

On top of that it breaks the ip27 build.

And while we're at it, the use of CONFIG_MIPS_L1_SHIFT in
arch/mips/kernel/vmlinux.lds.S is fishy - but it needs a constant and
this should be good enough for all users.

  Ralf

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT
  2014-01-22 23:11 ` Ralf Baechle
@ 2014-01-22 23:20   ` Florian Fainelli
  0 siblings, 0 replies; 4+ messages in thread
From: Florian Fainelli @ 2014-01-22 23:20 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: Linux-MIPS, John Crispin

2014/1/22 Ralf Baechle <ralf@linux-mips.org>:
> On Wed, Jan 15, 2014 at 11:05:22AM -0800, Florian Fainelli wrote:
>
>> When a platform overrides the dcache_line_size detection in its
>> cpu-features-override.h file, check that the value matches
>> (1 << CONFIG_MIPS_L1_SHIFT) to ensure both settings are correct.
>
> Conceptually wrong - the two values serve an entirely different purpose.
> dcache_line_size is used for cache maintenance by the MIPS code while
> CONFIG_MIPS_L1_SHIFT - which has to be a constant due to the way it's
> being used - are being used to define L1_CACHE_SHIFT in <asm/cache.h>
> which in turn is being used primarily to optimize the memory layout of
> various structures for performance - and in case of IP27 we lie, set
> L1_CACHE_SHIFT to 7 which is the size of the S-cache.
>
> On top of that it breaks the ip27 build.
>
> And while we're at it, the use of CONFIG_MIPS_L1_SHIFT in
> arch/mips/kernel/vmlinux.lds.S is fishy - but it needs a constant and
> this should be good enough for all users.

Fair enough, feel free to revert these commits and fix vmlinux.lds.S
while at it.
-- 
Florian

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2014-01-22 23:21 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2014-01-15 19:05 [PATCH mips-for-linux-next] MIPS: check for D$ line size and CONFIG_MIPS_L1_SHIFT Florian Fainelli
2014-01-15 19:05 ` Florian Fainelli
2014-01-22 23:11 ` Ralf Baechle
2014-01-22 23:20   ` Florian Fainelli

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