Re: [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read

[Ralf Baechle <ralf@linux-mips.org>]

On Wed, May 13, 2015 at 11:50:48AM +0100, James Hogan wrote:

> Add hazard macros to <asm/hazards.h> for the following hazards around
> tlbr (TLB read) instructions, which are used in TLB dumping code and
> some KVM TLB management code:
> 
> - mtc0_tlbr_hazard
>   Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
>   all cases on the assumption that tlbr always has similar data user
>   timings to tlbw.
> 
> - tlb_read_hazard
>   Between tlbr and mfc0 (various TLB registers). This is copied from
>   tlbw_use_hazard in all cases on the assumption that tlbr has similar
>   data writer characteristics to tlbw, and mfc0 has similar data user
>   characteristics to loads and stores.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
> Looking at r4000 manual, its tlbr had similar data user timings to tlbw,
> and mfc0 had similar data writer timings to loads and stores. Are there
> particular other cores that should be checked too?

The R4600 and R5000 CPUs are important.  The R4600 also covers the
R4700 and the R5000 the R52xx embedded cores.

For most cases the R4000/R4400 due to their long pipeline represent the
worst case but there are exceptions.

  Ralf