From: James Hogan <james.hogan@imgtec.com>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
Date: Mon, 18 May 2015 14:50:06 +0100 [thread overview]
Message-ID: <5559EE0E.5030606@imgtec.com> (raw)
In-Reply-To: <alpine.LFD.2.11.1505160137150.4923@eddie.linux-mips.org>
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Hi Maciej,
On 16/05/15 01:44, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, James Hogan wrote:
>
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>> arch/mips/lib/dump_tlb.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>> */
>> if ((entryhi & ~0x1ffffUL) == CKSEG0)
>> continue;
>> - if ((entryhi & 0xff) != asid)
>> + /* ASID takes effect in absense of global bit */
>
> Typo here, s/absense/absence/.
Thanks!
>
>> + if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>
> Hmm, it looks like r3k_dump_tlb.c will need a similar update. I suggest
Yes, quite possibly. Would you be happy to test such a patch (assuming
you have r3000 hardware available)? Patch 1 should allow the code to be
easily triggered.
> using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.
Yeh, as you mentioned these describe the PTE rather than what goes in
EntryLo. Perhaps it makes sense to have a few more TLB dependent
definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits).
Cheers
James
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WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account
Date: Mon, 18 May 2015 14:50:06 +0100 [thread overview]
Message-ID: <5559EE0E.5030606@imgtec.com> (raw)
Message-ID: <20150518135006.tHhnVRlDwRvP6QhZGmil55pFt6EEcLgiQ08Phj_qhfE@z> (raw)
In-Reply-To: <alpine.LFD.2.11.1505160137150.4923@eddie.linux-mips.org>
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Hi Maciej,
On 16/05/15 01:44, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, James Hogan wrote:
>
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>> arch/mips/lib/dump_tlb.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>> */
>> if ((entryhi & ~0x1ffffUL) == CKSEG0)
>> continue;
>> - if ((entryhi & 0xff) != asid)
>> + /* ASID takes effect in absense of global bit */
>
> Typo here, s/absense/absence/.
Thanks!
>
>> + if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>
> Hmm, it looks like r3k_dump_tlb.c will need a similar update. I suggest
Yes, quite possibly. Would you be happy to test such a patch (assuming
you have r3000 hardware available)? Patch 1 should allow the code to be
easily triggered.
> using _PAGE_GLOBAL and ASID_MASK rather than hardcoded 1 and 0xff.
Yeh, as you mentioned these describe the PTE rather than what goes in
EntryLo. Perhaps it makes sense to have a few more TLB dependent
definitions in mipsregs.h (patch 7 already adds a couple for RI/XI bits).
Cheers
James
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next prev parent reply other threads:[~2015-05-18 13:50 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-13 10:50 [PATCH 0/9] MIPS: dump_tlb improvements James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH RFC 1/9] MIPS: Add SysRq operation to dump TLBs on all CPUs James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH 2/9] MIPS: hazards: Add hazard macros for tlb read James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-15 15:08 ` Ralf Baechle
2015-05-18 13:30 ` James Hogan
2015-05-18 13:30 ` James Hogan
2015-05-13 10:50 ` [PATCH 3/9] MIPS: dump_tlb: Use tlbr hazard macros James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-15 15:17 ` Ralf Baechle
2015-05-16 0:32 ` Maciej W. Rozycki
2015-05-13 10:50 ` [PATCH 4/9] MIPS: dump_tlb: Refactor TLB matching James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH 5/9] MIPS: dump_tlb: Take global bit into account James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-15 15:38 ` Ralf Baechle
2015-05-18 13:37 ` James Hogan
2015-05-18 13:37 ` James Hogan
2015-05-16 0:44 ` Maciej W. Rozycki
2015-05-16 1:02 ` Maciej W. Rozycki
2015-05-18 13:50 ` James Hogan [this message]
2015-05-18 13:50 ` James Hogan
2015-05-18 14:19 ` Maciej W. Rozycki
2015-05-13 10:50 ` [PATCH 6/9] MIPS: dump_tlb: Take EHINV " James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH 7/9] MIPS: dump_tlb: Take RI/XI bits " James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH 8/9] MIPS: dump_tlb: Take XPA " James Hogan
2015-05-13 10:50 ` James Hogan
2015-05-13 10:50 ` [PATCH 9/9] MIPS: tlb-r4k: Fix PG_ELPA comment James Hogan
2015-05-13 10:50 ` James Hogan
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