Re: [PATCH 5/9] MIPS: dump_tlb: Take global bit into account

[James Hogan <james.hogan@imgtec.com>]

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On 15/05/15 16:38, Ralf Baechle wrote:
> On Wed, May 13, 2015 at 11:50:51AM +0100, James Hogan wrote:
> 
>> The TLB only matches the ASID when the global bit isn't set, so
>> dump_tlb() shouldn't really be skipping global entries just because the
>> ASID doesn't match. Fix the condition to read the TLB entry's global bit
>> from EntryLo0. Note that after a TLB read the global bits in both
>> EntryLo registers reflect the same global bit in the TLB entry.
>>
>> Signed-off-by: James Hogan <james.hogan@imgtec.com>
>> Cc: Ralf Baechle <ralf@linux-mips.org>
>> Cc: linux-mips@linux-mips.org
>> ---
>>  arch/mips/lib/dump_tlb.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
>> index 17d05caa776d..70e0a6bdb322 100644
>> --- a/arch/mips/lib/dump_tlb.c
>> +++ b/arch/mips/lib/dump_tlb.c
>> @@ -73,7 +73,8 @@ static void dump_tlb(int first, int last)
>>  		 */
>>  		if ((entryhi & ~0x1ffffUL) == CKSEG0)
>>  			continue;
>> -		if ((entryhi & 0xff) != asid)
>> +		/* ASID takes effect in absense of global bit */
>> +		if (!(entrylo0 & 1) && (entryhi & 0xff) != asid)
>>  			continue;
> 
> Note the architecture mandates that there only is one global bit per
> TLB entry and its written as the logic and of the two global bits in
> the entrylo0 and entrylo1 registers.  On TLB read the G bits of both
> entrylo registers will return the same value.
> 
> In reality some implementations differ in hardware, for example the
> SB1 core where the TLB entries both have their separate G bit.  Both
> will be written with the logic and of the G bits of the entrylo registers
> so the existence of multiple G bits per TLB entry should never become
> visible.
> 
> Except when writing a duplicate TLB entry where certain revisions will
> write the entrylo0 half of the TLB entry, then take the machine check
> exception leaving the entrylo1 half of the TLB entry unchanged.  At
> this point one may end up with architecturally undefined TLB entries
> with one G bit set and one clear.
> 
> There may be other CPUs where such invalid TLB entries are possible
> therfore think we should check for entries with mismatching global
> bits and print those anyway.

Okay, makes sense. If either global bit is set I'll make it skip the
ASID check.

Thanks for the information.

Cheers
James


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