From: James Hogan <jhogan@kernel.org>
To: Huacai Chen <chenhc@lemote.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
"Steven J . Hill" <Steven.Hill@cavium.com>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>
Subject: Re: [PATCH V2 03/12] MIPS: Loongson-3: Enable Store Fill Buffer at runtime
Date: Thu, 15 Feb 2018 12:43:15 +0000 [thread overview]
Message-ID: <20180215124315.GJ3986@saruman> (raw)
In-Reply-To: <1517022752-3053-4-git-send-email-chenhc@lemote.com>
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On Sat, Jan 27, 2018 at 11:12:23AM +0800, Huacai Chen wrote:
> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> index 3127391..4b7f58a 100644
> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> @@ -26,12 +26,15 @@
> mfc0 t0, CP0_PAGEGRAIN
> or t0, (0x1 << 29)
> mtc0 t0, CP0_PAGEGRAIN
> -#ifdef CONFIG_LOONGSON3_ENHANCEMENT
> /* Enable STFill Buffer */
> + mfc0 t0, CP0_PRID
> + andi t0, 0xffff
Maybe worth including <asm/cpu.h and doing:
andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
> + slti t0, 0x6308
and:
slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
With something like that here and in the other place:
Reviewed-by: James Hogan <jhogan@kernel.org>
Cheers
James
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next prev parent reply other threads:[~2018-02-15 12:43 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-27 3:12 [PATCH V2 00/12] MIPS: Loongson: new features and improvements Huacai Chen
2018-01-27 3:12 ` [PATCH V2 01/12] MIPS: Loongson: Add Loongson-3A R3.1 basic support Huacai Chen
2018-01-27 3:12 ` [PATCH V2 02/12] MIPS: Loongson64: Define and use some CP0 registers Huacai Chen
2018-02-15 11:36 ` James Hogan
2018-01-27 3:12 ` [PATCH V2 03/12] MIPS: Loongson-3: Enable Store Fill Buffer at runtime Huacai Chen
2018-02-15 12:43 ` James Hogan [this message]
2018-01-27 3:19 ` [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-02-19 22:19 ` James Hogan
2018-01-27 3:20 ` [PATCH V2 05/12] MIPS: Loongson fix name confict - MEM_RESERVED Huacai Chen
2018-01-27 3:21 ` [PATCH V2 06/12] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
2018-01-27 3:22 ` [PATCH V2 07/12] MIPS: Add __cpu_full_name[] to make CPU names more human-readable Huacai Chen
2018-01-27 3:22 ` [PATCH V2 08/12] MIPS: Align kernel load address to 64KB Huacai Chen
2018-02-19 23:07 ` James Hogan
2018-02-20 22:14 ` Maciej W. Rozycki
2018-02-20 22:14 ` Maciej W. Rozycki
2018-02-20 22:25 ` James Hogan
2018-02-20 22:25 ` James Hogan
2018-02-20 22:53 ` Maciej W. Rozycki
2018-02-20 22:53 ` Maciej W. Rozycki
2018-02-20 22:58 ` James Hogan
2018-02-20 22:58 ` James Hogan
2018-02-20 23:38 ` Maciej W. Rozycki
2018-02-20 23:38 ` Maciej W. Rozycki
2018-02-21 11:13 ` James Hogan
2018-02-21 11:13 ` James Hogan
2018-02-26 12:41 ` Maciej W. Rozycki
2018-02-26 12:41 ` Maciej W. Rozycki
2018-01-27 3:22 ` [PATCH V2 09/12] MIPS: Loongson: Add kexec/kdump support Huacai Chen
2018-02-19 23:54 ` James Hogan
2018-01-27 3:22 ` [PATCH V2 10/12] MIPS: Loongson: Make CPUFreq usable for Loongson-3 Huacai Chen
2018-01-27 3:23 ` [PATCH V2 11/12] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-02-20 21:49 ` James Hogan
2018-01-27 3:23 ` [PATCH V2 12/12] MIPS: Loongson: Introduce and use WAR_LLSC_MB Huacai Chen
2018-02-20 22:21 ` James Hogan
2018-02-21 10:09 ` Maciej W. Rozycki
2018-02-21 10:09 ` Maciej W. Rozycki
2018-02-21 11:43 ` James Hogan
2018-02-20 21:42 ` [PATCH V2 10/12] MIPS: Loongson: Make CPUFreq usable for Loongson-3 James Hogan
2018-02-15 11:05 ` [PATCH V2 00/12] MIPS: Loongson: new features and improvements James Hogan
2018-02-28 2:23 ` Huacai Chen
2018-02-28 10:03 ` James Hogan
2018-03-01 2:35 ` Huacai Chen
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