[PATCH 8/9] mips: dts: realtek: Add RTL838x SoC peripherals

[Sander Vanheule <sander@svanheule.net>]

Add some of the SoC's CPU peripherals currently supported:
  - GPIO controller with support for 24 GPIO lines, although not all
    lines are brought out to pads on the SoC package. These lines can
    generate interrupts from external sources.
  - Watchdog which can be used to restart the SoC if no external restart
    logic is present.
  - SPI controller, primarily used to access NOR flash

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index 246f4f607128..ce522a6af262 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -46,6 +46,14 @@ soc@18000000 {
 		#size-cells = <1>;
 		ranges = <0x0 0x18000000 0x10000>;
 
+		spi0: spi@1200 {
+			compatible = "realtek,rtl8380-spi";
+			reg = <0x1200 0x100>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@2000 {
 			compatible = "ns16550a";
 			reg = <0x2000 0x100>;
@@ -89,5 +97,33 @@ intc: interrupt-controller@3000 {
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>, <3>, <4>, <5>, <6>;
 		};
+
+		watchdog: watchdog@3150 {
+			compatible = "realtek,rtl8380-wdt";
+			reg = <0x3150 0xc>;
+
+			realtek,reset-mode = "soc";
+
+			clocks = <&lx_clk>;
+			timeout-sec = <20>;
+
+			interrupt-parent = <&intc>;
+			interrupt-names = "phase1", "phase2";
+			interrupts = <19>, <18>;
+		};
+
+		gpio0: gpio@3500 {
+			compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
+			reg = <0x3500 0x1c>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <23>;
+		};
 	};
 };
-- 
2.48.1