[PATCH] Philips(NXP)/STB810 changes

[PATCH] Philips(NXP)/STB810 changes

[Daniel Laird]

We have found the following changes are necessary for the Philips(NXP)/STB810
platform


Signed-off-by: Daniel Laird <daniel.j.laird@nxp.com> 

--- kernel/include/asm-mips/mipsregs.h
+++ kernel-new/include/asm-mips/mipsregs.h 
@@ -498,6 +498,25 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the PR4450 CMEM Registers */
+#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
+#define PR4450_CMEMB_BBA     20
+#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
+#define PR4450_CMEMB_SIZE    1
+#define PR4450_CMEM_SIZE_1MB    0
+#define PR4450_CMEM_SIZE_2MB    1
+#define PR4450_CMEM_SIZE_4MB    2
+#define PR4450_CMEM_SIZE_8MB    3
+#define PR4450_CMEM_SIZE_16MB   4
+#define PR4450_CMEM_SIZE_32MB   5
+#define PR4450_CMEM_SIZE_64MB   6
+#define PR4450_CMEM_SIZE_128MB  7
+#define PR4450_CMEM_SIZE_256MB  8
+#define PR4450_CMEM_SIZE_512MB  9
+#define PR4450_CMEM_SIZE_1GB   10
+#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
+#define PR4450_CMEMB_VALID   0
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
@@ -917,6 +936,14 @@
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 
+#ifdef CONFIG_SOC_PNX8550
+#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
+#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
+
+#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
+#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
+#endif
+
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
 
--- kernel/arch/mips/philips/pnx8550/common/setup.c
+++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
@@ -100,11 +100,29 @@
 
 	board_setup();  /* board specific setup */
 
-        _machine_restart = pnx8550_machine_restart;
-        _machine_halt = pnx8550_machine_halt;
-        pm_power_off = pnx8550_machine_power_off;
+    _machine_restart = pnx8550_machine_restart;
+    _machine_halt = pnx8550_machine_halt;
+    pm_power_off = pnx8550_machine_power_off;
+	board_time_init = pnx8550_time_init;
 
-	board_time_init = pnx8550_time_init;
+    /* Setup CMEM Registers */
+    /* CMEM0 = MMIO */
+    write_c0_diag4((0x1be00000 & PR4450_CMEMF_BBA) |
+                   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE) |
+                   (1 << PR4450_CMEMB_VALID));
+
+    /* CMEM1 = XIO */
+    write_c0_diag5((0x10000000 & PR4450_CMEMF_BBA) |
+                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
+                   (1 << PR4450_CMEMB_VALID));
+
+    /* CMEM2 = PCI */
+    write_c0_diag6((0x20000000 & PR4450_CMEMF_BBA) |
+                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
+                   (1 << PR4450_CMEMB_VALID));
+
+    /* CMEM3 = Not used */
+    write_c0_diag7(0);
 
 	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
 	   Bit 1:Enable DAC Powerdown

Cheers
Dan Laird

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Re: [PATCH] Philips(NXP)/STB810 changes

[Sergei Shtylyov]

Hello.

Daniel Laird wrote:

> We have found the following changes are necessary for the Philips(NXP)/STB810
> platform

> Signed-off-by: Daniel Laird <daniel.j.laird@nxp.com> 

> --- kernel/arch/mips/philips/pnx8550/common/setup.c
> +++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
> @@ -100,11 +100,29 @@
>  
>  	board_setup();  /* board specific setup */
>  
> -        _machine_restart = pnx8550_machine_restart;
> -        _machine_halt = pnx8550_machine_halt;
> -        pm_power_off = pnx8550_machine_power_off;
> +    _machine_restart = pnx8550_machine_restart;
> +    _machine_halt = pnx8550_machine_halt;
> +    pm_power_off = pnx8550_machine_power_off;

> +	board_time_init = pnx8550_time_init;

> -	board_time_init = pnx8550_time_init;

    What is changed here beside the tab being converted to 4 spaces for no 
reason? This violates kernel style and so is not acceptable.

> +    /* Setup CMEM Registers */
> +    /* CMEM0 = MMIO */
> +    write_c0_diag4((0x1be00000 & PR4450_CMEMF_BBA) |
> +                   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE) |
> +                   (1 << PR4450_CMEMB_VALID));
> +
> +    /* CMEM1 = XIO */
> +    write_c0_diag5((0x10000000 & PR4450_CMEMF_BBA) |
> +                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
> +                   (1 << PR4450_CMEMB_VALID));
> +
> +    /* CMEM2 = PCI */
> +    write_c0_diag6((0x20000000 & PR4450_CMEMF_BBA) |
> +                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
> +                   (1 << PR4450_CMEMB_VALID));
> +
> +    /* CMEM3 = Not used */
> +    write_c0_diag7(0);

    Please indent these properly too.

>  
>  	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
>  	   Bit 1:Enable DAC Powerdown

> Cheers
> Dan Laird

WBR, Sergei

Re: [PATCH] Philips(NXP)/STB810 changes

[Daniel Laird]

Apologies!

Please find the new patch below - I hope it is following the correct rules
now.
Signed-off-by: Daniel Laird <daniel.j.laird@nxp.com> 

--- kernel/include/asm-mips/mipsregs.h
+++ kernel-new/include/asm-mips/mipsregs.h 
@@ -498,6 +498,25 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the PR4450 CMEM Registers */
+#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
+#define PR4450_CMEMB_BBA     20
+#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
+#define PR4450_CMEMB_SIZE    1
+#define PR4450_CMEM_SIZE_1MB    0
+#define PR4450_CMEM_SIZE_2MB    1
+#define PR4450_CMEM_SIZE_4MB    2
+#define PR4450_CMEM_SIZE_8MB    3
+#define PR4450_CMEM_SIZE_16MB   4
+#define PR4450_CMEM_SIZE_32MB   5
+#define PR4450_CMEM_SIZE_64MB   6
+#define PR4450_CMEM_SIZE_128MB  7
+#define PR4450_CMEM_SIZE_256MB  8
+#define PR4450_CMEM_SIZE_512MB  9
+#define PR4450_CMEM_SIZE_1GB   10
+#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
+#define PR4450_CMEMB_VALID   0
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
@@ -917,6 +936,14 @@
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 
+#ifdef CONFIG_SOC_PNX8550
+#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
+#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
+
+#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
+#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
+#endif
+
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
 
--- kernel/arch/mips/philips/pnx8550/common/setup.c
+++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
@@ -106,6 +106,25 @@
 
 	board_time_init = pnx8550_time_init;
 
+	/* Setup CMEM Registers */
+	/* CMEM0 = MMIO */
+	write_c0_diag4((0x1be00000 & PR4450_CMEMF_BBA) |
+				   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE) |
+				   (1 << PR4450_CMEMB_VALID));
+
+	/* CMEM1 = XIO */
+	write_c0_diag5((0x10000000 & PR4450_CMEMF_BBA) |
+				   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
+				   (1 << PR4450_CMEMB_VALID));
+
+	/* CMEM2 = PCI */
+	write_c0_diag6((0x20000000 & PR4450_CMEMF_BBA) |
+				   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
+				   (1 << PR4450_CMEMB_VALID));
+
+	/* CMEM3 = Not used */
+	write_c0_diag7(0);
+
 	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
 	   Bit 1:Enable DAC Powerdown
 	  -> 0:DACs are enabled and are working normally

Cheers
Dan




Sergei Shtylyov-2 wrote:
> 
> Hello.
> 
> Daniel Laird wrote:
> 
>> We have found the following changes are necessary for the
>> Philips(NXP)/STB810
>> platform
> 
>> Signed-off-by: Daniel Laird <daniel.j.laird@nxp.com> 
> 
>> --- kernel/arch/mips/philips/pnx8550/common/setup.c
>> +++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
>> @@ -100,11 +100,29 @@
>>  
>>  	board_setup();  /* board specific setup */
>>  
>> -        _machine_restart = pnx8550_machine_restart;
>> -        _machine_halt = pnx8550_machine_halt;
>> -        pm_power_off = pnx8550_machine_power_off;
>> +    _machine_restart = pnx8550_machine_restart;
>> +    _machine_halt = pnx8550_machine_halt;
>> +    pm_power_off = pnx8550_machine_power_off;
> 
>> +	board_time_init = pnx8550_time_init;
> 
>> -	board_time_init = pnx8550_time_init;
> 
>     What is changed here beside the tab being converted to 4 spaces for no 
> reason? This violates kernel style and so is not acceptable.
> 
>> +    /* Setup CMEM Registers */
>> +    /* CMEM0 = MMIO */
>> +    write_c0_diag4((0x1be00000 & PR4450_CMEMF_BBA) |
>> +                   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE) |
>> +                   (1 << PR4450_CMEMB_VALID));
>> +
>> +    /* CMEM1 = XIO */
>> +    write_c0_diag5((0x10000000 & PR4450_CMEMF_BBA) |
>> +                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
>> +                   (1 << PR4450_CMEMB_VALID));
>> +
>> +    /* CMEM2 = PCI */
>> +    write_c0_diag6((0x20000000 & PR4450_CMEMF_BBA) |
>> +                   (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |
>> +                   (1 << PR4450_CMEMB_VALID));
>> +
>> +    /* CMEM3 = Not used */
>> +    write_c0_diag7(0);
> 
>     Please indent these properly too.
> 
>>  
>>  	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
>>  	   Bit 1:Enable DAC Powerdown
> 
>> Cheers
>> Dan Laird
> 
> WBR, Sergei
> 
> 
> 

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Re: [PATCH] Philips(NXP)/STB810 changes

[Ralf Baechle]

On Thu, Jun 21, 2007 at 05:37:25AM -0700, Daniel Laird wrote:

> Please find the new patch below - I hope it is following the correct rules
> now.

This is a good opportunity to advertise the checkpatch.pl script which is
part of the latest kernel once more.  For example running it against your
patch results gives:

[ralf@denk linux-queue]$ scripts/checkpatch.pl /tmp/xxx 
line over 80 characters
#107: FILE: arch/mips/philips/pnx8550/common/setup.c:117:
+                                  (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |

line over 80 characters
#112: FILE: arch/mips/philips/pnx8550/common/setup.c:122:
+                                  (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE) |

trailing whitespace
#141: 
>> +++ kernel-new/arch/mips/philips/pnx8550/common/setup.c $

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
[ralf@denk linux-queue]$ 

Re: [PATCH] Philips(NXP)/STB810 changes

[Daniel Laird]

Useful script that checkpatch.pl! 
Okay third attempt.  

Please find attached a patch that sets up the CMEM registers for PNX8550
properly:

Setup the CMEM registers for PNX8550 correctly.

Signed-off-by: Daniel Laird <daniel.j.laird@NXP.com>
---

--- kernel/include/asm-mips/mipsregs.h
+++ kernel-new/include/asm-mips/mipsregs.h 
@@ -498,6 +498,25 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the PR4450 CMEM Registers */
+#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
+#define PR4450_CMEMB_BBA     20
+#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
+#define PR4450_CMEMB_SIZE    1
+#define PR4450_CMEM_SIZE_1MB    0
+#define PR4450_CMEM_SIZE_2MB    1
+#define PR4450_CMEM_SIZE_4MB    2
+#define PR4450_CMEM_SIZE_8MB    3
+#define PR4450_CMEM_SIZE_16MB   4
+#define PR4450_CMEM_SIZE_32MB   5
+#define PR4450_CMEM_SIZE_64MB   6
+#define PR4450_CMEM_SIZE_128MB  7
+#define PR4450_CMEM_SIZE_256MB  8
+#define PR4450_CMEM_SIZE_512MB  9
+#define PR4450_CMEM_SIZE_1GB   10
+#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
+#define PR4450_CMEMB_VALID   0
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
@@ -917,6 +936,14 @@
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 
+#ifdef CONFIG_SOC_PNX8550
+#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
+#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
+
+#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
+#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
+#endif
+
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
 
--- kernel/arch/mips/philips/pnx8550/common/setup.c
+++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
@@ -75,6 +75,20 @@
 	},
 };
 
+/* Define the CMEM regions for the processor. */
+#define CMEM_VALID       (1 << PR4450_CMEMB_VALID)
+#define CMEM_REGION      (0x1be00000 & PR4450_CMEMF_BBA)
+#define MMIO_CMEM_SIZE   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE)
+#define MMIO_CMEM_ENABLE (CMEM_REGION | MMIO_CMEM_SIZE | CMEM_VALID)
+
+#define XIO_CMEM_REGION  (0x10000000 & PR4450_CMEMF_BBA)
+#define XIO_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define XIO_CMEM_ENABLE  (XIO_CMEM_REGION | XIO_CMEM_SIZE | CMEM_VALID)
+
+#define PCI_CMEM_REGION  (0x20000000 & PR4450_CMEMF_BBA)
+#define PCI_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define PCI_CMEM_ENABLE  (PCI_CMEM_REGION | PCI_CMEM_SIZE | CMEM_VALID)
+
 #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct
resource))
 
 extern struct resource pci_io_resource;
@@ -105,6 +119,19 @@
         pm_power_off = pnx8550_machine_power_off;
 
 	board_time_init = pnx8550_time_init;
+
+	/* Setup CMEM Registers */
+	/* CMEM0 = MMIO */
+	write_c0_diag4(MMIO_REGION_ENABLE);
+
+	/* CMEM1 = XIO */
+	write_c0_diag5(XIO_CMEM_ENABLE);
+
+	/* CMEM2 = PCI */
+	write_c0_diag6(PCI_CMEM_ENABLE);
+
+	/* CMEM3 = Not used */
+	write_c0_diag7(0);
 
 	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
 	   Bit 1:Enable DAC Powerdown

Attached Email:
http://www.nabble.com/file/p11246928/pnx8550_cmem_setup.patch
pnx8550_cmem_setup.patch 
Cheers
Daniel Laird
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Re: [PATCH] Philips(NXP)/STB810 changes

[Daniel Laird]

Not a good start to the day!!!

Please find the CORRECT patch below (Doh!!)

Setup the CMEM registers for PNX8550 correctly.

Signed-off-by: Daniel Laird <daniel.j.laird@NXP.com>
---

--- kernel/include/asm-mips/mipsregs.h
+++ kernel-new/include/asm-mips/mipsregs.h 
@@ -498,6 +498,25 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the PR4450 CMEM Registers */
+#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
+#define PR4450_CMEMB_BBA     20
+#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
+#define PR4450_CMEMB_SIZE    1
+#define PR4450_CMEM_SIZE_1MB    0
+#define PR4450_CMEM_SIZE_2MB    1
+#define PR4450_CMEM_SIZE_4MB    2
+#define PR4450_CMEM_SIZE_8MB    3
+#define PR4450_CMEM_SIZE_16MB   4
+#define PR4450_CMEM_SIZE_32MB   5
+#define PR4450_CMEM_SIZE_64MB   6
+#define PR4450_CMEM_SIZE_128MB  7
+#define PR4450_CMEM_SIZE_256MB  8
+#define PR4450_CMEM_SIZE_512MB  9
+#define PR4450_CMEM_SIZE_1GB   10
+#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
+#define PR4450_CMEMB_VALID   0
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
@@ -917,6 +936,14 @@
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 
+#ifdef CONFIG_SOC_PNX8550
+#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
+#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
+
+#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
+#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
+#endif
+
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
 
--- kernel/arch/mips/philips/pnx8550/common/setup.c
+++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
---
/home/laird/kernels/linux-2.6.21/arch/mips/philips/pnx8550/common/setup.c 
+++
/home/laird/ccm_wa/ipstb/ipstb/ipstb/src/open/linux/overlay/arch/mips/philips/pnx8550/common/setup.c 
@@ -75,6 +75,20 @@
 	},
 };
 
+/* Define the CMEM regions for the processor. */
+#define CMEM_VALID       (1 << PR4450_CMEMB_VALID)
+#define MMIO_CMEM_REGION (0x1be00000 & PR4450_CMEMF_BBA)
+#define MMIO_CMEM_SIZE   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE)
+#define MMIO_CMEM_ENABLE (MMIO_CMEM_REGION | MMIO_CMEM_SIZE | CMEM_VALID)
+
+#define XIO_CMEM_REGION  (0x10000000 & PR4450_CMEMF_BBA)
+#define XIO_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define XIO_CMEM_ENABLE  (XIO_CMEM_REGION | XIO_CMEM_SIZE | CMEM_VALID)
+
+#define PCI_CMEM_REGION  (0x20000000 & PR4450_CMEMF_BBA)
+#define PCI_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define PCI_CMEM_ENABLE  (PCI_CMEM_REGION | PCI_CMEM_SIZE | CMEM_VALID)
+
 #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct
resource))
 
 extern struct resource pci_io_resource;
@@ -105,6 +119,19 @@
         pm_power_off = pnx8550_machine_power_off;
 
 	board_time_init = pnx8550_time_init;
+
+	/* Setup CMEM Registers */
+	/* CMEM0 = MMIO */
+	write_c0_diag4(MMIO_CMEM_ENABLE);
+
+	/* CMEM1 = XIO */
+	write_c0_diag5(XIO_CMEM_ENABLE);
+
+	/* CMEM2 = PCI */
+	write_c0_diag6(PCI_CMEM_ENABLE);
+
+	/* CMEM3 = Not used */
+	write_c0_diag7(0);
 
 	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
 	   Bit 1:Enable DAC Powerdown

And attached below:
http://www.nabble.com/file/p11247006/pnx8550_cmem_setup.patch
pnx8550_cmem_setup.patch 



Daniel Laird wrote:
> 
> Useful script that checkpatch.pl! 
> Okay third attempt.  
> 
> Please find attached a patch that sets up the CMEM registers for PNX8550
> properly:
> 
> Setup the CMEM registers for PNX8550 correctly.
> 
> Signed-off-by: Daniel Laird <daniel.j.laird@NXP.com>
> ---
> 
> --- kernel/include/asm-mips/mipsregs.h
> +++ kernel-new/include/asm-mips/mipsregs.h 
> @@ -498,6 +498,25 @@
>  #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
>  #define MIPS_CONF_M		(_ULCAST_(1) << 31)
>  
> +/* Bits specific to the PR4450 CMEM Registers */
> +#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
> +#define PR4450_CMEMB_BBA     20
> +#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
> +#define PR4450_CMEMB_SIZE    1
> +#define PR4450_CMEM_SIZE_1MB    0
> +#define PR4450_CMEM_SIZE_2MB    1
> +#define PR4450_CMEM_SIZE_4MB    2
> +#define PR4450_CMEM_SIZE_8MB    3
> +#define PR4450_CMEM_SIZE_16MB   4
> +#define PR4450_CMEM_SIZE_32MB   5
> +#define PR4450_CMEM_SIZE_64MB   6
> +#define PR4450_CMEM_SIZE_128MB  7
> +#define PR4450_CMEM_SIZE_256MB  8
> +#define PR4450_CMEM_SIZE_512MB  9
> +#define PR4450_CMEM_SIZE_1GB   10
> +#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
> +#define PR4450_CMEMB_VALID   0
> +
>  /*
>   * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
>   */
> @@ -917,6 +936,14 @@
>  #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
>  #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
>  
> +#ifdef CONFIG_SOC_PNX8550
> +#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
> +#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
> +
> +#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
> +#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
> +#endif
> +
>  #define read_c0_debug()		__read_32bit_c0_register($23, 0)
>  #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
>  
> --- kernel/arch/mips/philips/pnx8550/common/setup.c
> +++ kernel-new/arch/mips/philips/pnx8550/common/setup.c 
> @@ -75,6 +75,20 @@
>  	},
>  };
>  
> +/* Define the CMEM regions for the processor. */
> +#define CMEM_VALID       (1 << PR4450_CMEMB_VALID)
> +#define CMEM_REGION      (0x1be00000 & PR4450_CMEMF_BBA)
> +#define MMIO_CMEM_SIZE   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE)
> +#define MMIO_CMEM_ENABLE (CMEM_REGION | MMIO_CMEM_SIZE | CMEM_VALID)
> +
> +#define XIO_CMEM_REGION  (0x10000000 & PR4450_CMEMF_BBA)
> +#define XIO_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
> +#define XIO_CMEM_ENABLE  (XIO_CMEM_REGION | XIO_CMEM_SIZE | CMEM_VALID)
> +
> +#define PCI_CMEM_REGION  (0x20000000 & PR4450_CMEMF_BBA)
> +#define PCI_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
> +#define PCI_CMEM_ENABLE  (PCI_CMEM_REGION | PCI_CMEM_SIZE | CMEM_VALID)
> +
>  #define STANDARD_IO_RESOURCES
> (sizeof(standard_io_resources)/sizeof(struct resource))
>  
>  extern struct resource pci_io_resource;
> @@ -105,6 +119,19 @@
>          pm_power_off = pnx8550_machine_power_off;
>  
>  	board_time_init = pnx8550_time_init;
> +
> +	/* Setup CMEM Registers */
> +	/* CMEM0 = MMIO */
> +	write_c0_diag4(MMIO_REGION_ENABLE);
> +
> +	/* CMEM1 = XIO */
> +	write_c0_diag5(XIO_CMEM_ENABLE);
> +
> +	/* CMEM2 = PCI */
> +	write_c0_diag6(PCI_CMEM_ENABLE);
> +
> +	/* CMEM3 = Not used */
> +	write_c0_diag7(0);
>  
>  	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
>  	   Bit 1:Enable DAC Powerdown
> 
> Attached Email:
>  http://www.nabble.com/file/p11246928/pnx8550_cmem_setup.patch
> pnx8550_cmem_setup.patch 
> Cheers
> Daniel Laird
> 
-- 
View this message in context: http://www.nabble.com/-PATCH--Philips%28NXP%29-STB810-changes-tf3957431.html#a11247006
Sent from the linux-mips main mailing list archive at Nabble.com.

Re: [PATCH] Philips(NXP)/STB810 changes

[Ralf Baechle]

On Thu, Jun 21, 2007 at 11:41:10PM -0700, Daniel Laird wrote:

> Please find the CORRECT patch below (Doh!!)
> 
> Setup the CMEM registers for PNX8550 correctly.
> 
> Signed-off-by: Daniel Laird <daniel.j.laird@NXP.com>

Hunk #2 succeeded at 938 (offset 2 lines).
patching file arch/mips/philips/pnx8550/common/setup.c
patch: **** malformed patch at line 118: resource))

  Ralf

Re: [PATCH] Philips(NXP)/STB810 changes

[Daniel Laird]

[-- Attachment #1: Type: text/plain, Size: 203 bytes --]

Have applied the patch below to the latest 2.6.22.RC6 tree (from 
linux-mips.org)
Still did not see the problems you are seeing. 

I hope this solves the problem (otherise I am confused!!)

Daniel Laird

[-- Attachment #2: pnx8550_cmem_setup_updated.patch --]
[-- Type: text/plain, Size: 3398 bytes --]

diff -urN linux-2.6.22-rc6/arch/mips/philips/pnx8550/common/setup.c linux-2.6.22-rc6-new/arch/mips/philips/pnx8550/common/setup.c
--- linux-2.6.22-rc6/arch/mips/philips/pnx8550/common/setup.c	2007-06-25 11:12:54.000000000 +0100
+++ linux-2.6.22-rc6-new/arch/mips/philips/pnx8550/common/setup.c	2007-06-27 15:07:29.000000000 +0100
@@ -75,6 +75,20 @@
 	},
 };
 
+/* Define the CMEM regions for the processor. */
+#define CMEM_VALID       (1 << PR4450_CMEMB_VALID)
+#define MMIO_CMEM_REGION (0x1be00000 & PR4450_CMEMF_BBA)
+#define MMIO_CMEM_SIZE   (PR4450_CMEM_SIZE_2MB << PR4450_CMEMB_SIZE)
+#define MMIO_CMEM_ENABLE (MMIO_CMEM_REGION | MMIO_CMEM_SIZE | CMEM_VALID)
+
+#define XIO_CMEM_REGION  (0x10000000 & PR4450_CMEMF_BBA)
+#define XIO_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define XIO_CMEM_ENABLE  (XIO_CMEM_REGION | XIO_CMEM_SIZE | CMEM_VALID)
+
+#define PCI_CMEM_REGION  (0x20000000 & PR4450_CMEMF_BBA)
+#define PCI_CMEM_SIZE    (PR4450_CMEM_SIZE_128MB << PR4450_CMEMB_SIZE)
+#define PCI_CMEM_ENABLE  (PCI_CMEM_REGION | PCI_CMEM_SIZE | CMEM_VALID)
+
 #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
 
 extern struct resource pci_io_resource;
@@ -106,6 +120,19 @@
 
 	board_time_init = pnx8550_time_init;
 
+	/* Setup CMEM Registers */
+	/* CMEM0 = MMIO */
+	write_c0_diag4(MMIO_CMEM_ENABLE);
+
+	/* CMEM1 = XIO */
+	write_c0_diag5(XIO_CMEM_ENABLE);
+
+	/* CMEM2 = PCI */
+	write_c0_diag6(PCI_CMEM_ENABLE);
+
+	/* CMEM3 = Not used */
+	write_c0_diag7(0);
+
 	/* Clear the Global 2 Register, PCI Inta Output Enable Registers
 	   Bit 1:Enable DAC Powerdown
 	  -> 0:DACs are enabled and are working normally
diff -urN linux-2.6.22-rc6/include/asm-mips/mipsregs.h linux-2.6.22-rc6-new/include/asm-mips/mipsregs.h
--- linux-2.6.22-rc6/include/asm-mips/mipsregs.h	2007-06-25 11:12:54.000000000 +0100
+++ linux-2.6.22-rc6-new/include/asm-mips/mipsregs.h	2007-06-27 15:07:29.000000000 +0100
@@ -498,6 +498,25 @@
 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
 
+/* Bits specific to the PR4450 CMEM Registers */
+#define PR4450_CMEMF_BBA     (_ULCAST_(2047) << 20)
+#define PR4450_CMEMB_BBA     20
+#define PR4450_CMEMF_SIZE    (_ULCAST_(15) << 1)
+#define PR4450_CMEMB_SIZE    1
+#define PR4450_CMEM_SIZE_1MB    0
+#define PR4450_CMEM_SIZE_2MB    1
+#define PR4450_CMEM_SIZE_4MB    2
+#define PR4450_CMEM_SIZE_8MB    3
+#define PR4450_CMEM_SIZE_16MB   4
+#define PR4450_CMEM_SIZE_32MB   5
+#define PR4450_CMEM_SIZE_64MB   6
+#define PR4450_CMEM_SIZE_128MB  7
+#define PR4450_CMEM_SIZE_256MB  8
+#define PR4450_CMEM_SIZE_512MB  9
+#define PR4450_CMEM_SIZE_1GB   10
+#define PR4450_CMEMF_VALID   (_ULCAST_(1) << 0)
+#define PR4450_CMEMB_VALID   0
+
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
@@ -919,6 +938,14 @@
 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
 
+#ifdef CONFIG_SOC_PNX8550
+#define read_c0_diag6()		__read_32bit_c0_register($22, 6)
+#define write_c0_diag6(val)	__write_32bit_c0_register($22, 6, val)
+
+#define read_c0_diag7()		__read_32bit_c0_register($22, 7)
+#define write_c0_diag7(val)	__write_32bit_c0_register($22, 7, val)
+#endif
+
 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)